JP3234002B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of selectively forming a metal silicide on a silicon-based semiconductor region.

[0002]

2. Description of the Related Art In a conventional method of manufacturing a semiconductor device of this kind, a complementary MIS (Metal Insulator Semiconducto
r) The case of a transistor will be described as an example.

In recent years, MIS transistor integrated circuits using silicon (Si) have been miniaturized and highly integrated.
Here, as the miniaturization of the integrated circuit progresses, the contact hole between the source / drain diffusion layer and the metal wiring also becomes smaller, and the contact resistance increases. Further, since the source / drain diffusion layers become shallower, the sheet resistance of these diffusion layers also increases. Then, the increase in the contact resistance and the increase in the sheet resistance decrease the current driving force of the MIS transistor and cause the operation speed of the semiconductor device to deteriorate.

[0004] Further, the gate length of the gate electrode is also reduced due to miniaturization of the integrated circuit. As a result, the resistance of the gate electrode increases, and the charging time of the gate electrode becomes longer. This also causes the operating speed of the semiconductor device to deteriorate.

In general, the deterioration of the operation speed due to the increase in the resistance of the source / drain diffusion layer and the gate electrode cannot be ignored when the source, drain and gate electrodes are smaller than 10 μm.

On the other hand, in order to reduce the resistance as described above, a metal silicide is formed on the source / drain diffusion layer and the gate electrode by a salicide process (a process of forming a silicide by self-alignment). Semiconductor devices are known.

[0007] Such a metal silicide is formed as follows.

First, an oxide film 61 for element isolation, a source diffusion layer 62a, and a drain diffusion layer 62 are formed on a silicon substrate 60.
b, after forming the gate oxide film 64 and the gate electrode 63, a metal (here, titanium (Ti)) 65 is deposited on the entire surface of the silicon substrate (see FIG. 6A).

Thereafter, by annealing at 750 ° C., the Ti film 65 reacts with the source diffusion layer 62a, the drain diffusion layer 62b, and the gate electrode 63, respectively. Thus, a TiSi ₂ (C49) layer 66, which is a titanium silicide layer having a relatively high resistance, is formed (see FIG. 3B).

The Ti which did not become TiSi ₂ (C 49) 66 is removed in a solution containing aqueous hydrogen peroxide (H ₂ O ₂ ) (see FIG. 3C).

Further, by performing annealing at 600 ° C., a phase transition occurs in the entire region of the TiSi ₂ (C49) layer 66, and TiSi ₂ (C
54) A layer 67 is obtained (see FIG. 4D).

[0012] By forming the TiSi ₂ (C54) layer 67 in this manner the source / drain diffusion layer and the gate electrode reduces the resistance in these parts, to improve the operating speed of the semiconductor device it can.

[0013]

According to the above-described silicide formation process, when the source, drain and gate electrodes are larger than a predetermined size (for example, 1 μm), a good metal silicide layer can be formed. This is effective in reducing the resistance of these components.

However, if the size of each of these electrodes is smaller than the above-mentioned predetermined size, the metal silicide may be formed by the conventional process as described above if the miniaturization of the semiconductor integrated circuit is further advanced. In addition, the resistance of the source / drain diffusion layer and the gate electrode could not be reduced.

This is not for the reason that the silicide layer is hardly formed on the source / drain diffusion layers or the gate electrode, but for the reason that the thinning of the electrode or the like makes the phase transition hard to occur. (References: JB, Losky et al., IEEE Transaction on E
lectron Devices, Vol38 No2 pp262-269). That is,
As described above, TiSi ₂ (C49) is replaced by TiSi ₂ (C54).
When the TiSi ₂ (C49) remains in the TiSi ₂ (C54) layer 67 on the source / drain diffusion layer and the gate electrode, the resistance of each of these parts is reduced. It cannot be reduced sufficiently.

The reason why the phase transition is less likely to occur as the electrode or the like becomes thinner is not clear, but when the silicide is titanium silicide, the following hypothesis is known (see the same reference). .

FIG. 7 is a perspective view showing a part of the structure of the MIS transistor. In the figure, (a) shows a gate electrode 71.
(B) shows a case where the width of the gate electrode 71 is narrow.

From the TiSi ₂ (C49) layer 66, TiSi ₂
It is believed that the phase transition to the (C54) layer 67 does not occur entirely entirely from the beginning. That is, although the reason is not clear, when annealing is started, first, Ti
It is considered that a scattered TiSi ₂ (C54) region 68 as shown in FIG. 7A is generated in the Si ₂ (C49) layer 66 (hereinafter, the dotted TiSi ₂ (C54) region 68).
Is referred to as "nucleus"). Then, as shown by arrows and dotted lines in FIG.
₂ gradually spreads in the (C49) layer 66, and finally all of the titanium silicide undergoes a phase transition to form TiSi ₂ (C5
4) It becomes layer 67.

Here, it is considered that the density of the "nuclei" does not change depending on the width of the gate electrode 63. Therefore, as shown in FIG.
Is narrow, the number of “nuclei” in the TiSi ₂ (C49) layer 66 decreases.

According to the above hypothesis, when the electrode or the like is made thin, the metal nucleus (titanium silicide in the above example) on this electrode completely undergoes a phase transition, so that a "nucleus" is formed. It is considered effective to increase the density at which the generation occurs. In other words, the density of "nuclei" is increased by the amount of thinning of electrodes, etc., and "nuclei" in metal silicide are increased.
It is considered that by not reducing the number of the compounds, it is possible to prevent the phase transition of the metal silicide from becoming difficult to occur.

On the other hand, as a solution when the phase transition of the metal silicide is unlikely to occur, it is conceivable that the phase transition is promoted by increasing the annealing temperature or lengthening the annealing time.

However, if the annealing temperature is increased or the annealing time is increased, as shown in FIG. 8, impurities in the silicon substrate are likely to be re-diffused, resulting in a decrease in yield, and a reduction in the metal silicide layer. In some cases, the shape of the metal silicide layer 67 is easily changed, and the uniformity of the thickness of the metal silicide layer 67 is impaired, so that the electrode resistance may be increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and a method of manufacturing a semiconductor device capable of forming a low-resistance metal silicide on a miniaturized Si-based semiconductor region. The purpose is to provide.

The method for manufacturing a semiconductor device according to the present invention comprises:
Source / drain diffusion layers on the surface of silicon-based semiconductor region
Forming a source / drain, and forming the source / drain
Metal silicide layer forming step performed after the rain forming step
The metal silicide layer forming step, an ion implantation step of performing ion implantation on the surface of the silicon-based semiconductor region,
A metal layer forming step of forming a metal layer such that there is a portion in which a distance between a contact portion end and the surface of the silicon-based semiconductor region after the ion implantation is 1 μm or less; And a heat treatment step of subjecting the silicide layer to a heat treatment to cause a phase transition.

[0025]

In the metal silicide layer forming step including the metal layer forming step, the reaction step, the metal removing step, and the heat treatment step, ion implantation is performed at a stage before the metal layer forming step, so that the metal silicide in the heat treatment step performed thereafter is Promotes phase transition.

Further, by using ions of atoms that do not become a silicon dopant as ions to be implanted,
It does not affect the conductivity or the like of the silicon-based semiconductor region.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. In this embodiment, a MOS (Metal Oxide Semiconductor) is manufactured using the method of manufacturing a semiconductor device according to the present invention.
A case where a transistor is manufactured will be described as an example.

First, the configuration of the MOS transistor according to the present embodiment will be described with reference to FIG.

As shown in FIG. 3, the plane direction is, for example, (1).
A source diffusion region 12a and a drain diffusion region 12b are respectively formed in a region of the surface of the p-type Si substrate 10 of FIG. The source diffusion region 12a and the drain diffusion region 1
A gate electrode 13 is formed on the p-type Si substrate 10 in a region between the gate electrode 13 and the gate electrode 13 via a gate oxide film 14a.
The gate electrode side wall 1 is formed on the side surface of the gate electrode 13.
4b is formed.

The surfaces of the source diffusion region 12a, the drain diffusion region 12b, and the gate electrode 13 have T
An iSi ₂ (C54) layer 19 is formed. Then, an interlayer insulating layer 20 is formed thereon, and further, an aluminum (Al) wiring layer 21 and a passivation film 22 are formed. The source diffusion region 12a and the drain diffusion region 12b are connected to the Al wiring layer 21 via a contact hole 20a formed in the interlayer insulating layer 20.

Next, a method of manufacturing the MOS transistor shown in FIG. 1 will be described with reference to FIG.

First, an oxide film 11 for element isolation is formed on the surface of a p-type Si substrate 10.

Subsequently, an oxide film is deposited on the entire surface, and a polycrystalline Si film having a thickness of 3000 A (angstrom) is further deposited on the oxide film. Then, a gate oxide film 14a and a gate electrode 13 are formed from the oxide film and the polycrystalline Si film by a lithography process.

Next, after depositing a Si oxide film on the entire surface,
By etching back the entire surface, the gate electrode side wall 1 is formed.
4b is formed.

Arsenic (As) is applied to the entire surface at 50 keV and 5 keV.
Ion implantation at × 10 ¹⁵ cm ^-2 and nitrogen (N ₂ )
Anneal in a gas at 1000 ° C for 20 seconds to perform As
Is activated to form an n ⁺ diffusion layer (source diffusion layer 12a, drain diffusion layer 12b) 12. At this time, As ions are also implanted into the gate electrode 13, so that the polycrystalline Si film forming the gate electrode 13 is n ⁺
This results in a doped polycrystalline Si film (see FIG. 2A).

Thereafter, argon (Ar) was added to the entire surface for 3 hours.
0keV, 1 × 10 ¹⁴ by ion implantation at cm ^-2, Ar on the surface of the ^{n +} diffusion layer 12 and the gate electrode 13
An implantation layer 15 is formed (corresponding to the “ion implantation step” of the present invention. Hereinafter, the same applies in “”; see FIG.

Subsequently, a titanium (Ti) film 16 having a thickness of 300 A is deposited on the entire surface ("metal layer forming step"; see FIG. 3C).

By performing annealing at 700 ° C. for 30 seconds in N ₂ gas, a metastable metal silicide phase is formed between the upper surface of the n ⁺ diffusion layer 12 and the gate electrode 13 and the lower surface of the Ti film 16. To form a layer 17 of TiSi ₂ (C49) (“reaction step”; see FIG. 4D). At this time, the TiSi ₂ (C49) layer 17 of the Ti film 16
The unreacted portion includes the mixed layer 18 in which unreacted Ti and TiN generated by reacting with the atmospheric gas N ₂ are mixed. This mixed layer 18 is selectively removed by treatment in a solution containing aqueous hydrogen peroxide (H ₂ O ₂ ) (“metal removal step”).

[0040] 850 ° C., annealing is performed for 20 seconds, causing a phase transition to a TiSi ₂ (C49) layer 17, to form a TiSi ₂ (C54) layer 19 ( "heat treatment step"; FIG. (E) reference).

Thereafter, the interlayer insulating layer 20, the Al wiring layer 2
1. A passivation film 22 and the like are formed to obtain a MOS transistor as shown in FIG.

Next, the characteristics of the MOS transistor thus manufactured will be described with reference to FIG.

In the figure, (a) shows the n ⁺ diffusion layer 12
6 is a graph showing the relationship between the width of the sheet and the sheet resistance. As can be seen from the graph, while the MOS transistor manufactured by the conventional manufacturing method as sheet resistance width is miniaturized n ⁺ diffusion layer 12 is narrowed becomes greater, MOS transistor of this example n ⁺ Even if the width of the diffusion layer 12 is reduced, the sheet resistance remains small.

This is presumably because the resistance of the metal silicide layer (TiSi ₂ (C54) layer 19) formed by the manufacturing method according to this embodiment is low.

Although the reason why a low-resistance metal silicide layer can be obtained by the manufacturing method according to the present embodiment is not clear, it is difficult to obtain the phase by performing Ar ion implantation in advance (the above process). During the annealing (the above process) for causing the transition, the “nucleus” as described above is used.
It is considered that this is because the generation density of the particles increased. That is, when the generation density of “nuclei” increases, TiSi ₂ (C4
Since the phase transition from 9) to TiSi ₂ (C54) is easily performed, it is considered that the region which remains as TiSi ₂ (C49) without phase transition is reduced, and the resistance of the entire metal silicide layer is reduced. Is reasonable.

FIG. 3 (b) shows that A
FIG. 9 is a graph showing a change in a reverse leakage characteristic of an n ⁺ / p junction when a dose at the time of performing ion implantation of r is changed (1 × 10 ¹⁴ cm ^{−2 in the} above process). As can be seen from the graph, the greater the dose, the greater the amount of damage introduced into the junction and the greater the junction leakage. Therefore, for example, when a voltage of 3 V is applied to the n ⁺ / p junction, the leakage current is reduced to 1 nA (nano-ampere).
In order to keep the dose below, the dose needs to be 1 × 10 ¹⁴ cm ⁻² or less.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, a semiconductor device in which the resistance of the source / drain diffusion layers and the gate electrode is reduced, that is, a semiconductor device having an excellent operation speed is manufactured. can do.

(Embodiment 2) Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In this embodiment, a case where the MOS transistor as shown in FIG. 1 is manufactured by using the method of manufacturing a semiconductor device according to the present invention will be described as an example.

This embodiment is different from the first embodiment in that the ion implantation step is performed after the metal layer forming step.

Hereinafter, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIG.

In the same manner as in Example 1, the p-type Si substrate 1
After forming an oxide film 11 for element isolation on the surface of the gate electrode 0, a gate oxide film 14a, a gate electrode 13, and a gate electrode side wall 14b are formed.

Further, in the same manner as in the first embodiment, an n ⁺ diffusion layer 12 is formed, and n ⁺ doping is performed on a polycrystalline Si film for forming a gate electrode 13 (see FIG. 4A).

Then, a Ti film 16 having a thickness of 300 A (angstrom) is deposited on the entire surface ("metal layer forming step"; see FIG. 4B).

Next, argon (Ar) is ion-implanted into the entire surface at a dose of 1 × 10 ¹⁴ cm ⁻² to obtain n ⁺
Ar injection layer 1 is formed on the surface of diffusion layer 12 and gate electrode 13.
5 ("Ion implantation step"; see FIG. 3C). Here, in the case of the present embodiment, the implantation energy is set to 50 keV in order to implant Ar ions so as to peak at the interface between the surface of the ⁺ diffusion layer 12 and the gate electrode 13 and the Ti film.

Subsequently, as in the first embodiment, annealing is performed in N ₂ gas at 700 ° C. for 30 seconds to obtain n ⁺
At the interface between the diffusion layer 12 and the gate electrode 13 and the Ti film 16, TiSi ₂ (C4
9) is formed (“reaction step”; see FIG. 4D), and the mixed layer 18 of Ti and TiN formed at this time is placed in a solution containing hydrogen peroxide solution. It is selectively removed by a treatment (“metal removal step”).

[0056] Thereafter, 850 ° C., annealing is performed for 20 seconds, causing a phase transition to a TiSi ₂ (C49) layer 17, to form a TiSi ₂ (C54) layer 19 ( "heat treatment step"; FIG. ( e)).

Finally, the interlayer insulating layer 20, the Al wiring layer 2
1. A passivation film 22 and the like are formed to obtain a MOS transistor as shown in FIG.

The MOS transistor manufactured in this manner can obtain substantially the same characteristics as those in FIG.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, a semiconductor device in which the resistances of the source / drain diffusion layers and the gate electrode are reduced, that is, a semiconductor device having an excellent operation speed can be manufactured. it can.

Embodiment 3 Next, a third embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In this embodiment, a case where the MOS transistor as shown in FIG. 1 is manufactured by using the method of manufacturing a semiconductor device according to the present invention will be described as an example.

This embodiment is different from the first embodiment in that the ion implantation step is performed after the reaction step and before the heat treatment step.

Hereinafter, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIG.

In the same manner as in Example 1, the p-type Si substrate 1
After forming an oxide film 11 for element isolation on the surface of the gate electrode 0, a gate oxide film 14a, a gate electrode 13, and a gate electrode side wall 14b are formed.

Further, as in the first embodiment, an n ⁺ diffusion layer 12 is formed, and at the same time, a polycrystalline Si film for forming a gate electrode 13 is doped with n ⁺ .

Then, a Ti film 16 having a thickness of 300 A (angstrom) is deposited on the entire surface ("metal layer forming step"; see FIG. 5A).

Subsequently, as in the first embodiment, annealing is performed in N ₂ gas at 700 ° C. for 30 seconds to obtain n ⁺
Between the upper surface of the diffusion layer 12 and the gate electrode 13 and the lower surface of the Ti film 16, TiS, which is a metastable metal silicide phase, is formed.
A layer 17 of i ₂ (C49) is formed (“reaction step”), and the mixed layer 18 of Ti and TiN is selectively removed by treatment in a solution containing aqueous hydrogen peroxide (“ Metal removing step "; see FIG.

Next, argon (Ar) is applied for 30 k on the entire surface.
By ion implantation at eV, 1 × 10 ¹⁴ cm ⁻² ,
An Ar implantation layer 15 is formed in the TiSi ₂ (C49) layer 17 (“ion implantation step”; see FIG. 3C).

Thereafter, annealing is performed at 850 ° C. for 20 seconds to cause a phase transition in the TiSi ₂ (C49) layer 17 to form a TiSi ₂ (C54) layer 19 (“heat treatment step”; FIG. d)).

Finally, the interlayer insulating layer 20, the Al wiring layer 2
1. A passivation film 22 and the like are formed to obtain a MOS transistor as shown in FIG.

The MOS transistor manufactured in this manner can obtain substantially the same characteristics as those in FIG.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the resistance of the source / drain diffusion layer and the gate electrode can be reduced, and therefore, a semiconductor device having an excellent operation speed can be manufactured. it can.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and it is needless to say that the present invention can be carried out with appropriate changes within the scope of the present invention.

For example, in each of the embodiments described above, the case where an n-channel MOS transistor is manufactured by using the method of manufacturing a semiconductor device according to the present invention has been described. However, a p-channel MOS transistor or the like may be used. That is,
The present invention can be applied to any semiconductor device as long as it is a Si-based semiconductor device having a structurally thin electrode.

In each of the above embodiments, titanium silicide is used as the metal silicide. However, the present invention can be applied to other metal silicides such as cobalt silicide, nickel silicide, and platinum silicide.

Further, in each of the above-described embodiments, Ar ions are implanted in advance into the region where the metal silicide is to be formed. However, even if this implanted ion does not show conductivity when implanted into SiO _2. Any ion may be used. For example, instead of the Ar ion, helium (He), xenon (Xe), krypton (Kr), neon (Ne), radon (Rn), nitrogen (N), oxygen (O), carbon (C), silicon Ions such as (Si) may be used. However, generally, Arsen (As), boron (B), phosphorus (P), antimony (Sb), etc., which are dopants to Si, are excluded.

In addition, annealing for causing a phase transition of the metal silicide may be performed after other steps such as formation of the passivation film 22.

In addition, it goes without saying that the conditions of annealing and ion implantation are not limited to the values shown in the above-described embodiments.

[0078]

As described above in detail, according to the method of manufacturing a semiconductor device according to the present invention, a low-resistance metal silicide can be formed even on a miniaturized region.

In particular, by applying the present invention to the manufacture of a semiconductor device having a metal silicide in a source / drain diffusion layer and a gate electrode, a semiconductor device having an excellent operation speed can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a configuration of a MOS transistor manufactured by a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a process chart for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention.

3A and 3B show characteristics of a MOS transistor manufactured by the manufacturing method shown in FIG. 2; FIG. 3A is a graph showing a relationship between a width of an n ⁺ diffusion layer and a sheet resistance; 4 is a graph showing the relationship between the reverse leakage characteristic of an n ⁺ / p junction.

FIG. 4 is a process chart for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a process chart for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view schematically showing a configuration example of a conventional semiconductor device.

7A and 7B are perspective views each showing a part of a conventional semiconductor device.

FIG. 8 is a cross-sectional view schematically showing a configuration example of a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 p-type semiconductor substrate 11 element isolation oxide film 12 n ⁺ diffusion layer 12 a source diffusion region 12 b drain diffusion region 13 gate electrode 14 oxide film 14 a gate oxide film 14 b gate electrode side wall 15 Ar injection layer 16 Ti film 17 TiSi ₂ (C49 ) Layer 18 Ti / TiN mixed layer 19 TiSi ₂ (C54) layer 20 Interlayer insulating layer 21 Al wiring layer 22 Passivation film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/43 H01L 29 / 47 H01L 29/872

Claims (4)

(57) [Claims] A source / drain is provided on the surface of a silicon-based semiconductor region.
A source / drain forming step of forming an in-diffusion layer, and a metal silicide performed after the source / drain forming step
Comprising a well layer forming step, the metal silicide layer forming step, an ion implantation step of performing ion implantation into the silicon-based semiconductor region surface, the distance between the contact portions ends of the silicon-based semiconductor region surface after the ion implantation A metal layer forming step of forming a metal layer so that a portion having a thickness of 1 μm or less exists; a reaction step of reacting the silicon-based semiconductor region with the metal layer to form a metal silicide layer; A heat treatment step of causing a phase transition by applying the heat treatment. (2) Metal silicide is the source of MIS transistor
Over the source region, the drain region and the gate electrode or
2. The method according to claim 1, wherein the first surface is formed on a part of the surface.
A method for manufacturing a semiconductor device. 3. An ion implantation step in the ion implantation step.
On is the ion of an atom that is not a silicon dopant
2. The manufacturing of a semiconductor device according to claim 1, wherein
Construction method. (4) Implanted in the ion implantation step
On is helium ion, xenon ion, krypton
Ion, neon ion, radon ion, nitrogen ion, acid
Element ion, carbon ion, or silicon ion
2. The method of manufacturing a semiconductor device according to claim 1, wherein
Law.