JP3232663B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3232663B2
JP3232663B2 JP17993592A JP17993592A JP3232663B2 JP 3232663 B2 JP3232663 B2 JP 3232663B2 JP 17993592 A JP17993592 A JP 17993592A JP 17993592 A JP17993592 A JP 17993592A JP 3232663 B2 JP3232663 B2 JP 3232663B2
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JP
Japan
Prior art keywords
region
substrate
semiconductor device
defect
absorption region
Prior art date
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Expired - Fee Related
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JP17993592A
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Japanese (ja)
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JPH0629382A (en
Inventor
律夫 滝澤
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Sony Corp
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Sony Corp
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Publication of JPH0629382A publication Critical patent/JPH0629382A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、各種半導体メモリ等の
異種導電性領域のみにより素子分離がなされる半導体装
置の製造方法に係わる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which elements are separated only by different conductive regions such as various types of semiconductor memories.

【0002】[0002]

【従来の技術】現在、半導体装置における素子分離はS
i基板上に部分的に熱酸化を生じさせて形成するLOC
OS(Local Oxidation of Silicon)によって行う構成が
主流となっている。例えばDRAM(ダイナミック・ラ
ンダム・アクセス・メモリ)やSRAM(スタティック
・ランダム・アクセス・メモリ)、またCCD(電荷結
合デバイス)などのあらゆる素子においてLOCOSに
よる素子分離が行われている。
2. Description of the Related Art At present, element isolation in a semiconductor device is S
LOC formed by causing partial thermal oxidation on i-substrate
A configuration performed by an OS (Local Oxidation of Silicon) has become mainstream. For example, element isolation by LOCOS is performed in all elements such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and CCD (Charge Coupled Device).

【0003】しかしながらこの熱酸化によるLOCOS
分離は、SiO2 膜のエッジ部分いわゆるバーズビーク
に歪みが発生し、重金属やアルカリ金属等の不純物が蓄
積されやすく、GR(Generation and Recombination)
電流の増大化の原因となることが指摘されている(例え
ばA.Ohsawa,R.Takizawa et al.,Semiconductor Sili-co
n 1990,p601(1990). )。
However, LOCOS due to this thermal oxidation
In the separation, distortion occurs at an edge portion of the SiO 2 film, that is, a bird's beak, and impurities such as heavy metals and alkali metals are easily accumulated, so that GR (Generation and Recombination) is performed.
It has been pointed out that this causes an increase in current (eg, A. Ohsawa, R. Takizawa et al., Semiconductor Sili-co
n 1990, p601 (1990).

【0004】従って、例えばGR電流や汚染に極めて影
響を受け易いCCDにおいては、LOCOSの代わりに
異種導電性領域いわゆるチャネルストッパー領域のみを
用いて素子分離を行う場合が多い。
[0004] Therefore, for example, in a CCD which is extremely susceptible to GR current and contamination, element isolation is often performed by using only a different conductive region, that is, a channel stopper region, instead of the LOCOS.

【0005】そしてこの場合、製造工程中の汚染対策と
しては、基板の一部に欠陥吸収領域を設けて汚染や欠陥
を除去するいわゆるゲッタリングが行われている。この
ゲッタリグは、Na,K等のアルカリ金属やFe,Cu
等の重金属などの不純物或いは結晶欠陥などを、高温処
理によって素子の活性領域外に設けた欠陥吸収領域に偏
析させることによって取り除くプロセスを示す。
In this case, as a countermeasure against contamination during the manufacturing process, so-called gettering for removing contamination and defects by providing a defect absorption region in a part of the substrate is performed. This getter rig is made of alkali metals such as Na and K, Fe, Cu
This is a process for removing impurities such as heavy metals and crystal defects, etc., by segregating in a defect absorption region provided outside the active region of the element by high-temperature treatment.

【0006】このゲッタリング方法としては、例えば基
板の裏面に多結晶Si領域を形成したり、リンを拡散さ
せてリンガラス層を形成する等して欠陥吸収領域を構成
するとか、または予め酸素を比較的高濃度含有する基板
を用いて、高温熱処理を施して表面の酸素をアウトディ
フュージョンさせ、基板内部に残留する酸素を熱処理に
より析出させるいわゆるイントリンシックゲッタリング
(IG)等が行われている。このIGによる場合、素子
を形成する表面層は酸素の析出も結晶欠陥もないデニュ
ーデッドゾーンとなり、一方基板内部には酸素の析出物
と結晶欠陥が高密度に形成され、これらがゲッタリング
効果をもつ。
As the gettering method, for example, a polycrystalline Si region is formed on the back surface of the substrate, a phosphorus absorption layer is formed by diffusing phosphorus to form a defect absorbing region, or oxygen is previously formed. A so-called intrinsic gettering (IG) or the like is performed in which a high-temperature heat treatment is performed on a substrate containing a relatively high concentration to out-diffuse oxygen on the surface and oxygen remaining in the substrate is precipitated by the heat treatment. In the case of this IG, the surface layer forming the element becomes a denuded zone where neither oxygen precipitation nor crystal defects occur, while oxygen precipitates and crystal defects are formed at high density inside the substrate, and these have a gettering effect. With.

【0007】これら従来のゲッタリング法では、素子活
性領域と上述の欠陥吸収領域との間隔が近いとリーク電
流発生の恐れがあることから、基板の裏面に形成する場
合は約数百μm、イントリンシックゲッタリングの場合
でも10〜30μm程度と比較的離間させて設けてお
り、充分効果的なゲッタリングを行うことが難しい。
In these conventional gettering methods, if the distance between the element active region and the above-mentioned defect absorption region is short, a leak current may occur. Even in the case of trinic gettering, it is provided at a relatively large distance of about 10 to 30 μm, and it is difficult to perform sufficiently effective gettering.

【0008】更に、現在半導体装置の製造に当たってそ
のプロセスの低温化が進められており、今後益々汚染不
純物のプロセス中の拡散長が短くなってゲッタリング効
果が低下するという問題がある。
Further, at the time of lowering the temperature of the process in the manufacture of semiconductor devices, there is a problem that the diffusion length of contaminant impurities during the process becomes shorter and the gettering effect is reduced.

【0009】[0009]

【発明が解決しようとする課題】本発明は、上述したよ
うな半導体装置の特に異種導電性領域により素子分離を
行う半導体装置において、欠陥吸収領域をより素子活性
領域近傍に形成してそのゲッタリング効果を充分得ると
共に、この欠陥吸収領域自身がリーク電流の発生源とな
らない構成とした半導体装置の製造方法を提供すること
を目的とする。
SUMMARY OF THE INVENTION The present invention relates to a semiconductor device as described above, in particular, in a semiconductor device in which element isolation is performed by using different kinds of conductive regions, a defect absorption region is formed closer to the element active region and the gettering is performed. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the effect is sufficiently obtained and the defect absorption region itself does not become a source of leakage current.

【0010】[0010]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、異種導電性領域のみによって素子分離を
行う半導体装置の製造方法において、基板上に欠陥吸収
領域を形成した後、この欠陥吸収領域を覆うようにこの
基板とは別体の基板を直接接合により接合させて、異種
導電性領域を形成すべき領域の深部直下のみに欠陥吸収
領域を形成する。
According to a method of manufacturing a semiconductor device according to the present invention, a method of manufacturing a semiconductor device in which element isolation is performed only by using different types of conductive regions is performed. A substrate separate from the substrate is directly bonded so as to cover the absorption region, and a defect absorption region is formed only immediately below a deep portion of a region where a heterogeneous conductive region is to be formed.

【0011】[0011]

【作用】本発明の半導体装置の製造方法によれば、欠陥
吸収領域を形成した後、基板を直接接合により接合させ
るものであり、この場合接合後に、この基板の裏面側か
ら研削及び研磨等の処理を行うことによって、接合した
基板の表面即ち素子活性領域から欠陥吸収領域までの間
隔を所望の距離に選定することができ、リーク電流を発
生することなく充分なゲッタリング効果が得られる半導
体装置を形成することができる。
According to the method of manufacturing a semiconductor device of the present invention, the substrate is bonded by direct bonding after forming the defect absorption region. In this case, after bonding, grinding and polishing are performed from the back side of the substrate. By performing the processing, a desired distance can be selected from the surface of the bonded substrate, that is, the distance from the element active region to the defect absorption region, and a sufficient gettering effect can be obtained without generating a leak current. Can be formed.

【0012】[0012]

【実施例】以下、本発明半導体装置の製造方法の実施例
を図1〜図3を参照して詳細に説明する。この場合、C
CD撮像素子に適用した例を示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to FIGS. In this case, C
An example in which the present invention is applied to a CD image sensor will be described.

【0013】図1は、本発明に係るCCD撮像素子の一
例を示す。同図において、1はCZ(チョクラルスキ
ー)法により形成した例えばn型のSi等より成る抵抗
率約50Ω・cmの基板で、この上に高濃度の例えばp
型のボロン等のイオン注入によるチャネルストッパー領
域即ち異種導電性領域3が、その略線的拡大平面図を図
2に示すように、受光領域9及び垂直シフトレジスタ部
10とを囲むように例えば枡目状に形成されて素子分離
が行われる。この受光領域9には、基板1とは逆導電型
即ちこの場合p型の低濃度の不純物が注入されてキャリ
ア発生領域4が形成される。そしてこの上にSiO2
より成る絶縁膜5を介して多結晶Si等より成るゲート
電極6及びAl等より成る配線8が、図2において上下
方向に延長して形成され、垂直シフトレジスタ部10が
構成される。7はPSG(リンシリケートガラス)等よ
り成る層間絶縁膜を示す。
FIG. 1 shows an example of a CCD image pickup device according to the present invention. Referring to FIG. 1, reference numeral 1 denotes a substrate made of, for example, n-type Si or the like having a resistivity of about 50 Ω · cm formed by a CZ (Czochralski) method and having a high concentration of, for example, p
As shown in FIG. 2, a channel stopper region formed by ion implantation of boron or the like, that is, a heterogeneous conductive region 3 is, for example, a square so as to surround the light receiving region 9 and the vertical shift register unit 10. The elements are formed in an eye shape to perform element isolation. Into the light receiving region 9, a low-concentration impurity of a conductivity type opposite to that of the substrate 1, that is, a p-type impurity in this case is implanted to form the carrier generation region 4. On this, a gate electrode 6 made of polycrystalline Si or the like and a wiring 8 made of Al or the like are formed so as to extend vertically in FIG. 2 via an insulating film 5 made of SiO 2 or the like. Is configured. Reference numeral 7 denotes an interlayer insulating film made of PSG (phosphosilicate glass) or the like.

【0014】そして特にこの場合、異種導電性領域3の
深部直下のみに深さdが2〜5μmの範囲にわたって欠
陥吸収領域2が選択的に形成される。このように、欠陥
吸収領域2を基板表面の素子活性領域この場合受光領域
9及び垂直シフトレジスタ部10に近接して設ける構成
とすることから、ゲッタリング効果を充分に得ることが
できて、従来のCCD素子に比し汚染に強く、CCD撮
像素子で一般に問題となっているGR電流の発生による
白キズ欠陥の発生を低減化することができる。この場
合、従来の半導体装置と同様に基板の裏面に欠陥吸収領
域を設けるとか、イントリンシックゲッタリングを組み
合わせることによって、更にゲッタリング効果を向上さ
せることができる。
In particular, in this case, the defect absorbing region 2 is selectively formed only under the deep portion of the heterogeneous conductive region 3 over a range of the depth d of 2 to 5 μm. As described above, since the defect absorption region 2 is provided close to the element active region on the substrate surface, in this case, the light receiving region 9 and the vertical shift register portion 10, the gettering effect can be sufficiently obtained, The white spot defect due to the generation of the GR current, which is more resistant to contamination than the CCD element and is generally a problem in the CCD image sensor, can be reduced. In this case, the gettering effect can be further improved by providing a defect absorption region on the back surface of the substrate or combining intrinsic gettering as in the conventional semiconductor device.

【0015】次に、このような欠陥吸収領域の形成方法
の一例を図3A及びBを参照して詳細に説明する。この
場合、Si基板の直接接合技術(例えば「新保,応用物
56,337(1987) 」)を応用した例で、図3Aに示すよ
うに対のSi基板1A及び1Bを用意し、その一方の基
板1A上に選択的に溝11を形成して、例えば多結晶S
iをCVD等により被着した後表面をエッチバック等に
より平坦化して、欠陥吸収領域2を形成する。この場
合、多結晶Siの代わりにSiO2 やSi3 4膜を形
成しても良く、またレーザ光を基板1Aの表面1ASに
選択的に照射して局所的に多結晶Siを形成することも
できる。また高濃度のイオン注入により欠陥を形成する
こともできる。
Next, an example of a method for forming such a defect absorption region will be described in detail with reference to FIGS. 3A and 3B. In this case, direct bonding technique of the Si substrate (e.g., "Shimbo, Applied Physics 56, 337 (1987)") in the example that applies, prepared Si substrate 1A and 1B of the pair, as shown in Figure 3A, one of its A groove 11 is selectively formed on the substrate 1A, and for example, a polycrystalline S
After depositing i by CVD or the like, the surface is flattened by etch back or the like to form a defect absorption region 2. In this case, a SiO 2 or Si 3 N 4 film may be formed instead of the polycrystalline Si, and the surface 1AS of the substrate 1A is selectively irradiated with a laser beam to locally form the polycrystalline Si. Can also. Defects can also be formed by high-concentration ion implantation.

【0016】そしてこの後、基板1Aの表面1AS及び
他方の基板1Bの表面1BSに鏡面加工を施して矢印c
で示すように重ね合わせ、1100℃、1時間程度のア
ニールを施すことによって図3Bに示すように基板1A
及び1Bを接合することができる。或いは表面1AS及
び1BSに親水性処理を施した後これらを重ね合わせ、
酸素中1200℃程度のアニールにより接合することも
できる。また、静電圧着を行う場合はより簡便に強固な
密着力を得ることができる。
Thereafter, the surface 1AS of the substrate 1A and the surface 1BS of the other substrate 1B are mirror-finished to produce an arrow c.
3A, the substrates 1A and 1A are annealed at about 1 hour, respectively.
And 1B can be joined. Alternatively, after subjecting surfaces 1AS and 1BS to hydrophilic treatment, they are superimposed,
The bonding can also be performed by annealing at about 1200 ° C. in oxygen. In the case of performing the electrostatic pressure bonding, a strong adhesion can be obtained more easily.

【0017】このとき加熱処理によって欠陥吸収領域2
この場合多結晶Siと、周囲の基板材料即ちSiとの熱
膨張係数の違いによって図3Bにおいて斜線を付して示
すようにその界面に転位欠陥が生じ、これらにより欠陥
吸収領域2が構成される。
At this time, the defect absorption region 2
In this case, due to the difference in the thermal expansion coefficient between the polycrystalline Si and the surrounding substrate material, ie, Si, dislocation defects occur at the interface as shown by hatching in FIG. 3B, and these form the defect absorption region 2. .

【0018】接合後、基板1A又は1B、例えば基板1
Bを研削及び研磨によって厚さtを2μm程度として薄
膜化し、この欠陥吸収領域2上に前述の図1において説
明したように、欠陥吸収領域2の直上に異種導電性領域
を形成すると共に、更にキャリア発生領域、ゲート電極
等を形成してCCD撮像素子を構成する。
After bonding, the substrate 1A or 1B, for example, the substrate 1
B is thinned to a thickness t of about 2 μm by grinding and polishing, and a different kind of conductive region is formed immediately above the defect absorption region 2 on the defect absorption region 2 as described with reference to FIG. A CCD image pickup device is formed by forming a carrier generation region, a gate electrode, and the like.

【0019】この場合、多結晶Siや、SiO2 或いは
Si3 4 膜とSi基板との界面は、上述したように熱
膨張係数のちがいによって応力が発生し歪みや結晶転移
等の欠陥を形成するので、充分なゲッタリング効果を得
ることができると共に、上述したように例えば表面から
2μm程度の深さとする等任意の深さの領域に欠陥吸収
領域2を形成することができることから、より効果的に
ゲッタリングを行うことができる。
In this case, stress is generated at the interface between the polycrystalline Si or SiO 2 or Si 3 N 4 film and the Si substrate due to the difference in the coefficient of thermal expansion, and defects such as distortion and crystal transition are formed. Therefore, a sufficient gettering effect can be obtained, and the defect absorption region 2 can be formed at an arbitrary depth, for example, at a depth of about 2 μm from the surface as described above. Gettering can be performed effectively.

【0020】尚、この例においては基板1Aに埋込みに
より欠陥吸収領域2を設けたが、他方の基板1B上、或
いは両基板1A及び1B共に欠陥吸収領域2を形成して
も良い。
In this example, the defect absorbing region 2 is provided by embedding in the substrate 1A. However, the defect absorbing region 2 may be formed on the other substrate 1B or both the substrates 1A and 1B.

【0021】図4は、上述の欠陥吸収領域の形成方法の
比較例を示す。本例は、高エネルギーイオン注入法によ
り欠陥吸収領域を形成する場合である。例えばCZ法に
より形成した酸素を含有するSiより成る基板1に、異
種導電性領域この場合チャネルストッパー領域を形成す
る前に、この部分の深部直下に歪み発生用不純物を矢印
Iで示すようにイオン注入する。この例においては、レ
ジストの厚さを通常のイオン注入の際の厚さに比し大と
し、約4μmの厚さとして露光現像によりパターニング
を行った後、カーボンを2MeVで1×1015cm-2
密度で注入し、1000℃60分の再結晶化アニールを
施して欠陥吸収領域2を形成した。この結果、表面から
の深さdが約3μmの領域に欠陥吸収領域2が形成さ
れ、これより表面側においては欠陥が発生していないこ
とを電子顕微鏡による観察を行って確認した。
FIG. 4 shows a comparative example of a method for forming the above-described defect absorption region. In this example, a defect absorption region is formed by a high energy ion implantation method. For example, before forming a heterogeneous conductive region, in this case, a channel stopper region, on a substrate 1 made of oxygen-containing Si formed by the CZ method, a strain-generating impurity is ionized as indicated by an arrow I just below the deep portion of this portion. inject. In this example, the thickness of the resist is determined greater than the thickness at the time of the conventional ion implantation, approximately after patterned by exposure and development the thickness of 4μm, 1 × 10 15 cm carbon at 2 MeV - Implantation was performed at a density of 2 and recrystallization annealing was performed at 1000 ° C. for 60 minutes to form a defect absorption region 2. As a result, it was confirmed by observation with an electron microscope that a defect absorption region 2 was formed in a region having a depth d of about 3 μm from the surface and no defect was generated on the surface side.

【0022】この比較例においては、CZ法により形成
されたSi基板を用いており、この場合酸素が数十pp
m(例えば30ppm程度)含有されるため、この基板
1に不純物を注入すると酸素が析出して、前述のIG
(イントリンシックゲッタリング)と同様の作用により
ゲッタリング効果を得ることができる。
In this comparative example, a Si substrate formed by the CZ method is used.
m (for example, about 30 ppm), oxygen is precipitated when impurities are implanted into the substrate 1 and the above-described IG
A gettering effect can be obtained by the same operation as (intrinsic gettering).

【0023】尚、上述の比較例においてはイオン種とし
てカーボンを用いたが、その他p型の材料としてはB
(ボロン)、Al、Ga等、またn型の材料としてはP
(りん)、As、Sb等を用いることができ、また中性
の欠陥吸収領域を形成する場合は酸素、Ge等種々の材
料を用いることができる。更に、基板1はCZ法に限る
ことなくMCZ(magnetic-field-applied Czochralsk
i)法により形成したSi基板等を用いることもでき
る。
Although carbon was used as the ion species in the comparative example, B was used as the other p-type material.
(Boron), Al, Ga, etc., and n-type material is P
(Phosphorus), As, Sb, etc. can be used, and when forming a neutral defect absorption region, various materials such as oxygen and Ge can be used. Further, the substrate 1 is not limited to the CZ method, and may be a magnetic-field-applied CZ
An Si substrate or the like formed by the i) method can also be used.

【0024】本発明に係る半導体装置の製造方法は、上
述の実施例に限定されることなく、その他種々の材料構
成を採り得ることはいうまでもない。
The method of manufacturing a semiconductor device according to the present invention is not limited to the above-described embodiment, and it goes without saying that various other material configurations can be adopted.

【0025】[0025]

【発明の効果】上述したように、本発明の半導体装置の
製造方法によれば、欠陥吸収領域の深さを制御性よく形
成することができて、充分なゲッタリング効果を得る半
導体装置を得ることができる。
As described above, according to the method for manufacturing a semiconductor device of the present invention, the depth of the defect absorption region can be formed with good controllability, and a semiconductor device having a sufficient gettering effect can be obtained. be able to.

【0026】このようにして得られた半導体装置は、素
子活性領域から離間することなく、またリーク電流を発
生させることなく欠陥吸収領域を設けることから、充分
なゲッタリング効果を得ることができる。特に今後装置
の低温プロセス化によって金属不純物の拡散長が小とな
る場合においても、充分ゲッタリングを行うことができ
る。
In the semiconductor device thus obtained, a sufficient gettering effect can be obtained because the defect absorbing region is provided without being separated from the element active region and without generating a leak current. In particular, even if the diffusion length of metal impurities becomes small due to the future low-temperature processing of the device, gettering can be sufficiently performed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に適用される半導体装置の一例の要部の
略線的拡大断面図である。
FIG. 1 is a schematic enlarged cross-sectional view of a main part of an example of a semiconductor device applied to the present invention.

【図2】図1の半導体装置の要部の略線的拡大平面図で
ある。
FIG. 2 is a schematic enlarged plan view of a main part of the semiconductor device of FIG. 1;

【図3】本発明に係る半導体装置の製造方法の一例を示
す製造工程図である。
FIG. 3 is a manufacturing process diagram showing an example of a method for manufacturing a semiconductor device according to the present invention.

【図4】比較例に係る半導体装置の製造方法を示す製造
工程図である。
FIG. 4 is a manufacturing process diagram showing a method for manufacturing a semiconductor device according to a comparative example.

【符号の説明】[Explanation of symbols]

1 基板 2 欠陥吸収領域 3 異種導電性領域 4 キャリア発生領域 6 ゲート電極 9 受光領域 10 垂直シフトレジスタ部 DESCRIPTION OF SYMBOLS 1 Substrate 2 Defect absorption area 3 Heterogeneous conductive area 4 Carrier generation area 6 Gate electrode 9 Light receiving area 10 Vertical shift register section

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 異種導電性領域のみによって素子分離を
行う半導体装置の製造方法において、 基板上に欠陥吸収領域を形成した後、上記欠陥吸収領域
を覆うように上記基板とは別体の基板を直接接合により
接合させて、上記異種導電性領域を形成すべき領域の深
部直下のみに上記欠陥吸収領域を形成することを特徴と
する半導体装置の製造方法。
In a method of manufacturing a semiconductor device in which element isolation is performed only by using different types of conductive regions, a defect absorbing region is formed on a substrate, and then a substrate separate from the substrate is formed so as to cover the defect absorbing region. A method of manufacturing a semiconductor device, wherein the defect absorption region is formed only directly below a deep portion of a region where the heterogeneous conductive region is to be formed by direct bonding.
JP17993592A 1992-07-07 1992-07-07 Method for manufacturing semiconductor device Expired - Fee Related JP3232663B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17993592A JP3232663B2 (en) 1992-07-07 1992-07-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17993592A JP3232663B2 (en) 1992-07-07 1992-07-07 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0629382A JPH0629382A (en) 1994-02-04
JP3232663B2 true JP3232663B2 (en) 2001-11-26

Family

ID=16074514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17993592A Expired - Fee Related JP3232663B2 (en) 1992-07-07 1992-07-07 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3232663B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006253715A (en) * 1995-04-14 2006-09-21 Sharp Corp Semiconductor apparatus
JP4991457B2 (en) * 2007-09-04 2012-08-01 キヤノン株式会社 Image forming apparatus, information processing method in image forming apparatus, computer-readable storage medium, and computer program
JP6947273B1 (en) 2020-10-15 2021-10-13 荒川化学工業株式会社 Thermosetting coating agent, cured product, laminate and its manufacturing method
JP2022137861A (en) 2021-03-09 2022-09-22 荒川化学工業株式会社 Surface protective coating agent, cured product and laminate

Also Published As

Publication number Publication date
JPH0629382A (en) 1994-02-04

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