JP3230172B2 - Serial synchronization protection circuit for parallel data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit test between communication devices and a circuit test for these communication devices themselves, in order to prevent error detection and error synchronization of a test signal. And a serial data protection circuit for parallel data.

[0002]

BACKGROUND ART FIG. 8 is an explanatory diagram showing an error detection circuit using a synchronous protection circuit this type of conventional generator polynomial X ¹⁵
9 shows an example of an error detection circuit of a PN pattern of + X + 1.

In the figure, 31 is a 2-1 selector, 32 is an 8-bit parallel PN pattern generation circuit, 33 is an error bit detection circuit, and 34 is a synchronization protection circuit. In this error detection circuit, the 2-1 selector 31 is initially set on the "B" side, and upon receiving an 8-bit parallel input signal, fetches the signal into an FF (flip-flop) of the PN pattern generation circuit 32. Generates a PN pattern synchronized with the outside.

Next, an error bit detection circuit 33 performs an exclusive OR (E-E) of the generated PN pattern and the input signal.
OR), the synchronization is secured by the synchronization protection circuit 34, and when the synchronization is secured, the 2-1 selector 31 is switched to the “A” side, and the PN pattern generation circuit 32 runs by itself. I have.

The synchronization protection circuit 3 in this error detection circuit
4 indicates that the flip-flop 34a is 3 from FF1 to FF3.
A four-stage shift configuration is provided. That is, in general, in a PN pattern error detection circuit, 30 synchronization protection stages are set, and an error is detected in units of 8-bit parallel signals, so that four 8-bit signals without errors are continuous. In this way, synchronization was considered to be established. After the synchronization is established, the flip-flop 34b
To output the switching signal to the 2-1 selector 31.

[0006]

However, in the conventional synchronous protection circuit 34 of this type, the number of synchronous protection stages is set by a four-stage shift configuration in which three flip-flops 34a are provided. Although the number of synchronization protection stages is 30, the number of synchronization protection stages is 8 bits × 4 stages = 32 bits. Therefore, when the number of synchronization protection stages is not an integral multiple of 8 bits but is specified in bit units, there is a problem that the number of synchronization protection stages cannot be secured accurately.

In order to solve this problem, the parallel input data is converted from P / S (parallel / serial) to serial data and is rearranged into serial data, and synchronization protection is provided as a serial data error detection circuit as shown in FIG. It is possible.

In FIG. 9, reference numeral 41 denotes a 2-1 selector, 4
2 is a PN pattern generation circuit, 43 is an error bit detection circuit, and 44 is a synchronization protection circuit. This synchronization protection circuit 44
Then, the flip-flop 44a is set to FF1 to FF29.
Since up to 29 are used, the number of synchronization protection stages can be exactly 30. However, when the error detection circuit is a serial circuit as described above, a high-speed clock is required when performing P / S conversion, which is difficult to realize.

For this reason, there has been a demand for a synchronous protection circuit capable of accurately counting the number of synchronous protection stages in parallel processing even when the number of synchronous protective stages is specified in bit units.

The present invention has been made in view of such circumstances, and it is possible to accurately count the number of synchronization protection stages in bit units without performing P / S conversion on parallel input data. It is intended to provide a serial synchronization protection circuit for parallel data.

[0011]

According to the present invention, there is provided an error bit detection circuit 11 for comparing parallel input data of a predetermined bit with data of a specific pattern in a predetermined bit unit to detect an error bit of the parallel input data. If all bits are valid as a result of bit detection, the number of valid bits is output, and if there is an error bit, the number of high-order valid bits that outputs the number of valid bits higher than the highest error bit is output. When an error bit is detected as a result of the error bit detection, a lower effective bit number output circuit 13 that outputs the number of effective bits existing lower than the lowest error bit, and a cumulative value of the effective bit number At the start of the synchronization protection judgment,
A valid bit number register 14 from which the stored contents of
An adding circuit 15 for adding the number of valid bits output from the upper significant bit number output circuit 12 to the total number of valid bits stored in the valid bit number register 14; In the valid bit number register 14, the number of valid bits added by the adder circuit 15 is accumulated, and when there is an error bit, the valid bit number register 14 erases the current storage content and simultaneously stores the lower valid bit. A selection circuit 16 for newly storing the number of effective bits output from the output circuit 13
And a comparison circuit 17 for comparing the number of effective bits added by the addition circuit 15 with a reference number of bits for synchronization protection.
As a result of comparison by the comparison circuit 17, when the total number of valid bits exceeds the reference bit number for synchronization protection,
It is determined that synchronization has been achieved with the parallel input data .
And the status signal is output
In both cases, when the synchronization protection judgment starts, the synchronization protection is not completed.
And a determination circuit 18 for outputting the state signal .

In the parallel data serial synchronization protection circuit, when an error bit of the parallel input data is detected by the error bit detection circuit 11, an effective pattern in a predetermined bit unit is set to any of a plurality of specified patterns. Pattern matching detection circuit 21 for detecting whether or not the pattern matches
However, as a result of the error bit detection, if all the bits are valid, the number of valid bits currently stored is stored in the valid bit number register 14 again. A selection circuit 2 for erasing the current storage contents and newly storing the number of valid bits output from the lower significant bit output circuit 13
The comparison circuit 17 determines the number of effective bits added by the addition circuit 15 as a
1 and a comparison circuit 23 which is set according to a plurality of prescribed patterns and is compared with the number of effective bits obtained by subtracting an integral multiple of a predetermined bit from the number of reference bits for synchronization protection. Good.

[0013]

According to the present invention, the error bit detection circuit 11
Then, the parallel input data of a predetermined bit is compared in a predetermined bit unit with data of a specific pattern such as a PN pattern.

As a result, when there is an error bit, the storage contents of the effective bit number register 14 are erased, and the effective bit number existing lower than the lowest error bit is newly stored in the effective bit number register 14. Then, the cumulative counting of the number of synchronization protection bits is started from this point.

When there are no error bits, that is, when valid bits continue, the adding circuit 15 adds the number of valid bits to the valid bit number register 14 to continue the cumulative counting of the number of valid bits. .
During this time, the number of effective bits added by the adder circuit 15 is always compared with the number of reference bits for synchronization protection. If the comparison result indicates that the number of bits exceeds the reference bit, it is determined that synchronization with the parallel input data has been achieved. .

In the meantime, if an error bit occurs, the number of effective bits existing higher than the highest error bit is finally added to the number of effective bits accumulated in the effective bit number register 14; This added number of effective bits is compared with the number of reference bits for synchronization protection. If the comparison result indicates that the number exceeds the reference bits, it is determined that synchronization with the parallel input data has been achieved.

At the same time, when an error bit occurs, the storage contents of the effective bit number register 14 are erased, and the effective bit number register 14 is renewed with the effective bit number existing lower than the lowest error bit. After storing the data, the cumulative counting of the number of synchronization protection bits is started again from this point.

Therefore, when there is an error bit,
Determines the number of significant bits that are lower than the least significant error bit, determines the number of significant bits that are higher than the most significant error bit, and synchronizes the accurate cumulative value of the number of significant bits in bit units. Since the comparison is made with the number of reference bits for protection, the number of protection stages can be accurately counted in bit units for parallel input data of a predetermined bit.

When a pattern match detection circuit is provided to separately count an error-free data string and an erroneous data string, the number of digits for addition is kept to a minimum and synchronization is performed. Protection can be speeded up.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. Note that the present invention is not limited to this. FIG. 1 is a circuit diagram showing an embodiment of an error detection circuit using a synchronization protection circuit according to the present invention, and shows an error detection circuit of a PN pattern of a generating polynomial X ¹⁵ + X + 1.

In this figure, 1 is a 2-1 selector, 2
Is an 8-bit parallel PN pattern generation circuit, 3 is an error bit detection circuit, and 4 is a synchronization protection circuit. In this error detection circuit, the input signal is a generator polynomial X ¹⁵ + X + 1
8 bit parallel signal having the following PN pattern.
The PN pattern generation circuit 2 is an 8-bit parallel PN pattern generation circuit of X ¹⁵ + X + 1, and has three protection stages.
This is the number of 0-bit protection stages.

The operation of this error detection circuit is as follows. 2-1 Selector 1 is initially set on the “B” side,
When an 8-bit parallel input signal is received, the signal is
The PN pattern is taken into an FF (flip-flop) of the N pattern generation circuit 2 and a PN pattern synchronized with the outside is generated.

Next, the error bit detection circuit 3 performs an exclusive OR (EO) of the generated PN pattern and the input signal.
R), synchronization is secured by the synchronization protection circuit 4, and when the synchronization is secured, the 2-1 selector 1 is switched to the "A" side, and the PN pattern generation circuit 2 runs by itself. in the meantime,
The detection of the error bit is performed by determining whether the PN pattern generation circuit 2 is synchronized with the external data or is free running.
Done regardless.

FIG. 2 is an explanatory diagram showing details of the synchronization protection circuit 4. In this figure, reference numeral 11 denotes details of the error bit detection circuit 3 shown in FIG. 1, which is an E-OR circuit. The E-OR circuit 11 compares 8-bit parallel input data with data from the PN pattern generation circuit 2 in 8-bit units. That is, in this comparison, an exclusive OR (exclusive OR: E-OR) is calculated to detect an error bit of the parallel input data.

Reference numeral 12 denotes a first priority encoder, which outputs the number of valid bits when all bits are valid as a result of error bit detection, and outputs the number of valid bits when an error bit exists, The number of existing valid bits is output with priority. Reference numeral 13 denotes a second priority encoder, and when an error bit is detected as a result of error bit detection, the second priority encoder 13 outputs the number of valid bits existing lower than the lowest error bit with priority.
Reference numeral 14 denotes a register for storing the cumulative value of the number of effective bits.

An adder circuit (ADD) 15 adds the number of effective bits output from the first priority encoder 12 to the total number of effective bits stored in the register 14.

Reference numeral 16 denotes a selector. When no error bit is detected as a result of error bit detection, that is, when all the bits are valid, the "absence" side is selected and the register 14
The number of effective bits added by the adding circuit 15 is accumulated. When an error bit exists, the “present” side is selected, and the register 14 is caused to erase the current storage content and to newly store the number of valid bits output from the second priority encoder 13.

Reference numeral 17 denotes a comparator (COMP) for comparing whether or not the number of synchronization protection stages has reached 30. The number of effective bits added by the adding circuit 15 is compared with the number of 30-bit synchronization protection stages.

Reference numeral 18 denotes an SR latch FF (flip-flop) for determining synchronization establishment. As a result of comparison by the comparator 17, when the total number of effective bits exceeds 30 bits, synchronization with the parallel input data is established. Then, a switching signal is sent to the 2-1 selector 1.

The operation of the synchronization protection circuit 4 is as follows. At the time of synchronization pull-in, first, the register 14 storing the current protection stage number is cleared, and the count of the protection stage number is set to “0”. Also, if the parallel input signal is
To take in the pattern generation circuit 2, the SR latch FF
18 and a synchronizing pull-in start signal is supplied to the SR latch FF.
18 to 2-1 by giving a select pulse to the selector 1
2-1 Let the selector 1 select the "B" side.

Next, the E-OR circuit 11 performs an exclusive OR operation on the PN pattern generated by the PN pattern generation circuit 2 and the input signal, and generates a first priority encoder 12.
And the second priority encoder 13 is used to encode the correct number of data from the MSB and LSB of the input signal until an error occurs, that is, the number of valid bits.

When there is an error bit, the first priority encoder 12 preferentially outputs the minimum number of effective bits counted from the MSB side of the input signal, and the second priority encoder 13 outputs the input signal when there is an error bit. The minimum number of effective bits counted from the LSB side of the signal is preferentially output.

If the E-OR circuit 11 compares the data and finds no error bit, the selector 16 selects the data on the “absent” side, and the number of valid bits stored in the register 14 is reduced. The number of valid bits output from the first priority encoder 12 is added, and the result is written back to the register 14 to accumulate the number of valid bits.

If the E-OR circuit 11 compares the data and finds that there is an error bit, the selector 16 selects the data on the “present” side. The number is erased and the second
The number of valid bits output from the priority encoder 13 is newly written in the register 14.

The result added by the adding circuit 15 is always compared by the comparator 17, and when the set number of protection bits is cleared, the SR latch FF 18 is reset and the 2-1 selector 1 is switched. , The input signal to the PN pattern generation circuit 2 is stopped, and synchronization is ensured. After the synchronous measurement is started, the above processing is repeated, whereby the number of protection stages can be accurately counted in bit units.

FIG. 3 is an explanatory diagram showing the operation result of the synchronization protection circuit according to the present invention. The process until the synchronization is actually secured is shown by the result of the conventional synchronization protection circuit and the result by the synchronization protection circuit of the present invention. It is what was compared with.

The upper half of the figure shows the time “1” to the time “1”.
The result of error bit detection in units of 8 bits at 3 ″ is shown. Bit data having no error is indicated by a number, and bit data having an error is indicated by hatching.

As a result of this error detection, if an error is detected in a pattern as shown in FIG.
Since the protection of the stage (8 bits × 4 stages = 32 bits) is taken,
When the count of the number of protection steps is “2”, the specified number of protection steps cannot be cleared. However, in this case, since there is actually 30 bits of error-free data, synchronization must be originally secured.
In the case of the pattern shown by, the data arrangement of the worst case error bits considered in the conventional four-stage protection is considered.
The result is that synchronization is not achieved despite the continued bits.

When the synchronization protection circuit 4 according to the present invention is used for these patterns, the first error is in the MSB in the 8 bits of the time "1", and the remaining 7 bits are used. Since the last error is in the LSB of the 8 bits at time “4”, the remaining 7 bits until the error is present, and the 16 bits at time “2” and time “3” without error are valid. The number of protection stages is cleared with a total of 30 bits, and synchronization is ensured.

In the pattern of the above, since the first error is in the MSB in the 8 bits of the time “7”, the remaining 7 bits and the time “ 24 at 8 ”, time“ 9 ”, and time“ 10 ”
Since there is data having no bit error, the number of protection stages is cleared by a total of 31 bits including the 24 bits, and synchronization is ensured.

In the case of the pattern (2), there are two error bits at the same time. At this time, the first priority encoder 12 sends the first error data more MS than the first error data.
"1" which is the correct number of data existing on the B side is output, and "2" which is the correct number of data existing on the LSB side than the second error data is output from the second priority encoder 13. . In this case, the 3-bit data between the erroneous 2 bits is processed as invalid.

As described above, by using the priority encoder (encoder with priority) for synchronization protection in error detection, N / N (N is an arbitrary natural number) parallel input data can be converted without P / S conversion. ,
The number of protection stages can be accurately counted in bit units.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. In the synchronization protection circuit of this embodiment, when the number of synchronization protection stages is increased to N (N is an arbitrary natural number) in the synchronization protection circuit of the previous embodiment, the number of digits of the adder circuit 15 increases and the delay increases. Is a circuit devised to solve the problem, and is a circuit that can cope with the number of synchronization protection stages of N stages.

That is, in the synchronization protection circuit 4 of the previous embodiment, the addition circuit 15 adds the register 14 and the first priority encoder 12 and writes the addition result into the register 14 again. When the number is increased to any N stages, the number of digits of the adder circuit 15 increases, and the delay increases. Therefore, in this embodiment, in order to minimize the delay applied to the adder circuit 15, the data string having no error is considered as one stage, and the data string having an error is considered as one stage. , First priority encoder 12 and second priority encoder 13
, The number of digits of the adder circuit 15 is minimized and the speed is increased.

The following is an example in which the above-described embodiment is compared with the present embodiment (however, the input data is an 8-bit parallel signal).

[0046]

[Table 1] As described above, in the protection circuit according to the present embodiment, the number of digits of the adder circuit 15 can be set to four digits.
And the delay caused by the delay can be minimized.

Hereinafter, this embodiment will be described. The same components as those in the previous embodiment are denoted by the same reference numerals, and description thereof will be omitted. Further, the input signal is an 8-bit parallel signal as in the previous embodiment, and the number of protection stages will be described as the 30-bit protection stage as in the previous embodiment.

In FIG. 4, reference numeral 20 denotes an AND circuit, and reference numeral 21 denotes a pattern matching detection circuit. Pattern match detection circuit 2
When an error bit of parallel input data is detected by the E-OR circuit 11, 1 detects which of a plurality of prescribed patterns matches a valid pattern in 8-bit units.

The selector 22 detects the result of the error bit,
When there are no error bits, that is, when all the bits are valid, the “absence” side is selected, and the register 14 stores the number of valid bits currently stored as it is again.
When there is an error bit, the “present” side is selected, and the register 14 is made to erase the current storage contents and newly store the number of valid bits output from the second priority encoder 13.

The comparison circuit 23 compares the number of effective bits added by the addition circuit 15 with the number of effective bits set according to a plurality of prescribed patterns of the pattern match detection circuit 21. That is, the number of effective bits obtained by subtracting an integral multiple of 8 bits from the number of bits of N (N is an arbitrary natural number) for synchronization protection is compared with the number of bits of 14 and 6 stages.

The adder circuit 15 in this embodiment may be a 4-digit adder circuit as described above. That is, as shown in FIG. 3, when the input data is an 8-bit parallel signal, a maximum of 7 bits + 8 bits = 15 bits of error-free data is continuously applied to two erroneous data strings. Can be considered. This 7 bits + 8
In order to perform a binary operation of 15 bits, a 4-digit addition circuit is sufficient, so that the addition circuit 15 is a 4-digit addition circuit.

FIG. 5 is a detailed explanatory diagram of the pattern match detection circuit 21. As shown in this figure, the pattern match detection circuit 21 has four flip-flops 21a and three ANs.
D (A), (B), (C) It is composed of a circuit 21b.

The flip-flop 21a is a four-stage flip-flop because the pattern shown in FIG. 3 (5 consecutive 8-bit parallel data) is considered to be the maximum in order to protect 30 consecutive bits. ing.

In the AND (A), (B), (C) circuit 21b, an 8-bit data string having an error is indicated by "x", and an 8-bit data string having no error is indicated by "O". , AND (A) circuit 21b detects that the error is ×××× (T1,
(T2, T3, T4). This pulse output is used as a valid / invalid pulse of the comparison result of the comparison circuit 23.

The AND (B) circuit 21b detects that the error is
This is to confirm that the pattern is × (T1, T2, T3, T4, T5), and this pulse output is used as a valid / invalid pulse of the comparison result of the comparison circuit 23.

The AND (C) circuit 21b detects that the error is
This is to confirm that the pattern is (T1, T2, T3, T4), and this pulse output is used as a valid / invalid pulse of the comparison result of the comparison circuit 23.

FIG. 6 is a detailed explanatory diagram of the comparison circuit 23.
As shown in the figure, the comparison circuit 23 includes a first comparator 23a for confirming the number of protection stages of 14 stages, a second comparator 23b for confirming the number of protection stages of 6 stages, and the number of protection stages of 6 stages. And three comparators for determining the AND of the pattern detected by the pattern match detection circuit 21.
Three AND (A), (B) and (C) circuits 23d and three AND
(A), (B), (C) An OR circuit 23e that takes an OR when any one of the circuits 23d matches.

The first comparator 23a is a circuit for detecting the minimum number of bits that can clear 30 bits of the protection stage when the pattern of xxxx is detected by the pattern matching detection circuit 21. The portion of ○ detected by the pattern match detection circuit 21 indicates that an error-free data string has been repeated twice = 16 bits, and the first comparator 23a has data before and after the error indicated by × before and after. Only valid data (error-free data) needs to be compared for the columns.
Therefore, when there are valid data of 30 bits−16 bits = 14 bits or more, the number of protection stages can be cleared.

The valid data shown here is the second priority encoder 13 (the number of error-free data counted from the LSB of 8-bit parallel data until the first error) for a data string having an error first. Is the value of the register 14 and the value of the first priority encoder 12 (the number of error-free data from the MSB of the 8-bit parallel data until the first error) for the data string having the next error It is.

The second comparator 23b outputs a signal at the time of the pattern of ××××× detected by the pattern match detection circuit 21.
This is a circuit for detecting the minimum number of bits that can clear the protection stage number of 30 bits. In the portion of ○ detected by the pattern matching detection circuit 21, the error-free data string is 3 times = 24
This indicates that the bit has continued, and the second comparator 23b
Then, it is sufficient to compare only valid data (error-free data) with a data string having an error indicated by x before and after the error. Therefore, when there are valid data of 30 bits-24 bits = 6 bits or more, the number of protection stages can be cleared.

The valid data shown here is the value of the second priority encoder 13 = the value of the register 14 for a data string having an error first, and the first priority for a data string having an error next. This is the value of the encoder 12.

The third comparator 23c is a circuit for detecting the minimum number of bits capable of clearing 30 bits of the protection stage in the case of the pattern of xxxx detected by the pattern matching detection circuit 21. The portion of ○ detected by the pattern match detection circuit 21 indicates that an error-free data string has been repeated 3 times = 24 bits. In the third comparator 23c, the error indicated by × before the error is indicated. It is sufficient to compare only valid data (error-free data) with a certain data string. Therefore, when there are valid data of 30 bits-24 bits = 6 bits or more, the number of protection stages can be cleared. The valid data shown here is the value of the second priority encoder 13 = the value of the register 14 for a data string having an error first.

The AND (A) circuit 23d controls the validity / invalidity of the result compared by the first comparator 23a. The AND (A) circuit 2d of the pattern match detection circuit 21
It is valid only when the pulse detected at 1b is "H (high)".

The AND (B) circuit 23d controls the validity / invalidity of the result compared by the second comparator 23b, and the AND (B) circuit 2d of the pattern match detection circuit 21
It is valid only when the pulse detected at 1b is "H".

The AND (C) circuit 23d controls the validity / invalidity of the result compared by the third comparator 23c. The AND (C) circuit 23d of the pattern match detection circuit 21
It is valid only when the pulse detected at 1b is "H".
The AND (C) circuit 21b and the third comparator 23
c, AND (C) circuit 23d outputs the first 8 bits having an error.
The number of effective bits on the LSB side in parallel data is 6 bits.
And the AND (B) circuit
21b, second comparator 23b, AND (B) circuit 23
The determination of synchronization establishment is one clock earlier than the detection by d.
I can do it. The OR circuit 23e is a gate that detects whether 30 bits of the synchronization protection stage have been cleared.

FIG. 7 is an explanatory diagram showing the operation result of the synchronization protection circuit according to another embodiment. The upper half of the figure shows the results of error bit detection in units of 8 bits from time “1” to time “11”. Bit data without errors are numbered, and bit data with errors are numbered. Is shown with diagonal lines.

As a result of this error detection, if an error is detected in a pattern as shown by the following, since an error has occurred in the MSB in the data string at time "1", the selector 22
Selects the “present” side data, invalidates the currently stored protection stage number, and newly writes the value of the second priority encoder 13 to the register 14.

Since no error is detected in the data strings at time “2” and time “3”, the pattern match detection circuit 21 counts the two data strings. During this time, since the selector 22 has selected the data on the “absent” side, the currently stored protection stage number is written again to the register 14 as it is.

Next, since an error has occurred in the LSB in the data string at time "4", the result of the register 14 and the result of the first priority encoder 12 are added, and the comparison circuit 23 makes a comparison. Is clear, synchronization can be ensured. However, in this case, the result compared by the comparison circuit 23 is valid only when the condition that the pattern match is detected by the pattern matching detection circuit 21 is satisfied, and is invalid when the condition is not satisfied. Becomes

As described above, the pattern indicated by the symbol “A” shown in the column “(2) Pattern match detection” in FIG.
(Xxxx), and with the same operation, the pattern of "B" (xxxx) shown in the same column is obtained by the same operation to ensure synchronization.

In this manner, the value of the first priority encoder 12 and the value of the register 14 are added to erroneous data to an arbitrary number of N stages of synchronization protection stages. At 21, the pattern is matched in units of 8 bits, that is, by separately counting the error-free data string and the erroneous data string, the number of digits for addition is minimized, and synchronization protection is performed. Higher speed can be achieved.

[0072]

According to the present invention, when an error bit exists, the number of effective bits existing lower than the lowest error bit is obtained, and the number of effective bits existing higher than the highest error bit is obtained. Is obtained, and the cumulative value of the number of effective bits is compared with the reference bit number for synchronization protection. Therefore, the number of protection stages can be accurately counted in bit units for parallel input data of a predetermined bit. If a pattern match detection circuit is provided to count error-free data strings and erroneous data strings separately, the number of digits for addition is minimized, and high-speed synchronization protection is achieved. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an error detection circuit using a synchronization protection circuit according to the present invention.

FIG. 2 is a detailed explanatory diagram of a synchronization protection circuit.

FIG. 3 is an explanatory diagram showing an operation result of the synchronization protection circuit according to the present invention.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is a detailed explanatory diagram of a pattern match detection circuit.

FIG. 6 is a detailed explanatory diagram of a comparison circuit.

FIG. 7 is an explanatory diagram showing an operation result of a synchronization protection circuit according to another embodiment of the present invention.

FIG. 8 is an explanatory diagram showing an error detection circuit using a conventional synchronization protection circuit.

FIG. 9 is an explanatory diagram showing a conventional serial data error detection circuit.

[Description of Signs] 1 2-1 selector 2 PN pattern generation circuit 3 error bit detection circuit 4 synchronization protection circuit 11 E-OR circuit 12 first priority encoder 13 second priority encoder 14 register 15 addition circuit (ADD) 16, 22 Selector 17 Comparator (COMP) 18 SR latch FF (flip-flop) 20, 21b, 23d AND circuit 21 Pattern match detection circuit 21a FF (flip-flop) 23 Comparison circuit 23a First comparator 23b Second comparator 23c Third comparator 23e OR circuit

Continuation of the front page (56) References JP-A-2-244837 (JP, A) JP-A-7-38551 (JP, A) JP-A-7-66800 (JP, A) (58) Fields studied (Int .Cl. ⁷ , DB name) H04L 7/08 H04L 1/00 H04L 7/00

Claims (2)

(57) [Claims] An error bit detection circuit (11) for comparing parallel input data of a predetermined bit with data of a specific pattern in a predetermined bit unit and detecting an error bit of the parallel input data; When the bit is valid, the valid bit number output circuit (1) outputs the number of valid bits, and when there is an error bit, outputs the number of valid bits existing higher than the highest error bit.
2) and when an error bit is detected as a result of the error bit detection, a lower effective bit number output circuit (13) for outputting the number of effective bits existing lower than the lowest error bit.
When stores the cumulative value of the number of effective bits, the synchronization protection-format
At the start of the constant, the stored contents are erased from the effective bit number register (14) and the accumulated effective bit number stored in the effective bit number register (14) to the upper effective bit number output circuit (12). Circuit for adding the number of effective bits (15)
If all bits are valid as a result of error bit detection,
The effective bit number added by the adder circuit (15) is accumulated in the effective bit number register (14), and when there is an error bit, the effective bit number register (14)
A selection circuit (16) for erasing the current storage contents and newly storing the number of valid bits output from the lower significant bit output circuit (13); and a number of valid bits added by the adder circuit (15). Is compared with a reference bit number for synchronization protection (1
7) and as a result of comparison by the comparison circuit (17), when the total number of valid bits exceeds the reference bit number for synchronization protection,
It is determined that synchronization has been achieved with the parallel input data .
And the status signal is output
In both cases, when the synchronization protection judgment starts, the synchronization protection is not completed.
, And outputs the state signal.
8) A parallel data serial synchronization protection circuit comprising: 2. When an error bit of a parallel input data is detected by an error bit detection circuit (11), it is determined which effective pattern in a predetermined bit unit matches a specified pattern among a plurality of specified patterns. A pattern matching detection circuit (21) for detecting, when the selection circuit (16) detects that all bits are valid as a result of error bit detection, a valid bit number register (14)
Again stores the currently stored number of effective bits,
When an error bit exists, a selection circuit (22) for erasing the current storage content in a valid bit number register (14) and newly storing the valid bit number output from the lower significant bit output circuit (13). The comparison circuit (17) sets the number of effective bits added by the addition circuit (15) according to a plurality of prescribed patterns of the pattern match detection circuit (21), respectively, and sets a reference bit for synchronization protection. 2. The parallel data serial synchronization protection circuit according to claim 1, further comprising a comparison circuit for comparing the number of bits obtained by subtracting an integral multiple of a predetermined bit from the number.