JPS6128276A - Decoding circuit - Google Patents

Abstract

PURPOSE:To obtain a decoding circuit realized high speed procession performing sequentially data arrangement so that a head bit of a code string to be discriminated is a prescribed location in a facsimile equipment. CONSTITUTION:Suppose that a 16-bit code string to be fetched from a code buffer is a sequence shown in figures 1, 2. First a control circuit 17 outputs signals k, d to allow registers 11, 12 to fetch an MH code string 16-bit and a signal l is outputted at the same time to make the content of a mask circuit 18 all ''1''. On the other hand, a control circuit 25 outputs a selection signal (m) to set the content of the register 11 to a shift circuit 15 at a multiplexer 14. Since the bit is shifted toward the low-order by 8-bit's share by the input of a count value (i), the 8-bit of [00110100] converted into a run length number is shifted to the low- order as an effective code.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a compressed code decoding circuit used in facsimile machines and the like. [Prior art] In the facsimile machine on the sending side, the black and white binary data string obtained by the photoelectric conversion element is converted into Mll (Modified
The facsimile machine on the receiving side decodes the Mll code into a binary data string corresponding to the number of run lengths of the original image information and transmits it optically. It should not be recorded as information. (Margin below) Table 1 M11 codes are as shown in Table 1, and the run length number, that is, the number of consecutive pixels of the same color, is 63 or less as a terminator code, and the number of consecutive pixels of the same color is 63 or less, and the term is 64 or more. A code incremented by 64 is called a make-up code.If the run length is 63 or less, it is expressed by only the terminator code, and if it is 64 or more, the make-up code and the terminus I code are expressed by a combination. It will be done. It is always terminated by a terminating sign. Now, the present invention relates to a circuit for decoding an MH code into a run-length number, and a decoding circuit as shown in FIG. 7 has heretofore been known (Japanese Patent Laid-Open No. 57-65064). The old code string received from the next line is taken into the shift register 73 using the clock output from the control circuit 71 as a shift pulse. This clock is also input to the counter 72.
L is given. 74 is a decoding ROM in which the output of the counter 72, the output of the shift register 73, and the black/white discriminating code issued by the control circuit 71 are input as addresses, and thereby the number of run lengths of white and black corresponding to the input Ml+code string is inputted as an address. Figure 8 shows the microprocessor 81
This is an example in which the control circuit 82 and register 83 are configured using
4, and then taken into the register 83 as appropriate, and the stored data is determined to be "1" or "0" bit by bit starting from the higher order bit in this register 83, and it is determined that the code matches the Ml+ code. Then, the control circuit 82 generates the run length number and outputs it to an external circuit. [Problems to be solved by the invention] In the decoding circuit shown in FIG. 7 described above, one via ), and each time one bit is processed, it is necessary to determine whether or not it is Ml+sign using the decoding ROM output B, so there is a problem that it is not suitable for speeding up. Also, although the decoding circuit shown in Figure 8 has the advantage of requiring less hardware, it requires many program steps for decoding, and is not suitable for high-speed encoding. Means] The present invention solves the above-mentioned problems.It is an object of the present invention to provide a decoding method that achieves high speed by sequentially aligning data so that the first bit of the code string to be determined is at a predetermined position. A decoding circuit according to the present invention is a circuit for decoding a compressed code representing a run length of binary data into a binary signal corresponding to the original number of run lengths. A memory of a predetermined number of bits for temporarily storing a code, a j-th register for latching the parallel output of the memory, a second register, a shift circuit for selectively inputting the contents of these registers, and a second register for storing the contents of the shift circuit. a mask circuit for merging the contents of the first register or shift circuit with the contents of the third register; and a decoder for inputting the merged data and converting it into a run-length number. It is equipped with a ROM, a circuit that detects the number of bits of the compressed code that has been effectively converted in the decoding ROM, and an adder circuit that adds the outputs of the circuit.Based on the contents of the adder circuit, the data in the shift circuit is It determines the number of shifts, determines the contents of the mask circuit, and also controls data transfer between each register and shift circuit to align the code string to be converted to the top of the data input to the decoding ROM. [Embodiments] The present invention will be specifically explained below based on the drawings showing the embodiments. Fig. 1 is a block diagram showing the configuration of the apparatus of the present invention. The Ml+ code string obtained is serially taken into a code buffer memory (hereinafter referred to as code buffer) 10, and sent from there in parallel to a thirteenth second register 11.12. In this embodiment, the parallel output of the code buffer 10 is 16 bis 1-, and its acquisition is controlled by an output signal n of a control circuit 25, which will be described later. Register II, 1
The contents of 2 are sent to the shift l-circuit 1 via the multiplexer 14 which selects the input with the selection signal m output by the control circuit 25.
5 is selectively given. Shift circuit 15 Addition circuit 2
The data is shifted to the upper side in response to the 81 value j of 3, and the data shifted to the upper side is returned to the lower side. Multiplexer 16 is connected to register 11
Alternatively, the contents of the shift circuit 15 are selectively applied to the AND key I.17 according to the selection signal f output by the control circuit 25. 18 is a mask circuit which includes registers 11. The - part of the contents of the third register 13 or shift circuit 15 is masked and the encoding ROM 24. The first value j of the adder circuit 23 is inputted to the register 13.
The lower side hit corresponding to this is set to "1", and the remaining - value opening histo 1- is set to "0".The contents are directly sent to the ANrl gate 17, and the inverter 19 is sent to the AND gate 1-20. Another input of the AND gate 20 is the content of the third register 13. The output of the ANrl gates 1 to 17.20 is decoded via the OP gate 21 or the register 13. The decoding ROM 24 is for directly converting the Ml+ code into a run length number, and has contents 1a as shown in Table 1.The processed number detection circuit 22 is OR
A number 1η representing how many hits are used to detect the Ml+ symbol is obtained from the back of the code output of the gate 1-21, and this value is sent to the adder circuit 23. Addition circuit 23
The number of cigarettes is added, but when it is counted up to 16, it is configured so that the number 61 starts again from O. The control circuit 25 controls the operation of each of the circuits mentioned above, and the adder circuit 23 outputs a signal g when the count value becomes 16 or more.
is given to the control circuit 25. Conversely, the control circuit 25 provides a reset signal to the adder circuit 23. Also register] L12
, 13 is based on the signal issued by the control circuit 25.
This is done by d and e. A signal 1 is applied to the mask circuit 18 to set it to an initial cent state of all "1"s. Others (J
l is a color judgment signal and is given to the decoding ROM 24. Next, the operation of the circuit of the present invention having the above structure will be explained. Assume that the 16-bit code string to be fetched from the code buffer is in the order shown in FIG. 2 [11, +21]. That is, the 16-bit data to be taken in first is the old code of white 63, black 10, and "0" (lowest order) from the most significant side (the one inputted to the code buffer IO first). The next 16 bits are the old code of white 10 from the most binary side, with the leading "0" (after the M I+ 24 combination of 10) missing, and the Ml+ code of focus 7. There is. The contents of the lower 7 bits are not relevant to the following explanation, so they are omitted and indicated by an X. First, the control circuit 17 outputs d as a signal to the register 11.
．． 12 is loaded with Ml+code sequence 16 bits. At the same time, the signal p is output and the contents of the mask circuit for one day are all 1.
In addition, a signal is output to reset the adder circuit 23.Furthermore, a predetermined selection signal f is given to the multiplexer 16 to select the input from the register 11, and this is given to the AND gate 17. Since the contents of the mask circuit 18 are all "1's," the input to the ND gate 17 is directly input to the OR gate 21. On the other hand, the output of the mask circuit 18 is transferred to the inverter 19.
Since it is input to the AND gate 1-20 via the OP gate 21, all outputs thereof become "0", and the output of the OR gate 21 becomes the exact contents of FIG. The output is given as an address signal to the decoding ROM 24, and the color judgment signal J (initially "0" representing white) is given from the control circuit 25, so the upper [00 month old 00] data Outputs the run length number 663" from the column. Processed number output 1?822
receives the same content as decoding 110M24, but instead of outputting the run length number, it outputs the number of bits (8 in this case) of the data string that was effectively used for conversion.
is detected from information stored in advance, and outputted to the adder circuit 23 as a binary signal. Then, the count value i of the adder circuit 23 becomes "8" and is outputted. On the other hand, the control circuit 25 outputs a selection signal m to shift the contents of the register 11 to the multiplexer 14.
-Save it. Then, by inputting the count value 1, in this case, it is shifted to the lower side by 8 pips, so as shown in Figure 3, the 8 bits of (00110100) converted to the run length number as the effective sign are shifted to the lower side. Be in a moving state. At this time, the contents on the binary side are the lower 8 bits in FIG. 2(1). Next, the control circuit 25 causes the multiplexer 16 to select the input from the shift circuit 15 using the selection signal f,
It also issues a signal e to change the contents of the shift circuit 15 to the AND game 117. It is stored in the register 13 via the OR gate 21. On the other hand, the old value 1 is also given to the mask circuit 18. Since the content of i is 8, its content is as shown in Figure 4 (1), the lowest 8 hits are 1", -, Ir, and the bottom 8 hits are "
0'' state.Next, ifi!I control FIJ!25 outputs lH number k, causes register 1 to take in the next data [Figure 2 (2)], and stores this content. Shift circuit 1
5 will be activated. Then, the d1 value of the adder circuit 23 is 1.
is "8", so the output of the shift circuit 15 is as shown in Fig. 4 (2
), the contents of Figure 2 (2) are shifted to the right by 8 bits I.
・It becomes a state. Then, the control circuit 25 selects the contents of the shift circuit 15 using the selection signal f. Then, since the contents of the mask circuit 18 are as shown in FIG. 4(1), the output of the AND gate 17 is as shown in FIG. 4(3).The upper 8 pins I- are "'o", The lower 8 bits I. have the same contents as the shift circuit 15. On the other hand, since the mask circuit V818 output is inverted and given to the static log gate 20, A11l
The output of the ll gate 20 is the lower 8 as shown in Figure 4 (4).
The bit is "0" and the upper 8 bits are the contents of the first 8 bits of the register 13. Therefore, the output of OR game 1-21 is the sum of both ANII games 1-17.20, and as a result, the Ml+ sign of black 10 to be converted next is on the upper side,
Next is a data string with white 10s. Is this decryption 1? Since the color determination signal j of "black" is supplied to the OM 24 and the "black" color determination signal j is supplied from the control circuit 25, the decoding ROM 24 outputs the run length number "10". Since the Ml+ sign of 10 in the river is 7 bits, it is detected by the processed number detection circuit 22 and counted by the addition circuit 23 (Direct i is B + 7 = 15. The control circuit 25 also performs addition by two conversions. Since the signal g cannot be obtained from the circuit 23, the selection signal m is used to input the data stored in the register 12 [FIG. 2 (1)] to the shift circuit 15 via the multiplexer 14.
-" A 15° bit shift is performed. This results in the contents as shown in FIG. figure

[As shown in υ, the lower 15 bits are 1'' and the most significant bit is 0. The control circuit then changes the contents of the register 11 (
(2)] in FIG. 2 is selected by the multiplexer 4 and inputted into the shift circuit 15 to perform a 15-bit shift. Then, the contents of the shift circuit 15 become as shown in FIG. 6(2). Since the contents of the mask circuit for the first day are only 0 in the lowest bit, the contents of the register 13 in FIG. (others are O), whereas multiplexer 1
Shift circuit I input to AND gate 17 via 6
The contents of 5 are OR game 1-21 for the bottom 15 people.
As a result, the output of the OR gate 21 is given to the first unprocessed M11 code white 1 as shown in FIG. 6 (5).
0 is located at the tip. The dirt is given to the decoding ROM 24, and the color determination signal j (in this case, white) is given, so that the decoding ROM 24 &i outputs the run length number 10. The processed number construction circuit 22 determines that the processed number is 5 and supplies it to the addition circuit 23, so that the added value becomes 20. Therefore, the adder circuit 23 issues a signal g to the control circuit 25, and the count value l becomes 2O-16=4. In response to input of signal g, control circuit 25 outputs signal d to 1 and takes in the code string shown in FIG. 2(2) from code buffer 10. At the same time, the next 16 bits of data (not shown) are loaded into the register 11. Then, the contents of the register 12 are input to the shift circuit 15, and the old value i of the adder circuit 23 is
Perform a 4-pitch 1- shift. Then, as is clear from FIG. 2 (2), the contents of the shift circuit 15 are black 7 (000
11) is shifted to the beginning. This is stored in the register 13 in the same manner as before. At this time, the lower 4 bits of the mask circuit are "1" and the upper 12 bits are "1".
Since the bit is "0", the 12 binary hits output from the OR gate 21 become the contents of the register I3, and the first field 7 is converted into a run-length number and output by the decoding ROM. By repeating the above operations, the decoding ROM 24
The OR gate 21 output given to is always the gate 1 to be decoded.
The head of the 1 code is located at the top. They will be arranged in L. [Effect] As described above, the Ml that should be decoded in the decoding ROM 24
The + sign is input with its head positioned at the most significant bit 1-, and high-speed decoding becomes possible. Furthermore, since such data alignment can be performed at high speed, a decoding circuit faster than that of the conventional art can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the circuit of the present invention, FIGS. 2 to 0 are code string diagrams for explaining its operation, and FIGS. 7 and 8 are conventional decoding circuit diagrams. ]O... Sign buffer 11, 12.13... Register 14.16... Multiplexer 15... Shift circuit 17.20... ANII game 1-18...
Mask circuit 19...Inverter 21/OR gate 2
2...Processed #! I detection circuit 23...addition circuit 2
4...Decoding circuit 25...Control circuit patent Applicant Sanyo Electric Co., Ltd. Agent Patent attorney Tomio Kono Procedural amendment (voluntary) September 20, 1980

Claims (1)

[Claims] In a circuit that decodes a compressed code representing a run length of 1- or 2-value data into a binary signal corresponding to the original number of run lengths, a memory having a predetermined number of bits that temporarily stores the compressed code; and a first latching the parallel output of the memory;
a second register, a shift circuit that selectively inputs the contents of these registers, a third register that stores the contents of the shift circuit, and a third register that inputs the contents of the first register or shift circuit and the third register. a mask circuit for merging the contents, a decoding ROM for inputting the merged data and converting it into a run length number, and a circuit for detecting the number of bits of the compressed code effectively converted by the decoding ROM. and an adder circuit that adds the outputs of the circuit, determines the number of shifts of data in the shift circuit based on the contents of the adder circuit, determines the contents of the mask circuit, and further determines the number of data shifts between each register and the shift circuit. A decoding circuit characterized in that it controls data transfer and aligns a code string to be converted to the highest order of data input to a decoding ROM.