JP3229698B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter, referred to as a TFT), and more particularly, to a thin film transistor having a structure in which even if the formation of a gate electrode is misaligned, problems associated therewith are unlikely to occur. About the method.

[0002]

2. Description of the Related Art FIGS. 6 and 7 are sectional views showing a conventional TFT structure. FIG. 6 shows a TFT having a coplanar structure.
Indicates a staggered TFT. In each figure, 100 is an insulating substrate, 101 is a drain contact doped layer, 102 is a source contact doped layer, 103
Is an active layer, 104 is a gate insulating film, 105 is a gate electrode, 106 is a drain electrode, and 107 is a source electrode. The contact doped layers 101 and 102 and the active layer 103 in such a TFT are formed of, for example, amorphous silicon (hereinafter, referred to as a-Si) or polycrystalline silicon (hereinafter, referred to as p-Si). Is done.

Meanwhile, it is known that the above-mentioned a-Si has a low electron mobility.
Development of a TFT made of p-Si capable of realizing electron transfer of about 10 to 1000 times that of -Si is underway.

[0004] However, this p-Si TFT has a disadvantage that the leakage current is large. For this reason,
Attempts have been made to reduce the leakage current by providing a structure for weakening the gate electric field strength at the drain end to the TFT.

FIG. 8 shows a leak current reducing structure in the above-mentioned coplanar TFT. By providing an n ⁻ layer 101a at the drain end, the LDD (L
In this case, the gate electric field strength at the drain end is weakened.

On the other hand, FIG. 9A shows a leakage current reducing structure in the above-mentioned staggered TFT, which is on the right side (hereinafter referred to as a minus side) with reference to the position of the broken line in the figure. ), The gate electrode is located at
That is, by providing a constant interval (offset) between the drain end and the gate end, the electric field intensity at the drain end is reduced.

[0007]

However, the above-mentioned n ^- layer 101a can be formed in a self-aligned manner with respect to the gate electrode 105 by ion implantation or ion doping. Dope control is not easy. In addition, although annealing is required, there is a defect in which heat at that time adversely affects other constituent materials.

On the other hand, in the offset gate structure, as shown in FIG. 9B, a shift may occur in the formation position of the gate electrode 105 due to a patterning misalignment in forming the gate electrode 105. is there. FIG. 10 is a graph showing the relationship between the gate voltage and the drain current in the TFT. Graph a in FIG. 9A shows an appropriate offset of ΔL (0.5 μm) on the minus side from the broken line position. Graph showing the characteristics at the time.
Is ΔL on the plus side from the broken line position in FIG.
(0.5 μm) shows the characteristic when it is shifted. In addition,
The voltage (V _DS ) between the drain and the source is set to 5 V, and the gate width / gate length (W / L) is set to 10 μm / 10 μm.

When an appropriate offset structure is obtained as shown in FIG. 9A, the off-state current can be reduced as shown in graph a, but as shown in FIG. Occurs, the off-current reduction effect cannot be obtained as shown in the graph b. Although not shown in the figure, if the offset is too large in FIG. 9A, the effect of reducing the off-current is saturated, but
The decrease in the on-current becomes remarkable.

As a solution to the above problem, a TFT having a structure in which the gate insulating film is thicker between the gate electrode and the drain region than in the channel region has been devised. (JP-A-3-108
374 (International Patent Classification H01L29 / 78). That is, weaken the gate electric field strength in the drain region by the gate insulating film and thick film on the drain region, is obtained thereby reducing the off current.

However, in the above-mentioned conventional TFT, it is difficult to set a process condition for accurately and uniformly forming a thick portion of the gate insulating film on the drain region. There is a disadvantage that the current increases.

In view of the above circumstances, the present invention is based on reducing the electric field strength at the gate end by using an offset structure, and even if a shift occurs in the gate electrode formation position due to the formation of this offset structure. The effect of reducing the off current is secured by the thick gate insulating film on the drain region, and further, the thick portion of the gate insulating film can be accurately formed on the drain region. It is an object of the present invention to provide a thin film transistor having a structure that hardly affects the on-current regardless of the position of the gate electrode end in any position within the offset section, and a method of manufacturing the same.

[0013]

The thin film transistor of the present invention SUMMARY OF THE INVENTION To solve the above problems, is formed on an insulating substrate, a convex insulating portion bottom has a large trapezoidal than the upper side, the convex The convex insulation on one side of the convex insulation
And the drain contact layer which is formed at a lower height than the upper surface position of parts, the convex absolute at the other side of the convex shaped insulating portion
A source contact layer formed at a height lower than the upper surface position of the edge, and an active layer formed over the convex insulating portion and having one end connected to the drain contact layer and the other end connected to the source contact layer When, a gate insulating film formed flat covering said active layer and before Kido Ray <br/> down contact layer and the source contact layer, and the convex insulating portion a on the gate insulating layer And a gate electrode formed at a corresponding position.

Further, according to the method of manufacturing a thin film transistor of the present invention, a lower insulating film is formed on an insulating substrate, and the lower insulating film has a convex shape having a trapezoidal cross section whose base is larger than the upper side.
Forming an insulating part, forming a contact layer on the lower insulating film including the convex insulating portion, a step of flat forming resist film on the contour <br/> transfected layer, wherein co <br/> Ntakuto layer and the resist film, the convex shaped insulating portion is exposed, and etching to further position of the upper surface of the contact layer is lower than the upper surface position of the convex insulating portion, wherein forming an active layer on the end portion of the contact layer located on the side of the exposed convex insulating portion and the convex insulating portion, formed flat gate insulating layer on the active layer and the contact layer a step is characterized in that it comprises a step of forming a gate electrode in a position corresponding to the convex insulating portion a on the gate insulating film.

Further, a corner of the upper surface of the convex insulating portion may be formed as a curved surface.

[0016]

According to the above construction, the gate electrode end is formed corresponding to the section (offset section) located above the drain contact layer in the inclined portion (taper section) of the convex insulating portion on the trapezoidal cross section. In this case, a desired offset structure is obtained, and the off-state current can be reduced. On the other hand, even when the gate electrode formation is misaligned and the gate electrode end is formed above the drain contact layer, the gap between the gate electrode and the active layer remains between the gate electrode and the drain contact layer. Since the gate insulating film having a larger thickness is interposed therebetween, an effect of reducing off-current can be obtained.

The edge of the drain contact layer is restricted in position by the above-mentioned etching process by the convex insulating portion, and the thick portion of the gate insulating film is also formed with reference to the convex insulating portion. Is done. Therefore, the thick portion of the gate insulating film is accurately formed on the drain contact layer in a self-aligned manner, and an increase in current leakage due to the displacement is avoided.

Further, the convex insulating portion has a trapezoidal section having a trapezoidal cross section whose bottom side is larger than the upper side, so that the influence on the on-current due to the displacement of the formation position of the gate electrode is reduced. That is, if the convex insulating portion has a rectangular cross section, the side surface of the convex insulating portion is cut off at the end of the drain contact layer, and whether or not the gate electrode end is located on the drain contact layer at this side surface is determined. This causes variation in the ON current, but the presence of the tapered portion reduces the variation in the ON current.

The thickness of the thick portion of the insulating film is determined by the thickness of the convex insulating portion and the thickness of the insulating film on the active layer. The thickness is set so as to be reduced.

Further, since the convex insulating portion is formed to have a trapezoidal cross section, the pattern of the active layer formed on the convex insulating portion is prevented from being cut. In addition, since the corners of the upper surface of the convex insulating portion are formed as curved surfaces, the above-described pattern is prevented from being cut and the withstand voltage of the gate insulating film is prevented from lowering.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) The present invention will be described below with reference to FIGS. FIG. 1 is a longitudinal sectional view of a thin film transistor. Reference numeral 1 denotes an insulating transparent substrate, and this substrate 1 is formed of, for example, glass. On the insulating substrate 1, lower insulating film 2 made of SiO ₂ is formed. This is lower insulating film 2, the base has a larger cross-section trapezoidal than the upper side, the width of the tapered portion is somewhat larger and the convex insulating portion 2a is formed from the offset section (described later T _V interval) I have.

A drain contact layer 3a is formed on one side of the convex insulating portion 2a, and a source contact layer 3b is formed on the other side. These contact layers 3a and 3b are both formed lower than the convex insulating portion 2a. In addition, these contact layers 3a and 3b
Is a n ⁺ layer 3, the n ⁺ layer 3, n ⁺ -type a-Si
This is an n ⁺ -type p-Si layer (polycrystalline silicon layer) obtained by subjecting a layer (amorphous silicon layer) to certain processing described later.

On the convex insulating portion 2a, an active layer 4 having a thickness of 300.degree. Is formed so as to straddle the convex insulating portion 2a. One end of the active layer 4 is connected to the drain contact layer 3a, and the other end is connected to the source contact layer 3b. The active layer 4 is an i-layer, and the i-layer is an i-type p-Si layer obtained by subjecting the i-type a-Si layer to a certain process described later.

The drain contact layer 3a, the source contact layer 3b, and the convex insulating portion 2a have S
The flattened gate insulating film 5 made of iO ₂ has a thickness of 1500 ° on the channel portion and approximately 7000 ° on the n ⁺ layer 3. On the flattened gate insulating film 5 and at a position corresponding to the convex insulating portion 2a, Al
A gate electrode 7c made of (aluminum) is formed.

A drain electrode 7a made of Al is formed on the flattened gate insulating film 5 at a position corresponding to the drain contact layer 3a, and this electrode 7a is formed on the flattened gate insulating film 5. Connected to the drain contact layer 3a through the contact hole. A source electrode 7b made of Al is formed on the planarized gate insulating film 5 at a position corresponding to the source contact layer 3b, and the electrode 7b is formed on the planarized gate insulating film 5. It is connected to the source contact layer 3b through the contact hole.

FIG. 2 is an enlarged sectional view showing the vicinity of the drain-gate in the thin film transistor having the above structure. In this embodiment, T _V and T _H in the figure are each 7000 °. Here, the above T _H indicates the height from the upper surface of the convex insulating portion 2a to the upper surface position of the drain contact layer 3a, the offset of the width of the tapered portion above T _V is the convex insulating portion 2a The width of the section is shown.

FIG. 3 is a graph showing the gate voltage-drain current characteristics of the thin film transistor having the above structure. Graph c shows the characteristics when ΔL = 0.5 μm in FIG. 2, and graph d shows the characteristics when ΔL = −0.5 μm. The case where ΔL = 0.5 μm means that the formation position of the gate electrode 7c is shifted to the left by 0.5 μm from the position indicated by the broken line in the drawing, and ΔL = −0.5 μm.
The case of m means that the formation position of the gate electrode 7c is shifted to the right by 0.5 μm from the position of the broken line in the figure.
Note that the voltage (V _DS ) between the drain and the source is 5 V, and the gate width / gate length (W / L) is 10 μm / 10 μm.

As is clear from the graphs c and d in FIG.
When the end of the gate electrode 7c is formed corresponding to a section (offset section) located above the drain contact layer 3a in the tapered section (that is, ΔL = −
(In the case of 0.5 μm), a desired offset structure can be obtained, and the off-state current can be reduced. On the other hand, even when a position shift occurs in the formation of the gate electrode and the end of the gate electrode 7c is formed above the drain contact layer 3a (that is, when ΔL = 0.5 μm described above), the gate electrode 7c is not Since the gate insulating film 5 having a larger thickness than that between the gate electrode 7c and the active layer 4 is interposed between the drain contact layer 3a, an effect of reducing off current can be obtained. That is, the above-described offset section and a section slightly larger than the above-mentioned offset section become the positional deviation allowable width for forming the drain electrode.

Further, since the convex insulating portion 2a has a tapered portion having a trapezoidal section whose bottom side is larger in cross section than the upper side, the influence on the on-current due to the displacement of the formation position of the gate electrode 7c is reduced. That is, when the convex insulating portion 2a has a rectangular cross section, the side surface of the convex insulating portion 2a is cut off at the end of the drain contact layer 3a, and the end of the gate electrode 7c is located on the drain contact layer 3a with this side surface as a boundary. The on-current varies depending on whether or not it is performed. However, the presence of the tapered portion reduces the variation in the on-current.

Since the convex insulating portion 2a has the tapered portion, the convex insulating portion 2a is formed on the convex insulating portion 2a as compared with the case where the cross-sectional shape of the convex insulating portion 2a is square. Poor pattern disconnection of the active layer 4 is less likely to occur.

Next, a method of manufacturing the thin film transistor having the above structure will be described with reference to FIG. As shown in FIG. 4A, first, a lower insulating film 2 is formed on an insulating substrate 1. For example, the insulating substrate 1 is loaded into a chamber of a CVD apparatus, and Si is used as a reaction gas in the CVD apparatus.
H ₄ and O ₂ are injected, the formation temperature is set to 400 ° C., and normal pressure C
By applying the VD method, a 1 μm thick
The lower insulating film 2 made of SiO ₂ is formed.

Next, a resist film 10 corresponding to the position where the convex insulating portion 2a is to be formed and its size is formed, and this resist and the lower insulating film 2 are etched at substantially the same etching rate. As shown in (b), a convex insulating portion 2a having a trapezoidal cross section whose bottom side is larger than the top side and whose width of the tapered portion is somewhat larger than the offset section is formed. In this etching, the inclination angle of the tapered portion of the trapezoid can be adjusted by adjusting the combination of isotropic etching and anisotropic etching. The inclination angle is desirably in the range of 30 ° to 60 °, and the etching depth is desirably in the range of 5000 ° to 10000 °.

Next, as shown in FIG. 3C, an n ⁺ -type p-Si film is formed on the lower insulating film 2 on which the convex insulating portion 2a is formed.
The layer 3 is formed. For example, the formation temperature is 400 ° C., the pressure is 6.7 Pa, the RF power is 0.01 W / cm ² ,
In a mixed gas atmosphere of H ₃ / SiH ₄ = 2%, a 1500 ° thick n ⁺ -type a-Si
Form a layer. Then, after performing a heat treatment on the n ⁺ -type a-Si layer, an ArF excimer laser (250 m
(J / cm ² ) is crystallized by annealing for 8 shot irradiation to obtain an n ⁺ -type p-Si layer 3.

Next, as shown in FIG. 3D, the resist film 11 is formed flat. Then, by applying an etch-back method, a gas ratio of CF ₄ and O ₂ is selected so that the resist film 11 and the n ⁺ -type p-Si layer 3 have the same etching rate, and dry etching is performed under these conditions. Then, the n ⁺ -type p-Si layer 3 on the convex insulating portion 2a is removed, and the n ⁺ -type p-Si layer 3 on the side of the convex insulating portion 2a remains. The remaining n ⁺ -type p-Si layer 3 on one side becomes a drain contact layer 3a, and the n ⁺ -type p-Si layer 3 on the other side becomes a source contact layer 3b. At this time, each edge (drain end, source end) of both contact layers 3a and 3b is regulated in position by the convex insulating portion 2a. The etching rate for SiO ₂ in the etching process (convex portion 2a) is selected to sufficiently small, the SiO ₂
Reduce the damage to.

Next, as shown in FIG. 3E, the convex insulating portion 2a is straddled on the convex insulating portion 2a.
An i-type p-Si layer which is the active layer 4 is formed. For example, an i-type a-S with a thickness of 300 ° is formed by a plasma CVD method in a SiH ₄ gas atmosphere at a forming temperature of 400 ° C., a pressure of 6.7 Pa, an RF power of 0.01 W / cm ^2.
An i-layer is formed. Then, after performing a heat treatment on the i-type a-Si layer, an ArF excimer laser (250 m
(J / cm ² ) is crystallized by annealing for 8 shot irradiation to obtain an i-type p-Si layer.

Next, as shown in FIG. 4F, a SiO ₂ layer 5 ′ is formed with a thickness of 1 μm by a sputtering method, and then, under the conditions for bias sputtering as shown in FIG. the thickness of the channel portion in the sputtering process to planarize the SiO ₂ layer 5 'so that 1500 Å. Thus, a planarized gate insulating film 5 is formed.
Note that the thickness of the planarized gate insulating film 5 on the n ⁺ layer 3 is about 7000 °.

Next, after a contact hole is formed at a predetermined position of the planarized gate insulating film 5,
An Al film is formed thereon by a vacuum evaporation method. Then, by patterning the Al film by photolithography,
As shown in FIG. 1H, a drain electrode 7a, a source electrode 7b, and a gate electrode 7c are formed.

Through the above steps, the thin film transistor of this embodiment is manufactured.

As described above, the position of the edge of the drain contact layer 3a is regulated with reference to the convex insulating portion 2a, and the thick portion of the gate insulating film 5 can be formed by the above-described manufacturing method. It is formed based on the above-mentioned convex insulating portion 2a. Therefore, the thick portion of the gate insulating film 5 is accurately formed in a self-aligned manner on the drain contact layer 3a, and an increase in current leak due to this displacement is avoided.

(Embodiment 2) Another embodiment of the present invention will be described with reference to FIG. As shown in FIG. 5, the thin film transistor of this embodiment has a convex upper surface having a curved upper surface formed by a convex insulating portion 2a formed by a lower insulating layer 2 and a second insulating layer 2 'formed on the upper surface thereof. It has a structure having an insulating portion 2a '.

According to the above configuration, the convex insulating portion 2
In addition, it is possible to make it difficult for the active layer 4 formed on a ′ to have a pattern breakage, and to prevent a reduction in the withstand voltage of the gate insulating film 5 at the corner of the curved upper surface.

In the case of manufacturing this thin film transistor, after the convex insulating portion 2a 'is formed in the etching step of FIG. 4B described in the first embodiment, the SiO 2 serving as the second insulating layer 2' is formed. _{The two} films may be formed by the CVD method, and the subsequent steps are the same as in the first embodiment.

[0043]

As described above, according to the present invention, it is possible to avoid an increase in off-state current even if a position shift occurs in the formation of a gate electrode, and for example, to improve the uniformity of characteristics in a large-area array. become.

In addition, the thick portion of the gate insulating film is accurately formed on the drain contact layer in a self-aligned manner, so that an increase in current leak due to the displacement can be avoided. .

Further, the presence of the tapered portion as described above reduces the variation in the on-current. Similarly, the presence of the tapered portion prevents the active layer formed on the protruding insulating portion from having a pattern breakage. Further, since the upper surface corners of the convex insulating portion are formed into a curved surface, the above-described pattern disconnection failure is prevented, the withstand voltage of the gate insulating film is prevented from lowering, and the yield is improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a thin film transistor of the present invention.

FIG. 2 is an enlarged sectional view showing the vicinity of a drain and a gate in the thin film transistor of the present invention.

FIG. 3 is a graph showing a gate voltage-drain current characteristic of the thin film transistor of the present invention.

FIG. 4 is a process chart showing a method for manufacturing a thin film transistor of the present invention.

FIG. 5, showing another embodiment of the present invention, is a longitudinal sectional view of a thin film transistor having a convex insulating portion having a curved upper surface corner.

FIG. 6 is a longitudinal sectional view showing a conventional coplanar thin film transistor.

FIG. 7 is a longitudinal sectional view showing a conventional staggered thin film transistor.

FIG. 8 is a longitudinal sectional view showing a conventional thin film transistor having a coplanar structure and an off-current reduction structure.

FIG. 9A is a longitudinal sectional view showing a thin film transistor when a gate electrode is formed with an appropriate offset in a conventional staggered structure, and FIG. 9B is a vertical sectional view of the conventional staggered structure. It is a longitudinal cross-sectional view which shows the thin film transistor when the shift | offset | difference arises in the formation position of an electrode.

FIG. 10 is a graph showing gate voltage-drain current characteristics of a conventional thin film transistor, and graph a is shown in FIG.
The characteristics of the thin film transistor of FIG.
9 shows characteristics of the thin film transistor shown in FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 insulating substrate 2 lower insulating film 2 ′ second insulating layer 2 a convex insulating portion 2 a ′ convex insulating portion 3 n ⁺ -type p-Si layer 3 a drain contact layer 3 b source contact layer 4 active layer 5 flattened gate insulation Film 7 Al layer 7a drain electrode 7b source electrode 7c gate electrode

Claims (3)

(57) [Claims] 1. A formed on an insulating substrate, a convex insulating portion having a larger cross-section trapezoidal base is from the upper side, the upper surface position of the one side by the convex insulating portion of the convex insulating portion and the drain contact layer which is formed at a lower height, and a source contact layer formed on a lower height than the upper surface position of the convex insulating portion on the other side of the convex shaped insulating portion, the convex insulation covering one end side is across by forming the upper part and the active layer other end connected to a drain contact layer is connected to the source contact layer, and said <br/> source contact layer and the active layer and the front Kido rain contact layer A thin film transistor, comprising: a gate insulating film formed flat and flat; and a gate electrode formed on the gate insulating film at a position corresponding to the convex insulating portion. 2. The thin film transistor according to claim 1, wherein a corner of the upper surface of the convex insulating portion is formed as a curved surface. Wherein the lower insulating film is formed on an insulating substrate, the bottom side by the lower insulating film have a larger cross-section trapezoidal than the upper side
Forming a convex insulating portion which, forming a contact layer on the lower insulating film including the convex insulating portion, before
A step of flat forming resist film on the serial contact layer, the said contact layer and the resist film, the convex shaped insulating portions are exposed, further upper surface position of the contact layer before
And etching until the lower surface position of the serial convex insulating portion, to form an active layer on the end portion of the contact layer located on the side of the convex shaped insulating portion and the exposed and the convex insulating portion and a step, a step of flat forming a gate insulating layer on the active layer and the contact layer, forming a gate electrode at a position corresponding to the convex insulating portion a on the gate insulating film, the A method for manufacturing a thin film transistor, comprising: