JPH06244427A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a thin-film transistor having a structure in which an increase in off-state current is avoided even if an offset gate is deviated. CONSTITUTION:An insulating mesa 2a is formed on an insulating substrate 1. A drain contact layer 3a and a source contact layer 3b, which are lower than the mesa, are formed on opposite sides of the mesa. The drain contact layer and the source contact layer are connected through an active layer 4 that extends over the mesa. The active layer and the drain and source contact layers are covered with a flat gate oxide 5. A gate electrode 7c is formed on the gate oxide above the mesa.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as "TFT"), and more particularly, to a thin film transistor having a structure in which even if a misalignment occurs in the formation of a gate electrode, a defect accompanying the misalignment does not occur and its manufacture. Regarding the method.

[0002]

2. Description of the Related Art FIGS. 6 and 7 are sectional views showing a conventional TFT structure. FIG. 6 shows a coplanar structure TFT.
Indicates a staggered TFT. In each drawing, 100 is an insulating substrate, 101 is a drain contact doped layer, 102 is a source contact doped layer, and 103.
Is an active layer, 104 is a gate insulating film, 105 is a gate electrode, 106 is a drain electrode, and 107 is a source electrode. The contact dope layers 101 and 102 and the active layer 103 in such a TFT are formed of, for example, amorphous silicon (hereinafter referred to as a-Si) or polycrystalline silicon (hereinafter referred to as p-Si). To be done.

By the way, it is known that the electron mobility of the above a-Si is low, and in recent years, a
The development of TFTs made of p-Si that can realize electron transfer of about 10 to 1000 times that of -Si is under way.

However, this p-Si.TFT has a drawback that the leak current is large. For this reason,
Attempts have been made to reduce the leak current by providing the TFT with a structure that weakens the gate electric field strength at the drain end.

FIG. 8 shows a leak current reduction structure in the TFT having the above-mentioned coplanar structure. By providing the n ⁻ layer 101a at the drain end, LDD (L
The gate electrode electric field strength is weakened at the drain end.

On the other hand, FIG. 9A shows a leak current reduction structure in the above-mentioned staggered TFT, which is on the right side with respect to the position of the broken line in the figure (hereinafter referred to as the minus side). ) By positioning the gate electrode
That is, the electric field strength at the drain end is weakened by providing a constant gap (offset) between the drain end and the gate end.

[0007]

However, the n ⁻ layer 101a can be formed by self-alignment with the gate electrode 105 by ion implantation or ion doping, but since the film thickness is as thin as several hundred Å. Dope control is not easy. Further, although annealing is required, there is a defect that the heat at that time adversely affects other constituent materials.

On the other hand, in the above-mentioned offset gate structure, the formation position of the gate electrode 105 may be deviated as shown in FIG. 9B due to patterning misalignment when the gate electrode 105 is formed. is there. FIG. 10 is a graph showing the relationship between the gate voltage and the drain current in the TFT. In graph a, an appropriate offset of ΔL (0.5 μm) was obtained from the position of the broken line in FIG. Graph b shows the characteristics when
Is ΔL from the position of the broken line to the plus side in (b) of FIG.
The characteristic is shown when there is a shift (0.5 μm). In addition,
The voltage (V _DS ) between the drain and the source is 5 V, and the gate width / gate length (W / L) is 10 μm / 10 μm.

When a proper offset structure is obtained as shown in FIG. 9A, the off-current can be reduced as shown in the graph a, but as shown in FIG. 9B, the position where the gate electrode 105 is formed is deviated. Occurs, the off current reduction effect cannot be obtained as shown in the graph b. Although not shown in the figure, when the offset becomes too large in FIG. 9A, the effect of reducing the off current is saturated, but
The decrease in on-current becomes remarkable.

As a solution to the above problems, a TFT having a structure in which the gate insulating film is thicker between the gate electrode and the drain region than in the channel region has been devised. (JP-A-3-108
374 (International Patent Classification H01L29 / 78)). That is, by making the gate insulating film thick on the channel region, the electric field strength from the gate in the drain region is weakened to reduce the off current.

However, in the above-mentioned conventional TFT, it is difficult to set the process condition that the thick portion of the gate insulating film is accurately and uniformly formed on the drain region. Therefore, when the position shift occurs, leakage occurs. There is a drawback that it causes an increase in current.

In view of the above circumstances, the present invention is basically based on the purpose of reducing the electric field strength at the gate end by the offset structure, and even if the position of the gate electrode is displaced due to the formation of the offset structure. , A thick gate insulating film on the drain region can ensure the effect of reducing the off-current, and a thick gate insulating film can be accurately formed on the drain region. An object of the present invention is to provide a thin film transistor having a structure in which the on-current is hardly affected regardless of the position of the gate electrode end in the offset section, and a manufacturing method thereof.

[0013]

In order to solve the above problems, a thin film transistor of the present invention comprises a convex insulating portion formed on an insulating substrate and having a trapezoidal cross section whose bottom side is larger than that of the upper side. A drain contact layer formed at a lower height on one side of the convex insulating portion, and a source contact layer formed at a lower height on the other side of the convex insulating portion, An active layer formed over the convex insulating portion and having one end side connected to the drain contact layer and the other end side connected to the source contact layer, and covering the active layer, the drain contact layer, and the source contact layer. It is characterized in that it has a gate insulating film formed flat and a gate electrode formed on the planarized gate insulating film at a position corresponding to the convex insulating portion.

In the method of manufacturing a thin film transistor of the present invention, a step of forming a lower layer insulating film on an insulating substrate and forming a trapezoidal cross section whose bottom side is larger than the upper side by this lower layer insulating film, and this convex insulating film A step of forming a contact layer on the lower insulating film including a portion, a step of flatly forming a resist film on the contact layer, the contact layer and the resist film, the convex insulating portion is exposed, Further, a step of etching until the upper surface position of the contact layer is lower than the upper surface position of the convex insulating portion, and the end of the contact layer located on the exposed convex insulating portion and on the side portion of the convex insulating portion. A step of forming an active layer on the portion, and a step of forming a gate insulating film flat on the active layer and the contact layer,
And a step of forming a gate electrode on the planarized gate insulating film at a position corresponding to the convex insulating portion.

The corners of the upper surface of the convex insulating portion may be curved.

[0016]

According to the above structure, the gate electrode end is formed corresponding to the section (offset section) located above the drain contact layer in the inclined section (taper section) of the convex insulating section having a trapezoidal cross section. In this case, a desired offset structure can be obtained, and off current can be reduced. On the other hand, even when the gate electrode formation is misaligned and the end of the gate electrode is formed above the drain contact layer, the gate electrode and the active layer are not separated from each other between the gate electrode and the drain contact layer. Since the gate insulating film having a larger film thickness than that in the gap is interposed, the effect of reducing the off current can be obtained.

Further, the edge portion of the drain contact layer is position-regulated by the convex insulating portion by the above-mentioned etching treatment, and the thick portion of the gate insulating film is also formed on the basis of the convex insulating portion. To be done. Therefore, the thick portion of the gate insulating film is accurately formed on the drain contact layer in a self-aligned manner, and an increase in current leakage due to this positional deviation can be avoided.

Furthermore, the convex insulating portion has a trapezoidal cross section whose bottom side is larger than the top side and has a taper portion, so that the influence on the on-current due to the displacement of the formation position of the gate electrode is alleviated. That is, if the convex insulating portion has a rectangular cross section, the side surface of the convex insulating portion is cut up at the edge of the drain contact layer, and the edge of the gate electrode may be positioned on the drain contact layer with the side surface as a boundary. As a result, the on-current varies, but the presence of the tapered portion reduces the variation in the on-current.

The thickness of the thick film portion of the insulating film is determined by the thickness of the convex insulating portion and the thickness of the insulating film on the active layer. The thickness does not decrease the on-current but the off-current. The thickness is set to reduce.

Further, since the convex insulating portion is formed to have a trapezoidal cross section, pattern breakage of the active layer formed on the convex insulating portion can be prevented. Further, by forming the curved corners of the upper surface of the convex insulating portion, it is possible to prevent the pattern breakage and prevent the breakdown voltage of the gate insulating film from decreasing.

[0021]

(Embodiment 1) The present invention will be described below with reference to FIGS. 1 to 4 showing an embodiment thereof. FIG. 1 is a vertical sectional view of a thin film transistor. Reference numeral 1 is an insulating transparent substrate, and this substrate 1 is made of, for example, glass. On the insulating substrate 1, lower insulating film 2 made of SiO ₂ is formed. The lower insulating film 2 is formed with a convex insulating portion 2a having a trapezoidal cross section whose bottom side is larger than that of the upper side, and the width of the taper portion of which is somewhat larger than the offset section (T _V section described later). There is.

A drain contact layer 3a is formed on one side of the convex insulating portion 2a, and a source contact layer 3b is formed on the other side. Both of these contact layers 3a and 3b are formed lower than the convex insulating portion 2a. In addition, these contact layers 3a and 3b
Is an n ⁺ layer 3, and the n ⁺ layer 3 is an n ⁺ type a-Si.
It is an n ⁺ -type p-Si layer (polycrystalline silicon layer) obtained by subjecting the layer (amorphous silicon layer) to a certain treatment described later.

An active layer 4 having a film thickness of 300Å is formed on the convex insulating portion 2a so as to straddle the convex insulating portion 2a. One end of the active layer 4 is connected to the drain contact layer 3a, and the other end is connected to the source contact layer 3b. The active layer 4 is an i layer, and the i layer is an i type p-Si layer obtained by subjecting the i type a-Si layer to a certain process described later.

S is formed on the drain contact layer 3a, the source contact layer 3b, and the convex insulating portion 2a.
The planarized gate insulating film 5 made of iO ₂ has a thickness of 1500 Å on the channel portion and a thickness of about 7,000 Å on the n ⁺ layer 3. Then, at a position on the flattened gate insulating film 5 corresponding to the convex insulating portion 2a, Al is formed.
A gate electrode 7c made of (aluminum) is formed.

A drain electrode 7a made of Al is formed on the flattened gate insulating film 5 at a position corresponding to the drain contact layer 3a. The electrode 7a is formed on the flattened gate insulating film 5. The drain contact layer 3a is connected through the contact hole. A source electrode 7b made of Al is formed on the flattened gate insulating film 5 at a position corresponding to the source contact layer 3b. The electrode 7b is formed on the flattened gate insulating film 5. It is connected to the source contact layer 3b through the contact hole.

FIG. 2 is an enlarged sectional view in the vicinity of the drain-gate in the thin film transistor having the above structure. In this embodiment, T _V and T _H in the figure are each set to 7,000 Å. Here, the above T _H indicates the height from the upper surface of the convex insulating portion 2a to the upper surface position of the drain contact layer 3a, the offset of the width of the tapered portion above T _V is the convex insulating portion 2a The width of the section is shown.

FIG. 3 is a graph showing gate voltage-drain current characteristics of the thin film transistor having the above structure. The graph c shows the characteristic when ΔL = 0.5 μm in FIG. 2, and the graph d shows the characteristic when ΔL = −0.5 μm. The case of ΔL = 0.5 μm means the case where the formation position of the gate electrode 7c is deviated from the position of the broken line in the figure by 0.5 μm to the left side, and ΔL = −0.5 μm.
The case of m means that the formation position of the gate electrode 7c is shifted from the position of the broken line in the figure by 0.5 μm to the right.
The voltage between drain and source (V _DS ) is 5 V, and the gate width / gate length (W / L) is 10 μm / 10 μm.

As is clear from the graphs c and d in FIG.
When the end of the gate electrode 7c is formed corresponding to a section (offset section) located above the drain contact layer 3a in the tapered section (that is, ΔL = −
In the case of 0.5 μm), a desired offset structure can be obtained, and the off current can be reduced. On the other hand, even when the gate electrode formation is misaligned and the end of the gate electrode 7c is formed above the drain contact layer 3a (that is, when ΔL = 0.5 μm described above), the gate electrode 7c and Since the gate insulating film 5 having a thickness larger than that between the gate electrode 7c and the active layer 4 is interposed between the drain contact layer 3a and the drain contact layer 3a, an effect of reducing the off current can be obtained. That is, the offset section and a section slightly larger than the offset section are the positional deviation permissible widths for forming the drain electrode.

Also, since the convex insulating portion 2a has a trapezoidal section with a larger base than the upper side and a tapered portion, the influence on the on-current due to the displacement of the formation position of the gate electrode 7c is alleviated. That is, when the convex insulating portion 2a has a rectangular cross section, the side surface of the convex insulating portion 2a is cut off at the edge of the drain contact layer 3a, and the edge of the gate electrode 7c is located on the drain contact layer 3a with this side surface as a boundary. The ON current varies depending on whether the ON current is applied or not, but the tapered ON portion as described above reduces the ON current variation.

Further, since the convex insulating portion 2a has the tapered portion, it is formed on the convex insulating portion 2a as compared with the case where the convex insulating portion 2a has a rectangular cross section. The pattern cutting defect of the active layer 4 is less likely to occur.

Next, a method of manufacturing the thin film transistor having the above structure will be described with reference to FIG. As shown in FIG. 4A, first, the lower insulating film 2 is formed on the insulating substrate 1. For example, the insulating substrate 1 is loaded into a chamber of a CVD apparatus, and Si is used as a reaction gas in the CVD apparatus.
H ₄ and O ₂ are injected, the forming temperature is 400 ° C., and the atmospheric pressure is C
By applying the VD method, the thickness on the insulating substrate 1 is 1 μm.
The lower insulating film 2 made of SiO ₂ is formed.

Next, a resist film 10 corresponding to the position and size of the convex insulating portion 2a to be formed is formed, and this resist and the lower insulating film 2 are etched at the same etching rate. As shown in (b), a convex insulating portion 2a having a trapezoidal cross section whose base is larger than that of its upper side and whose taper width is somewhat larger than that of the offset section is formed. In this etching, the inclination angle of the trapezoidal tapered portion can be adjusted by adjusting the combination of isotropic etching and anisotropic etching. The inclination angle is preferably in the range of 30 ° to 60 °, and the etching depth is preferably in the range of 5000Å to 10000Å.

Next, as shown in FIG. 3C, n ⁺ type p-Si is formed on the lower insulating film 2 having the convex insulating portion 2a formed thereon.
Form layer 3. For example, the formation temperature is 400 ° C., the pressure is 6.7 Pa, the RF power is 0.01 W / cm ^2, and P
An n ⁺ type a-Si having a thickness of 1500 Å was formed by a plasma CVD method in a mixed gas atmosphere of H ₃ / SiH ₄ = 2%.
Form the layers. Then, after heat-treating the n ⁺ -type a-Si layer, an ArF excimer laser (250 m
Crystallization is performed by an annealing treatment of irradiating 8 shots of J / cm ² ) to obtain an n ⁺ type p-Si layer 3.

Next, as shown in FIG. 3D, the resist film 11 is formed flat. Then, by applying the etch back method, the gas ratio of CF ₄ and O ₂ is selected so that the resist film 11 and the n ⁺ type p-Si layer 3 have the same etching rate, and dry etching is performed under these conditions. Then, the n ⁺ -type p-Si layer 3 on the convex insulating portion 2a is removed, and the n ⁺ -type p-Si layer 3 on the side of the convex insulating portion 2a is left. The remaining n ⁺ -type p-Si layer 3 on one side becomes the drain contact layer 3a, and the n ⁺ -type p-Si layer 3 on the other side becomes the source contact layer 3b. At this time, the respective edges (drain end, source end) of both contact layers 3a and 3b are positionally regulated by the convex insulating portion 2a. The etching rate for SiO ₂ in the etching process (convex portion 2a) is selected to sufficiently small, the SiO ₂
Reduce damage to.

Next, as shown in (e) of the figure, on the convex insulating portion 2a, so as to straddle the convex insulating portion 2a,
An i-type p-Si layer which is the active layer 4 is formed. For example, the formation temperature is 400 ° C., the pressure is 6.7 Pa, the RF power is 0.01 W / cm ^2, and the i-type a-S having a thickness of 300 Å is formed by the plasma CVD method in the SiH ₄ gas atmosphere.
Form the i-layer. Then, after heat-treating the i-type a-Si layer, an ArF excimer laser (250 m
Crystallization is performed by an annealing treatment of irradiating 8 shots of J / cm ² ) to obtain an i-type p-Si layer.

Next, as shown in FIG. 2F, a SiO ₂ layer 5'is formed to a thickness of 1 μm by a sputtering method, and then, as shown in FIG. 3G, under the condition that bias sputtering is performed. The SiO ₂ layer 5 ′ is flattened by the sputtering process so that the thickness on the channel portion becomes 1500 Å. As a result, the flattened gate insulating film 5 is formed.
The thickness of the flattened gate insulating film 5 on the n ⁺ layer 3 is about 7,000 Å.

Next, after forming a contact hole at a predetermined position in the flattened gate insulating film 5, the flattened gate insulating film 5 is formed.
An Al film is formed on the top by a vacuum deposition method. Then, by patterning the Al film by the photoetching method,
As shown in FIG. 3H, the drain electrode 7a, the source electrode 7b, and the gate electrode 7c are formed.

Through the above steps, the thin film transistor of this embodiment is manufactured.

By the manufacturing method described above, the edge of the drain contact layer 3a is position-regulated with the convex insulating portion 2a as a reference as described above, and the thick portion of the gate insulating film 5 is also formed. It is formed on the basis of the convex insulating portion 2a. Therefore, the thick portion of the gate insulating film 5 is accurately formed on the drain contact layer 3a in a self-aligned manner, and an increase in current leakage due to this positional deviation can be avoided.

(Embodiment 2) Another embodiment of the present invention will be described with reference to FIG. As shown in FIG. 5, the thin film transistor of this example has a convex insulating portion 2a formed by the lower insulating layer 2 and a second insulating layer 2'formed on the upper surface of the convex insulating portion 2a. It has a structure having a strip-shaped insulating portion 2a '.

According to the above configuration, the convex insulating portion 2 is provided.
The pattern breakage of the active layer 4 formed on a'is less likely to occur, and the breakdown voltage of the gate insulating film 5 at the curved upper surface corners can be prevented.

Further, in the case of manufacturing this thin film transistor, after the convex insulating portion 2a 'is formed by the etching process of FIG. 4 (b) described in the embodiment 1, the SiO 2 which becomes the second insulating layer 2'is formed. _{The two} films may be formed by the CVD method, and the subsequent steps are the same as in the first embodiment.

[0043]

As described above, according to the present invention, it is possible to avoid an increase in off-current even if the gate electrode is misaligned, and for example, to improve the uniformity of characteristics in a large-area array. become.

Further, the thick portion of the gate insulating film is accurately formed on the drain contact layer in a self-aligned manner, and an increase in current leakage due to this positional deviation can be avoided. .

Further, the taper portion as described above alleviates the variation in the ON current. Similarly, by having the above-described tapered portion, defective pattern cutting of the active layer formed on the convex insulating portion can be prevented. In addition, by forming the corners of the upper surface of the convex insulating portion in a curved surface, it is possible to prevent the above-mentioned defective pattern cutting, prevent the breakdown voltage of the gate insulating film from being lowered, and improve the yield.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a thin film transistor of the present invention.

FIG. 2 is an enlarged cross-sectional view showing the vicinity of a drain and a gate in the thin film transistor of the present invention.

FIG. 3 is a graph showing gate voltage-drain current characteristics of the thin film transistor of the present invention.

FIG. 4 is a process drawing showing the method of manufacturing the thin film transistor of the present invention.

FIG. 5 shows another embodiment of the present invention, and is a vertical cross-sectional view of a thin film transistor having a convex insulating portion with a curved upper surface corner portion.

FIG. 6 is a vertical cross-sectional view showing a conventional thin film transistor having a coplanar structure.

FIG. 7 is a vertical sectional view showing a conventional staggered thin film transistor.

FIG. 8 is a vertical cross-sectional view showing a thin film transistor having a conventional coplanar structure and an off-current reducing structure.

9A is a vertical cross-sectional view showing a thin film transistor having a conventional staggered structure with an appropriate offset for forming a gate electrode, and FIG. 9B is a conventional staggered structure with a gate. FIG. 6 is a vertical cross-sectional view showing a thin film transistor when a position where an electrode is formed is displaced.

FIG. 10 is a graph showing gate voltage-drain current characteristics of a conventional thin film transistor, where graph a is FIG.
The characteristics of the thin film transistor of (a) are shown in graph b.
Shows the characteristics of the thin film transistor of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Lower insulating film 2'Second insulating layer 2a Convex insulating part 2a 'Convex insulating part 3 n ⁺ type p-Si layer 3a Drain contact layer 3b Source contact layer 4 Active layer 5 Flattened gate insulation Film 7 Al layer 7a Drain electrode 7b Source electrode 7c Gate electrode

Claims (3)

[Claims] 1. A convex insulating portion formed on an insulating substrate and having a base having a trapezoidal cross section whose base is larger than that of the upper side, and one side of the convex insulating portion is formed at a height lower than that. The drain contact layer, the source contact layer formed on the other side of the convex insulating portion at a height lower than this, and the one end side connected to the drain contact layer formed over the convex insulating portion. An active layer having the other end side connected to the source contact layer, a gate insulating film formed flat to cover the active layer, the drain contact layer, and the source contact layer, and the flattened gate insulating film. And a gate electrode formed at a position corresponding to the convex insulating portion. 2. The thin film transistor according to claim 1, wherein a corner of the upper surface of the convex insulating portion is formed into a curved surface. 3. A step of forming a lower layer insulating film on an insulating substrate and forming a trapezoidal cross section with a bottom side larger than the upper side by the lower layer insulating film, and including the convex insulating portion on the lower layer insulating film. The step of forming a contact layer, the step of forming a flat resist film on the contact layer, the contact layer and the resist film, the convex insulating portion is exposed, and the upper surface position of the contact layer is A step of etching until it becomes lower than the upper surface position of the convex insulating part, and a step of forming an active layer on the exposed convex insulating part and on an end of a contact layer located on a side part of the convex insulating part. And a step of forming a gate insulating film flat on the active layer and the contact layer, and a step of forming a gate electrode on the flattened gate insulating film at a position corresponding to the convex insulating portion. Characterized by including Method of manufacturing thin film transistor.