JP3209208B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an air bridge wiring, and more particularly to a semiconductor device having an air bridge wiring excellent in high frequency characteristics and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, there has been known a semiconductor device having an air bridge wiring as disclosed in Japanese Patent Application Laid-Open No. H5-211179. The detailed configuration of such a semiconductor device is shown in FIGS.
As shown in FIG. 1, a transistor 10 including a gate electrode 2, a source electrode 3, and a drain electrode 4 is formed on an appropriate substrate 1, and as one specific example, protrudes from the gate electrode in parallel with each other. The source electrode bus 6 connecting the source electrodes 3 formed with the gate electrode 2 interposed therebetween at a predetermined interval in every other space between the gate finger portions 5, that is, in the space 11, A protruding source finger portion 7 is disposed, and finally a drain finger portion 8 protruding from the drain electrode 4 disposed along the source electrode bus 6 crosses the space above the source electrode bus 6. It is configured so as to be disposed in the remaining space portion 12 of the space portion between the gate finger portions 5.

In such a configuration, as shown in FIG. 4, a drain finger portion 8 intersects with the source electrode bus 6 via a space 13 formed above the source electrode bus 6. It is. Semiconductor device 10 having such a configuration.
In particular, since an air layer having a low dielectric constant is present between the drain finger portion 8 and the source electrode bus 6, it is possible to form a transistor having less generation of capacitance and therefore having excellent high frequency characteristics. .

However, in a semiconductor device having such a structure, a plurality of transistors are formed in a matrix on one wafer as a method of manufacturing the semiconductor device.
In the process, for example, there is a step of polishing the back surface of the substrate, or in a step of separating and cutting each transistor from the wafer to form an individual chip in an operation such as braking, the surface of the transistor is Often comes into contact with the pressing member, and the stress causes the air bridge wiring structure portion formed at an angle to be crushed or deformed.

As a result, the air bridge is crushed, and the upper wiring, for example, the drain electrode portion, and the lower wiring, for example, the source electrode portion, overlap with each other, resulting in a defect that RF characteristics are deteriorated. In addition, there is a problem that the RF characteristics of the transistor deteriorate due to the deformation of the air bridge wiring portion.

[0006]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to improve the above-mentioned drawbacks of the prior art and to improve the air bridge portion of a transistor having an air bridge wiring structure when polishing and braking the back surface of the transistor. By reducing the RF characteristics failure by preventing
An object of the present invention is to provide a semiconductor device capable of improving the yield and a method for manufacturing the same.

[0007]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, the first according to the present invention
Is a transistor including a gate electrode, a source electrode, and a drain electrode on an appropriate substrate, wherein at least one electrode of the electrode group crosses an upper part of another electrode via a space. In such a transistor, the top of at least a part of the substrate constituting the peripheral portion of the transistor has at least the same height as the maximum height of the electrode portion intersecting through the space. A semiconductor device in which a wall set at a height is arranged, and a second embodiment according to the present invention is a transistor including a gate electrode, a source electrode, and a drain electrode on an appropriate substrate. a is, when at least one electrode of the electrode group to upper portion of the other electrode forming a transistor that is configured so as to intersect through the space, the substrate Arrangement formed of at the transistor
A wall is formed on at least a part of the periphery of the part,
The height of the wall is formed in the area where the transistor is formed.
The maximum of the cross electrode part in the transistor
Forming at least the same height as the height,
Process for forming the transistor in the
During the transistor formation process,
In addition, part or all of the formation process of any of the above-described electrodes
The steps of laminating an appropriate film layer using the steps of
Semiconductor device to be executed before surface polishing and breaking process
It is a manufacturing method of .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device and the method of manufacturing the semiconductor device according to the present invention employ the above-described technical configuration, and therefore have a higher height than an air bridge wiring portion formed in a transistor. By arranging two or four wall portions on the outer periphery of the transistor, for example, the FET portion, the stress acting on the semiconductor device during the back surface polishing step or the breaking operation in the manufacturing process of the transistor is caused by the wall portion. Thus, the air bridge wiring portion can be prevented from being crushed.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a semiconductor device according to the present invention. That is, FIGS. 1 and 2 are cross-sectional views showing a configuration of a specific example of the semiconductor device according to the present invention. In the drawings, a gate electrode 2, a source electrode 3, and a drain electrode 4 Transistor 1 composed of
0, in the transistor 10 in which at least one electrode 8 of the electrode group intersects the upper part of the other electrode 6 via the space 13, the periphery of the transistor 10 is On at least a part of the substrate 1 to be constituted, a wall portion 16 whose top portion 14 is set to a height at least equal to the maximum height of the electrode portion 8 intersecting via the space portion 13 is arranged. The semiconductor device 10 is shown.

In the semiconductor device 10 according to the present invention, a part 6 of the source electrode 3 and a part 8 of the drain electrode 4 constitute an air bridge 30. I have. Further, in the semiconductor device 10 according to the present invention, the wall portion 16 has two opposing sides of a square forming the periphery of the transistor 10.
It is desirable to be arranged on the sides 17, 17 '.

In the present invention, the wall 16 formed on two sides 17 and 17 ′ opposed to each other with respect to the transistor 10 is formed by the plurality of transistors 10 in a later process. It is desirable that the wafer be formed in parallel with a dicing line used in a dicing step for separating and dividing the individual transistors from the wafers arranged and formed in a large number of matrixes.

In the semiconductor device 10 according to the present invention, as a more preferred specific example, the wall portion 16 is configured to surround the periphery of the transistor 10 in a rectangular shape. Further, in the present invention, the height of the wall portion 16 and the interval between the wall portions 16 are determined so that at least the space portion 13 is pressed by a pressing force acting on the transistor from the electrode forming portion side of the transistor 10. It is desirable that the conditions be set so that the electrode portions that intersect through each other are not completely crushed.

More specifically, for example, when an individual transistor is to be separated from the wafer, a groove having a predetermined depth in a predetermined direction is provided in advance, and then appropriate pressing means, cutting, The individual transistors 10 are cut and separated from the wafer while applying a desired stress to the separation grooves by using means, bending means, or the like.

That is, the present invention is characterized in that a semiconductor device having an air bridge wiring has at least two or more walls 16 having a top portion 14 higher than the air bridge wiring portion. In the present invention, as a result of adopting the above configuration, by arranging two to four wall portions 16 higher than the air bridge wiring portion outside the FET portion, stress acting on the semiconductor device at the time of back surface polishing and breaking is reduced. It can be absorbed at the bank and prevent the air bridge from crushing.

As a method of manufacturing the semiconductor device 10 having the above-described structure, for example, Japanese Patent Application Laid-Open No. 8-340063
It is also possible to use a method of manufacturing the wall portion 16 as disclosed in Japanese Patent Application Laid-Open No. H10-260, 1988. That is, an active layer is formed by a mesa, a source and a drain are formed by an ohmic metal, a gate metal is formed, a protective film is formed, a window is opened, electrode sputtering, Au plating, and electrode formation are performed.
In this case, the FET section and the wall section 16 shown in FIG.

As an example of a method for simultaneously forming the transistor section 10 and the wall section 16 on one substrate 1 according to the present invention, as shown in FIG. As shown in (B), the substrate 1 is subjected to mesa etching to form a desired recess 20. Next, as shown in FIG. 5C, an ohmic electrode 22 and a gate electrode 23 are formed by a lift-off method to form an FET.
As shown in FIG. 5, a protective film 24 is formed on the entire surface of the substrate 1, and then, as shown in FIG.

Thereafter, as shown in FIG. 5F, a wiring metal film 25 is formed on the entire surface of the substrate 1 by using a sputtering method, and subsequently, as shown in FIG. After the gold plating 26 is formed on the portion 28 to be formed and the portion 16 where the future wall portion is to be formed simultaneously or in a different process,
As shown in FIG. 5H, the wiring portion 28 and the wall portion 16 are formed at the same time by removing the unnecessary sputtered metal film 25 by performing ion milling using the gold plating portion 26 as a mask. Is done.

In the above method, the height of the wall portion 16 is not particularly limited. However, the height of the wall portion 16 is taken into consideration in consideration of the size of the pressing member abutting on the wiring portion of the air bridge 30. It is desirable to set the height and spacing so that the wiring portion of the air bridge 30 can maintain a desired height. Further, the formation of each electrode portion and the formation of the air bridge wiring structure in the transistor 10 according to the present invention can use the method disclosed in Japanese Patent Application Laid-Open No. Hei 5-21179.

As another specific example of the method of manufacturing the wall portion 16 according to the present invention, as shown in FIG. 6A, a substrate 1 is prepared, and as shown in FIG. Then, the substrate 1 is subjected to mesa etching to form a desired concave portion 20. Next, as shown in FIG. 6C, an ohmic electrode 22 and a pattern portion 221 constituting the wall portion 16 are formed, and a gate electrode 23 is formed by a lift-off method to form an FET. 6), a protective film 24 is formed on the entire surface of the substrate 1, and then, as shown in FIG. To form

Thereafter, as shown in FIG. 6 (F), a wiring metal film 25 is formed on the entire surface of the substrate 1 by using a sputtering method, and subsequently, as shown in FIG. After the gold plating 26 is formed on the portion 28 to be formed and the portion 16 where the future wall portion is to be formed simultaneously or in a different process,
As shown in FIG. 6H, by performing ion milling using the gold plated portion 26 as a mask to remove unnecessary sputtered metal film 25, the wiring portion 28 and the wall portion 16 are simultaneously formed. Is done.

That is, as a specific example of the method of manufacturing the semiconductor device according to the present invention, a transistor including a gate electrode, a source electrode, and a drain electrode on an appropriate substrate, When forming a transistor in which one electrode crosses an upper portion of another electrode via a space portion, at least a part of the periphery of the transistor formation portion on the substrate is a wall portion. Is formed above the surface of the transistor formation region as a base portion of the transistor, and then, on the base portion, by utilizing a part or all of the above-described electrode forming steps, an appropriate film layer is formed. Is a method of manufacturing a semiconductor device in which a semiconductor device is laminated.

[0022]

Since the semiconductor device and the method of manufacturing the semiconductor device according to the present invention employ the above-described technical configuration, the semiconductor device having the air bridge wiring 30 has a higher wall portion than the air bridge wiring portion. By providing at least two or more, it is possible to prevent collapse of the air bridge portion during back surface polishing and braking, and therefore, it is possible to reduce the RF characteristics failure due to the collapse of the air bridge portion and improve the yield. .

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a specific example of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a specific example of a semiconductor device according to the present invention.

FIG. 3 is a plan view showing a configuration of one specific example of a conventional semiconductor device.

FIG. 4 is a cross-sectional view showing a configuration of one specific example of a conventional semiconductor device.

FIG. 5 is a fragmentary cross-sectional view for explaining steps of a specific example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a fragmentary cross-sectional view for explaining steps of another specific example of the method for manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Gate electrode 3 ... Source electrode 4 ... Drain electrode 5 ... Gate finger part 6 ... Source electrode path 7 ... Source finger part 8 ... Drain finger part 10 ... Transistor 11, 12 ... Space part between gate fingers 13 ... Space part 14 ... Top part of wall part 16 ... Wall part 17, 17 '... Side of peripheral edge of transistor 20 ... Concave part 30 ... Air bridge

Continuation of front page (56) References JP-A-4-96339 (JP, A) JP-A-5-211179 (JP, A) JP-A-7-29919 (JP, A) JP-A-4-29330 (JP) , A) JP-A-7-29939 (JP, A) JP-A-55-121656 (JP, A) JP-A-7-29940 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 29/80 H01L 21/768 H01L 29/78

Claims (7)

(57) [Claims] 1. A transistor including a gate electrode, a source electrode, and a drain electrode on an appropriate substrate, wherein at least one electrode of the electrode group crosses an upper part of another electrode via a space. In such a transistor, the top of at least a part of the substrate constituting the peripheral portion of the transistor has at least the same height as the maximum height of the electrode portion intersecting through the space. A semiconductor device having a wall portion set at a height. 2. The semiconductor device according to claim 1, wherein a part of said source electrode and a part of said drain electrode form an air bridge. 3. The semiconductor device according to claim 1, wherein the wall portion is disposed on two sides facing each other in a square forming the periphery of the transistor. 4. The semiconductor device according to claim 3, wherein said wall portions formed on two sides facing each other with respect to said transistor are formed in parallel with a dicing line. 5. The semiconductor device according to claim 1, wherein the wall is configured to surround a periphery of the transistor in a rectangular shape. 6. The height of the wall and the distance between the walls are
By a pressing force acting on the transistor from the electrode forming portion side of the transistor, a condition is set such that at least an electrode portion crossing through the space portion is not completely crushed. The semiconductor device according to claim 1. 7. A transistor including a gate electrode, a source electrode, and a drain electrode on an appropriate substrate, wherein at least one electrode of the electrode group crosses an upper part of another electrode via a space. in forming the configured transistor as to, in the preparative on the substrate
At least part of the periphery of the transistor forming area is a wall
The height of the wall and the transistor
In the transistor formed in the arrangement formation region of
The height should be at least equal to the maximum height of the cross electrode.
In the transistor forming and forming section of the transistor.
Forming a transistor, during the transistor forming process
In this case, any one of the above-described electrodes is formed on the wall portion.
By using a part or all of the process,
Before the backside polishing and breaking step
A method for manufacturing a semiconductor device, comprising: