JP3209162B2 - Semiconductor integrated circuit and design method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and a method for designing the same, and more particularly, to a semiconductor integrated circuit having a clock tree circuit for reducing clock skew and a method for designing the same.

[0002]

2. Description of the Related Art Conventionally, in a synchronous circuit of a semiconductor integrated circuit, a plurality of flip-flops (hereinafter simply referred to as F / F) may be supplied with a clock from the same clock supply source. In this case, a clock tree circuit is used to eliminate clock skew generated due to variations in wiring length, wiring resistance, and the like.

In a semiconductor integrated circuit using the above-described clock tree circuit, the clock tree circuit is generally constituted by several stages of inverters or buffers. Then, the automatic arrangement and wiring program arranges the inverters and performs wiring between the inverters so that the delay value difference from the input to the output of each inverter at the final stage, that is, the clock skew is minimized. Usually, the same type of blocks are used for the inverters in each stage, and the number of stages depends on the scale of the synchronous circuit in the semiconductor integrated circuit to be driven.

Therefore, in the above-described semiconductor integrated circuit having the conventional clock tree circuit, even if a plurality of F / Fs are supplied with the clock from the same clock supply source, the wiring length, the wiring resistance, etc. It is stated that clock skew generated due to variations can be effectively reduced.

[0005]

However, in the above-described conventional semiconductor integrated circuit, since the clock tree circuit is provided, the skew of each clock output from the clock input is minimized. Therefore, at the time of clock switching, a large number of inverters in each stage, particularly the last stage, may operate at the same time. In this case, when switching is performed by the clock, a large current flows in a short time, and as a result, the same chip is used. Other circuits in the device may malfunction, and for the outside of the chip,
Eleatro-Magnetic Inference (hereinafter referred to as EMI)
Is generated.

The present invention has been made in view of the above circumstances,
To provide a semiconductor integrated circuit capable of reducing the influence of simultaneous switching of a clock tree at the time of clock switching and improving circuit reliability without deteriorating the performance of a synchronous circuit of the semiconductor integrated circuit, and a method of designing the same. With the goal.

[0007]

According to the first aspect of the present invention,
In order to reduce clock skew, at least one or more clock branching units forming a clock tree that branch a clock supplied from a clock supply source, and at least two or more registers to each of which a clock is supplied from the clock branching unit And at least one or more random logic for transmitting and receiving data to and from the register, and a delay within a range that is provided between a clock branch unit that supplies a clock to the register and guarantees hold in the register, entered given to the clock and at least one or more delay elements to output, the black
The clock branch unit stores the time in the at least two or more registers.
The clock is supplied with a difference .

Therefore, according to the present invention, in order to reduce clock skew, a delay element for providing a delay within a range in which holding in a register is guaranteed is provided between clock branching units constituting a clock tree. Therefore, it is possible to prevent a large current from flowing due to the simultaneous operation of each register due to the clock delay, and the delay by the delay element is a delay within a range that guarantees the hold of the register. Malfunction of the circuit can be prevented.

According to a second aspect of the present invention, in the first aspect, the clock branching unit is an inverter or a buffer.

Therefore, according to the present invention, the operation of the invention described in claim 1 can be obtained, and the clock skew in the clock tree can be adjusted more accurately because the clock branching unit is an inverter or a buffer. Can be performed.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the delay within the range that guarantees hold in the register by the delay element is a connection between the random logic and the register. Information and a minimum path delay value of the random logic obtained by the path delay analysis of the random logic.

Therefore, according to the present invention, the operation of the invention described in claim 1 or 2 can be obtained, and the delay by the delay element within the range for guaranteeing the hold in the register is between the random logic and the register. Connection information,
Since it is given by obtaining the minimum path delay value of the random logic obtained by the path delay analysis of the random logic, it is possible to more appropriately guarantee the hold in the register.

According to a fourth aspect of the present invention, in the first or second aspect of the present invention, the delay within the range that guarantees hold in the register by the delay element focuses on the delay element that determines the value of the delay. A clock element is provided as a delay element, and the clock branch sections connected across the delay element of interest are respectively a first clock branch section and a second clock branch section, and a clock is supplied by the first clock branch section. The register to be supplied is a first register, the register to which a clock is supplied by the second clock branching unit is a second register, and data transfer between the first register and the second register is performed. The random logic to be exchanged is a first random logic, a delay value of the first clock branching unit is ΔB1, and the second clock branching is If the delay value of ΔB2 is set, the path delay analysis of the first random logic is performed, the minimum path delay value obtained as a result of the path delay analysis is set as ΔC2, and the delay value of the delay element of interest is set as ΔA1. ΔB1
+ ΔC1> ΔA1 + ΔB2.

Therefore, according to the present invention, the operation of the invention described in claim 1 or 2 can be obtained, and the delay in the first clock branching section is ΔB1, and the delay in the second clock branching section is ΔB2. When the minimum path delay value in the first random logic is ΔC1 and the delay value of the delay element of interest for determining the delay value is ΔA1, ΔA1 is determined so as to satisfy ΔB1 + ΔC1> ΔA1 + ΔB2. The first register and the second
Can more reliably execute the hold, and the switching in each register is executed by the delayed clock, so that the inflow of a large current due to the simultaneous ON can be more effectively prevented. .

According to a fifth aspect of the present invention, in the first aspect of the present invention, the register includes at least one flip-flop.

Therefore, according to the present invention, the operation of the invention according to any one of claims 1 to 4 can be obtained, and the register is constituted by at least one flip-flop, so that it is synchronized with the clock. Thus, the register can reliably latch the data.

According to a sixth aspect of the present invention, in order to reduce clock skew, at least one or more clock branching units forming a clock tree for branching a clock supplied from a clock supply source are arranged. A step of arranging at least two or more registers to which a clock is supplied from the clock branching unit, the register being arranged in the clock branching unit arranging step, and the register being arranged in the register arranging step. Between a random logic arranging step of arranging at least one or more random logics for exchanging data between the two, and a clock branching unit for supplying a clock to the register, a delay within a range that guarantees hold in the register, Given to the clock and output at least And a delay element arrangement step of arranging a further delay element, by the clock branch portion placement step
The arranged clock branching unit includes the at least two or more clock branching units.
The clock is supplied with a time difference between the registers .

Therefore, according to the present invention, at least one delay element is provided between clock branching units, the delay element being provided with a delay within a range that guarantees hold in a register to an input clock and output. Since the arrangement step is provided, it is possible to prevent a large current from flowing due to simultaneous switching and to prevent a malfunction of the semiconductor integrated circuit.

According to a seventh aspect of the present invention, in the sixth aspect, the clock branching unit is an inverter or a buffer.

Therefore, according to the present invention, the operation of the invention described in claim 6 can be obtained, and the clock skew in the clock tree can be adjusted more accurately because the clock branching unit is an inverter or a buffer. Can be performed.

According to an eighth aspect of the present invention, in the invention of the sixth or seventh aspect, there is provided a connection information calculating step of calculating connection information between the random logic and the register, and a path delay analysis of the random logic. A minimum path delay value calculating step of calculating a minimum path delay value of random logic given based on the connection information and the minimum path by the delay element within a range that guarantees hold in the register. It is characterized by being given by a delay value.

Therefore, according to the present invention, the operation of the invention described in claim 6 or 7 can be obtained, and the delay by the delay element within the range for guaranteeing the hold in the register is between the random logic and the register. The connection information calculating step of calculating the connection information of the random logic and the minimum path delay value calculating step of calculating the minimum path delay value of the random logic given based on the path delay analysis of the random logic, so that the delay is more appropriately The delay in the element can be set.

According to a ninth aspect of the present invention, in the invention according to the sixth or seventh aspect, the delay element for determining the value of the delay is a delay element of interest, and the clock branching unit sandwiching the delay element of interest is A first clock branch unit and a second clock branch unit, respectively, the register to which a clock is supplied by the first clock branch unit is a first register, and a clock is supplied by the second clock branch unit. A connection information recognizing step of recognizing, as a first random logic, the first register, and the first register, and the random logic for transmitting and receiving data between the second register and the first register. Calculating a delay value of the first clock branching unit, setting the calculated value to ΔB1, and calculating a delay value of the first clock branching unit; A second clock branching unit delay value calculating step of calculating the delay value of the clock branching unit and setting the calculated value to ΔB2; and performing a path delay analysis of the first random logic. A minimum path delay value calculating step of setting a minimum path delay value obtained as a result to ΔC2, wherein a delay within a range that guarantees hold in the register by the delay element is set to ΔA1 in the delay element of interest. Where ΔB1 + ΔC1> ΔA1 + ΔB
2 is a value that satisfies 2.

Therefore, according to the present invention, the operation of the invention described in claim 6 or 7 is obtained, and in the connection information recognition step, the delay element for determining the delay value is recognized as the delay element of interest. Recognizing a first clock branch and a second clock branch, recognizing a first register and a second register, recognizing a first random logic,
Let the delay in the first clock branching unit be ΔB1,
Is calculated as ΔB2, the minimum path delay value in the first random logic is calculated as ΔC1, and the delay value of the delay element of interest for determining the delay value is ΔA.
In the case of 1, ΔB1 + ΔC1> ΔA1 + ΔB
Since ΔA1 is determined so as to satisfy 2, the first register and the second register can more reliably execute the hold, and the switching in each register is executed by the delayed clock. Therefore, it is possible to more effectively prevent the inflow of a large current due to the simultaneous turning on.

The invention according to claim 10 is the invention according to claims 6 to 9
In the invention described in any one of the above, the register is constituted by at least one or more flip-flops.

Therefore, according to the present invention, the operation of the invention described in any one of claims 6 to 9 can be obtained, and since the register is constituted by at least one or more flip-flops, Synchronously, the register can reliably latch data.

Hereinafter, the means for solving the problems will be described in more detail. In the semiconductor integrated circuit and the method of designing the same according to the present invention, a basic circuit having the following properties is used. 1. The flip-flops that make up the registers in one pipeline are driven by one clock branch of the clock tree. 2. A delay element is inserted between each clock branch of the clock tree.

The following algorithm is used to determine the delay time of the delay element. 1. The random logic and the upper level circuit information (RTL) constituted by the register are analyzed, and the register and the random logic therebetween are separated and recognized. 2. The path delay analysis of each random logic is performed, and the minimum path delay value is obtained. 3. A constraint expression (hold guarantee) is created for the delay inserted from the upper level circuit information, and a solution is obtained. 4. Based on the obtained delay value, a delay element having the delay is actually inserted.

Next, the operation of the present invention will be described in more detail. First, since a delay element is inserted in each clock branch of the clock tree of the synchronous circuit included in the semiconductor integrated circuit, it is possible to avoid simultaneous switching of all blocks (inverters) in the clock tree.

Further, the delay due to the inserted delay element has a value that can guarantee the timing constraint (hold guarantee) of the register in the circuit. Therefore, even if the delay is inserted, the synchronous circuit included in the semiconductor integrated circuit does not malfunction.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of a semiconductor integrated circuit and a method for designing the same according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronous circuit provided in a semiconductor integrated circuit according to the present invention. FIG.
As shown in FIG. 2, the synchronous circuit includes an external clock terminal E for outputting a clock, a clock buffer B0 that receives a clock output from the external clock terminal E and serves as a first-stage clock branching unit, Buffer B0
Clock buffers B1, B2, and B3, which serve as a second-stage clock branching unit that receives the clocks branched by and outputs clocks to the registers connected to the clocks,
A register D1 for inputting a clock output from the clock buffer B1, a register D2 for inputting a clock output from the clock buffer B2, and a register D3 for inputting a clock output from the clock buffer B3
A random logic C1 for transmitting and receiving data between the register D1 and the register D2, a random logic C2 for transmitting and receiving data between the register D2 and the register D3, and a data between the register D1 and the register D3. A random logic C3 for giving and receiving
It comprises a delay element A1 disposed between the clock buffer B1 and the clock buffer B2, and a delay element A2 disposed between the clock buffer B2 and the clock buffer B3.

Next, the operation of the synchronous circuit provided in the semiconductor integrated circuit shown in FIG. 1 will be described. At least one
The registers D1, D2, and D3 configured by the F / F are clocked by the external clock output from the external clock terminal E.

The random logics C1, C2 and C3 are random logics located between the registers.

The clock is output from the external clock terminal E, passes through the delay element A1 or the delay element A2, and finally the clock buffers B1, B2, and B3 drive the clock terminals of the registers D1, D2, and D3, respectively.

The delay values of the delay elements A1 and A2 are determined by the following algorithm based on the delay values of the random logics C1, C2 and C3.
This algorithm will be described next.

The algorithm of the present invention will be described with respect to the circuit example described in the description of the configuration. 1. From the circuit description, analyze the high-level circuit information,
Registers D1, D2 and D3 are set to random logic C
After cutting into 1, C2, and C3, each is recognized. 2. A path delay analysis of the random logic C1, C2, and C3 is performed, and each of the minimum path delay values is expressed as {C1,
ΔC2, ΔC3. Further, clock buffer B
The delay values of 1, B2, and B3 are obtained, and the respective delay values are set as △ B1, △ B2, and △ B3. 3. From the values of △ C1, △ C2, △ C3, △ B1, △ B2, and △ B3 obtained by the constraint expression that assures the hold time of each register in 2, and the connection information between the register and the random logic obtained in 1 create. More specifically, the delay values of the inserted delay elements A1 and A2 are respectively set to △ A1, △ A2
Then, the constraint expression is as follows. ΔB1 + ΔC1> ΔA1 + ΔB2 for register D1, D2 (1) ΔB2 + ΔC2> ΔA2 + ΔB3 for register D2, D3 (2) ΔB1 + for register D1, D3 ΔC3> ΔA2 + ΔB3 (3) 4. By solving this constraint equation, the values of △ A1 and △ A2 are obtained.
A delay element having this value is configured and inserted into the circuit.

The delay values A1 and A2 determined by the above constraints (1), (2) and (3) fall within a range that guarantees the hold of the register. Therefore, according to the above embodiment, even when the clock skew is reduced to zero as much as possible in the clock tree, the clock is delayed and input by the delay element A1 and the delay element A2. And inflow of a large current due to simultaneous operation can be prevented.

Here, the configuration of the semiconductor integrated circuit shown in FIG. 1 is a preferred example when the semiconductor integrated circuit and the design method thereof according to the present invention are applied, but the present invention is as shown in FIG. The present invention is not limited to the semiconductor integrated circuit, and the number of registers, the number of random logics, the number of clock tree stages, that is, the number of clock buffers, and the like can be arbitrarily changed.

[0040]

As is apparent from the above description, according to the present invention, the clock tree is divided into several branches, a delay element is inserted in each branch, and each branch has its delay difference. A semiconductor integrated circuit capable of preventing a large current from flowing into a circuit constituting a clock tree without switching at the same time, and reducing the influence of switching noise and EMI on and off a chip. And a method for designing the same.

Further, since the delay between the branched clocks is determined so as to satisfy the constraint equation of the hold guarantee obtained from the upper level information of the circuit and the path analysis information of the random logic, the delay inserted by the synchronous circuit is determined. Therefore, it is possible to provide a semiconductor integrated circuit capable of appropriately preventing the inflow of a large current without causing a malfunction and a design method thereof.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

 A1, A2 Delay element B0, B1, B2, B3 Clock buffer C1, C2, C3 Random logic D1, D2, D3 Register (flip-flop group) E External clock terminal

Claims (10)

(57) [Claims] At least one or more clock branching units that form a clock tree for branching a clock supplied from a clock supply source to reduce clock skew, and a clock is supplied from the clock branching unit. At least two or more registers; at least one or more random logics for exchanging data with the registers; and a range provided between a clock branch unit for supplying a clock to the registers and guaranteeing hold in the registers And at least one or more delay elements for giving the delay in the clock to the input clock and outputting the clock.
A semiconductor integrated circuit that supplies the clock with a time difference between the clocks . 2. The semiconductor integrated circuit according to claim 1, wherein said clock branching unit is an inverter or a buffer. 3. A delay within a range that guarantees hold in the register by the delay element, the connection information between the random logic and the register, and a random logic of a random logic obtained by a path delay analysis of the random logic. 3. The semiconductor integrated circuit according to claim 1, wherein the value is obtained by obtaining a minimum path delay value. 4. A delay within a range that guarantees hold in the register by the delay element, wherein a delay element that determines a value of the delay is set as a target delay element, and the clock connected across the target delay element. A first clock branching unit and a second clock branching unit; a register supplied with a clock by the first clock branching unit as a first register; and a second clock branching unit. A register supplied with a clock by a unit as a second register; the first register, and the random logic for transmitting and receiving data between the second register as a first random logic; The delay value of the clock branch unit is ΔB1, the delay value of the second clock branch unit is ΔB2, and the delay value of the first random logic is When a minimum path delay value obtained as a result of the path delay analysis is set to ΔC2 and a delay value of the delay element of interest is set to ΔA1, the value satisfies ΔB1 + ΔC1> ΔA1 + ΔB2. The semiconductor integrated circuit according to claim 1. 5. The semiconductor integrated circuit according to claim 1, wherein said register is constituted by at least one flip-flop. 6. A clock branch section arranging step of arranging at least one or more clock branch sections constituting a clock tree for branching a clock supplied from a clock supply source in order to reduce clock skew; A register arranging step of arranging at least two or more registers to each of which a clock is supplied from a clock branching unit arranged in the unit arranging step; and transmitting and receiving data to and from the registers arranged in the register arranging step. A random logic arranging step of arranging at least one or more random logics to be performed, and a clock branching unit for supplying a clock to the register, wherein a delay within a range that guarantees hold in the register is given to the input clock. Output at least one delay element And a delay element arranging step, wherein the clock is arranged by the clock branching section arranging step.
The branching unit adds a time difference to the at least two or more registers.
And supplying the clock to the semiconductor integrated circuit. 7. The method of designing a semiconductor integrated circuit according to claim 6, wherein said clock branching unit is an inverter or a buffer. 8. A connection information calculating step of calculating connection information between the random logic and a register, and a minimum path delay calculating a minimum path delay value of the random logic given based on a path delay analysis of the random logic. The method according to claim 6, further comprising a value calculating step, wherein a delay within a range that guarantees hold in the register by the delay element is given by the connection information and the minimum path delay value. Semiconductor integrated circuit design method. 9. A delay element that determines the value of the delay is a delay element of interest, and the clock branch sections sandwiching the delay element of interest are a first clock branch section and a second clock branch section, respectively. Wherein the register supplied with a clock by the first clock branching unit is a first register, the register supplied by a clock by the second clock branching unit is a second register,
And a connection information recognizing step of recognizing, as first random logic, the random logic that exchanges data between the second register and the second register; and calculating a delay value of the first clock branching unit. A first clock branching unit delay value calculating step of setting the calculated value to ΔB1, a second clock branching unit delay calculating the delay value of the second clock branching unit and setting the calculated value to ΔB2 A value calculation step, and a minimum path delay value calculation step of performing a path delay analysis of the first random logic and setting a minimum path delay value obtained as a result of the path delay analysis to ΔC2. The delay within the range that guarantees hold in the register is a value that satisfies ΔB1 + ΔC1> ΔA1 + ΔB2 when the delay value of the delay element of interest is ΔA1. Method for designing a semiconductor integrated circuit according to claim 6 or 7, characterized in. 10. The method of designing a semiconductor integrated circuit according to claim 6, wherein said register is constituted by at least one or more flip-flops.