JP3063614B2 - Semiconductor integrated circuit and test method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a test method therefor, and more particularly, to a semiconductor integrated circuit having a clock distribution circuit formed by a clock signal line network branched in a branch including a CMOS inverter circuit and configured as a synchronous MOSFET. And a test method thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit formed as a synchronous MOSFET integrated circuit of this kind, the entire semiconductor integrated circuit operates in synchronization with one clock signal or a plurality of clock signals having different phases. May be caused. In such a case, by distributing the basic clock signal supplied from the outside to the terminal synchronization circuit such as the flip-flop of each unit in the semiconductor integrated circuit,
When operations such as various operations are performed, if the wiring length from the source to the destination of the clock signal is different, the arrival timing of each clock signal is shifted (clock skew).
Occurs. If the clock skew exists, an erroneous signal may be captured in an end synchronization circuit such as a flip-flop, or an undesired whisker pulse may be generated in an output of a logic gate, causing a malfunction in the circuit. .

A conventional technique for minimizing such clock skew is disclosed in, for example, Japanese Patent Application Laid-Open No. H5-1590.
As disclosed in Japanese Patent Publication No. 80 and a logic integrated circuit (author: Kazuo Koide), it is known as an effective technique applied to a clock signal supply system. FIG. 5 is a block diagram showing a conventional semiconductor chip disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-159080. As shown in FIG. 5, the semiconductor chip IC ₃ of this conventional example is composed of four blocks IC _3a , IC _3b , IC _3c and IC _3d, of which the block IC _3a is a semiconductor chip IC.
₍₃₎ A clock input terminal (pad: hereinafter, pad is referred to as a terminal) PD ₃₁ commonly used for inputting a clock signal CK ₀ supplied to the whole, and also used for inputting a reference clock signal CKR _0. that a clock input terminal PD _32, an input terminal, respectively, the buffer circuits BF ₃₁ and BF ₃₂ are connected to these clock input terminal
When connected to an output terminal of the buffer circuit BF _32, and a buffer circuit BF ₃₃ arranged at the center portion of the semiconductor chip IC _3, comprising a common buffer circuit for the entire semiconductor chip IC _3, the clock phase adjustment circuit PC ₃₁ And a buffer circuit BF ₃₄ connected to the output terminal of the clock phase adjustment circuit PC ₃₁ , seven terminal circuits SY ₃₁ to which a clock signal is supplied, and a cascade connection to the buffer circuit BF _34. constructed and a four buffer circuits BF ₃₅ which functions as a clock signal input to the circuit SY _31. It should be noted that the other blocks IC _3b , IC _3c and IC _3d other than the block IC _3a do not include any of the common components relating to the entire semiconductor chip IC ₃ described above, and the other internal components are This is exactly the same as the internal components in the block IC _3a . That is, the block IC _3b includes the clock phase adjustment circuit PC
₃₂ , a buffer circuit BF ₃₆ , and seven terminal circuits SY
₃₂ and four buffer circuits BF ₃₇ ,
Block IC _3c includes a clock phase adjustment circuit PC _33, a buffer circuit BF _38, the seven-terminal circuit SY _33, is constituted by a four buffer circuits BF _39, the block IC _3d, clock a phase adjustment circuit PC _34, a buffer circuit BF _40, the seven-terminal circuit SY _34, is constituted by a four buffer circuits BF _41.

[0004] In FIG. 5, the reference clock signal CKR ₀ frequency is lower than the clock signal CK ₀ is input through the clock input terminal PD _32, once the buffer circuit B
It is transmitted from F ₃₂ to the buffer circuit BF ₃₃ provided in the center portion of the semiconductor chip IC _3, further from there, as described above, each block IC _3a, IC _3b, provided inside the IC _3c and IC _3d Clock phase adjustment circuit PC ₃₁ , P
It is input to C ₃₂ , PC ₃₃ and PC ₃₄ . In this case, the wiring from the buffer circuit BF ₃₃ to the clock phase adjustment circuit of each block is laid with the respective wiring lengths set to be equal, and each of the clock phase adjustment circuits PC ₃₁ , PC _32, PC ₃₃ and the reference clock signal _CKR 1 inputted to PC _34, CKR _2, CKR
₃ and CKR ₄ are in the same phase. In addition, each clock phase adjustment circuit PC ₃₁ , PC ₃₂ , P
For C ₃₃ and PC ₃₄ , a clock input terminal PD ₃₁
The clock signal CK ₀ inputted through, is supplied to the common via the buffer circuit _31, these clock phase adjustment circuit PC _31, PC _32, a clock signal output from the PC ₃₃ and PC ₃₄ are , Block IC _3a , buffer circuit BF ₃₄ and four buffer circuits BF
Through _35, it is distributed to the terminal circuit SY ₃₁ such four flip flops, respectively. Note that the load capacitances (such as the wiring capacitance and the input capacitance of the next-stage gate) of the buffer circuits in each of these stages correspond to each other, so that the wiring length between the buffer circuits and between the final buffer circuit and the terminal circuit, The number of fan-outs of the buffer circuit is determined.

Further, clock phase adjusting circuits PC ₃₁ , PC ₃₂ , PC ₃₃ and PC ₃₄ included in each block are further provided.
Are each provided with a phase comparison circuit, a control circuit, and a delay adjustment circuit (not shown). In the phase comparison circuit, in each block, the terminal circuits SY ₃₁ , SY ₃₂ , SY _33, and SY ₃₄ are respectively provided. Supplied clock signals CKD ₁ , CKD ₂ , CKD ₃ and CK
D ₄ and respective clock phase adjustment circuits PC ₃₁ , PC
₃₂ , a phase difference between the reference clock signals CKR ₁ , CKR ₂ , CKR ₃ and CKR ₄ input to the PCs ₃₃ and ₃₄ is detected, and a signal corresponding to the phase difference is output to the delay adjustment circuit. Is entered. The terminal circuit SY is controlled by the control circuit so that the phase difference becomes zero.
The phases of the clock signals CKD ₁ , CKD ₂ , CKD ₃ and CKD ₄ supplied to ₃₁ , SY ₃₂ , SY ₃₃ and SY ₃₄ are delayed and adjusted. That is, the clock signals CK ₁ , CK ₂ , and CK ₃ input to the clock phase adjusting circuits PC ₃₁ , PC ₃₂ , PC ₃₃ and PC ₃₄ via the buffer circuit BF ₃₁ .
The delay amounts for CK ₃ and CK ₄ are controlled and adjusted.
Thereby, the clock phase adjustment circuits PC ₃₁ , PC ₃₂ , PC _{33 of the} blocks IC _3a , IC _3b , IC _3c and IC _3d are provided.
And the clock signals CK ₁ and C input to the PC ₃₄
Even if there is a phase shift between K ₂ , CK ₃ and CK ₄ , each clock signal CKD ₁ , CKD supplied to the terminal circuits SY ₃₁ , Y ₃₂ , Y ₃₃ and Y ₃₄ in each block.
₂ , the phases of CKD ₃ and CKD ₄ are adjusted so as to match each other in the entire semiconductor chip IC ₃ .

[0006]

The above conventional synchronous M
In a semiconductor integrated circuit formed as an OSFET integrated circuit, in a design method thereof, a clock distribution system that minimizes a clock skew can be realized based on the phase adjustment circuits PC ₃₁ , PC ₃₂ , PC _33, and PC _33. Reference clock signals CKR ₁ and CK applied to ₃₄
It is an absolute condition that R ₂ , CKR ₃ and CKR ₄ have the same phase as each other. That is, the reference clock signal CKR ₀ inputted to the clock input terminal PD _32, the buffer circuit BF ₃₃ provided from the buffer circuit BF ₃₂ in the central portion of the semiconductor chip IC ₃
To each block IC _3a , IC _3b , IC
Clock phase adjustment is provided in _3c and the IC _3d circuit PC _31, PC _32, up to the PC ₃₃ and PC _34, to be supplied via the same wiring each length and fundamental requirements Become.

However, in recent years, semiconductor integrated circuits formed as synchronous MOSFET integrated circuits have been remarkably increasing in scale and integration, and are not suitable for synchronizing a flip-flop or the like located at an end from an input terminal of a synchronization clock signal. The clock signal distribution circuit until reaching the terminal circuit including the circuit tends to become more and more complicated. That is, the number of branches in the clock signal distribution circuit reaches up to two digits, and the number of insertion stages of buffer circuits provided for each branch stage is steadily increasing. Therefore, from the reference clock input terminal PD _32, up to the clock phase adjustment circuit PC _31, PC _32, PC ₃₃ and PC _34,
The number of stages in which the reference clock signal CKR ₀ is branched in a branch,
In addition, the number of stages of buffer circuits inserted at least at each branch point is also increasing, and each of the reference clock signals CKR ₁ , CKR ₂ , CKR ₃ and CKR ₄ which is an absolute condition in the above-mentioned conventional design method is required. It is extremely difficult to make the phases identical between them. In addition, supply fluctuations due to fluctuations in transistor element performance due to manufacturing fluctuations, fluctuations in wiring capacitance and resistance, fluctuations in MOSFET gate electrode or drain electrode capacitance, or fluctuations in operating environment conditions, etc. When various fluctuation factors such as a voltage fluctuation of a power supply and a temperature fluctuation of an operating atmosphere are added, there is a disadvantage that the possibility of realizing the above-described design method is further reduced.

An object of the present invention is to provide a semiconductor integrated circuit formed as a synchronous MOSFET on the premise that there is a limit in designing a clock distribution system that minimizes clock skew. It is an object of the present invention to provide a semiconductor integrated circuit capable of preliminarily selecting a semiconductor chip having a high risk of causing a malfunction in operation by a chip test, and a test method thereof.

[0009]

The semiconductor integrated circuit of the means for solving the problems] The first invention includes a predetermined clock input terminal, distribution to clock distribution supplied to the plurality of terminal circuits a clock signal input from the clock input terminal Synchronous M with circuit
In the semiconductor integrated circuit formed by OSFET integrated circuit, the clock distribution circuit, the inputted clock <br/> click signal via a plurality of branch points of the plurality of terminals circuits
A clock signal line network laid out so as to be sequentially branched in a branch shape for distribution to each of the plurality of branch points ;
Enhancement type P-channel with voltage supply terminal
MOSFET and enhancement type N-channel MOSF
ET and a plurality of CMOS inverter circuits and test
Sometimes controlled in response to a control signal supplied from the outside pair
Normal operation with the corresponding back gate voltage
Sometimes, the enhancement method is performed in response to the non-supply of the control signal.
-Type P-channel MOSFET and enhancement-type N
The same voltage as the source voltage of each channel MOSFET
Generating a Kugeto voltage, before Symbol C MOS inverter circuit
And a plurality of bus <br/> Kkugeto voltage generating circuit supplies the back gate voltage to each of said plurality of branch points
The CMOS connected to each wiring after branching at the final branch point
It is characterized by supplying the clock signal to be output from the inverter circuit to the terminal circuit.

[0010] Incidentally, the CMOS inverter circuit, the CMOS inverter circuit, before comprises Kiba Kkugeto voltage supply terminal is connected to the branch point corresponding to the gate,
And a source connected to the high-potential power supply, and the enhancement-type P-channel MOSFET having a drain connected to the clock signal output line, before with Kiba Kkugeto voltage supply terminal, the gate enhancement type P-channel MOS
The commonly connected to the branch point with FET, the drain with the previous <br/> Symbol enhancement P-channel MOSFET are commonly connected to the clock signal output line, the enhancement N-channel MO having a source connected to the low potential power supply
And an SFET.

Further, the back gate voltage is supplied to each of the first CMOS inverter circuits, which are a pair of the CMOS inverter circuits, connected to each wiring after the first branch point of the plurality of branch points. Two first back gate voltage generating circuits respectively control the P-channel MOSFET and the N-channel MOSFET in response to control of the control signal from outside.
In addition to generating the back gate voltage of each of the channel MOSFETs, when the control signal is not supplied, the same back gate voltage as the source voltage of each of the enhancement type P channel MOSFET and the enhancement type N channel MOSFET is generated. Each pair of CMOS inverters connected to each wiring after the branch point
A pair of second CMOs comprising any one of the roads
A pair of third Cs consisting of an S inverter circuit and the other
A second and a third back gate voltage generating circuit for supplying the back gate voltage to the MOS inverter circuit respectively correspond to the control of the control signal from the outside, and the pair of the second or third A common back gate voltage for each of the P-channel MOSFETs of the CMOS inverter circuit, and when there is no supply of the control signal, the enhancement type P-channel MOSF
A back-gate voltage generation circuit for a P-channel MOSFET for generating the same back-gate voltage as the source voltage of the ET; and the pair of second or third CMOS inverters respectively corresponding to the control value of the control signal from outside A common back gate voltage for each of the N-channel MOSFETs of the circuit is generated, and when there is no supply of the control signal, the enhancement-type N-channel MOSFET is used.
And a back-gate voltage generation circuit for N-channel MOSFET that generates the same back-gate voltage as the source voltage.

According to a second aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit, comprising a predetermined clock input terminal, wherein a plurality of back gate voltage generating circuits are used to back clock a clock signal input from the clock input terminal. Synchronous MO having a clock distribution circuit for supplying a plurality of terminal circuits via a CMSO inverter circuit supplied with a voltage
A method of testing a semiconductor integrated circuit formed by an SFET integrated circuit, wherein a first step of selecting a plurality of back gate voltage generation circuits by an arbitrary combination from the plurality of back gate voltage generation circuits; in response to a control signal from the external that correspond to a plurality of back-gate voltage generator circuit selected in the step of, the back gate voltage generation circuit from the second outputs respectively to generate any back gate voltage A third step of executing a predetermined operation test on a semiconductor integrated circuit formed by the synchronous MOSFET integrated circuit by inputting a synchronization clock signal to the clock input terminal; A plurality of back gate voltage generation circuits selected by another arbitrary combination from among the back gate voltage generation circuits And is characterized in that it has a fourth step of performing repeatedly the second and third step, at least.

[0013]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram on a semiconductor chip according to one embodiment of the present invention. As shown in FIG. 1, the semiconductor chip of this embodiment has a power supply terminal VD and a ground terminal G.
D, data input / output terminal PD ₁₁ , clock input terminal P
D _12, corresponding to the control terminal PD ₁₃ ~PD _18, a data input-output Intafeisu buffer IF _11, a Intafeisu buffer circuit IF _12, CMOS inverter circuit including a Enhasumento type P-channel MOSFET and an enhancement-type N-channel MOFET BF _{11 to} BF
₁₇ and buffer gate voltage generation circuits VB _{1 to} VB 6 When,
Configured with a synchronization circuit SY ₁₁ to SY ₁₄ disposed at the ends. In Figure 1, a clock signal for synchronization input to the clock input terminal PD ₁₂ is input to the semiconductor chip through the input interface buffer IF _12, are bifurcated through the CMOS inverter circuit BF ₁₁ , it is input to the CMOS inverter circuit BF ₁₂ and BF _13, respectively. For these CMOS inverter circuits BF ₁₂ and BF _13, is supplied with the back gate voltage to the back gate voltage generating circuit VB ₁ and VB ₂ corresponding, also, VB ₁ and these back-gate voltage generator circuit VB ₂ is connected to the control terminal PD ₁₃
And PD ₁₄ are independently controlled.

[0014] The clock signal output is inverted via a CMOS inverter circuit BF ₁₂ is branched into two similarly, is input to the CMOS inverter circuits BF ₁₄ and BF _15, respectively. Also, a CMOS inverter circuit B
Clock signal output is inverted via the F ₁₃ also 2
The signals are branched and input to the CMOS inverter circuits BF ₁₆ and BF ₁₇ , respectively. CMOS inverter circuit BF
_The enhancement-type P-channel MOSFETs included in ₁₄ and BF ₁₆ are controlled by receiving a back-gate voltage output from a back-gate voltage generation circuit VB ₅ controlled via a control terminal PD _17, and are controlled by a CMOS inverter. enhancement P-channel MOSFET included in the circuit BF ₁₅ and BF ₁₇ is controlled by receiving the input of the back gate voltage output from the back gate voltage generating circuit VB ₆ which is controlled through a control terminal PD _18. Further, the CMOS inverter circuits BF ₁₄ and BF
Enhancement type N-channel MOSFE included in ₁₆
T, the back gate voltage generating circuit is controlled via a control terminal PD ₁₅ VB3 The N-channel MOSFET is controlled by receiving a back gate voltage output from the CMOS inverter circuits BF ₁₅ and BF ₁₇ , and is controlled via a control terminal PD _16. It is controlled by receiving the input of the back gate voltage output from the VB _4.

Finally, the clock signals output via the CMOS inverter circuits BF ₁₄ , BF ₁₅ , BF ₁₆ and BF ₁₇ are respectively converted to the corresponding terminal synchronizing circuits SY ₁₁ , SY ₁₂ , SY ₁₃ and it is supplied to the SY _14,
It is used as a clock signal for synchronizing the entire semiconductor chip. Here, the synchronization circuit SY ₁₁ at the end,
SY _12, SY _13, and SY _14, the data input-output terminal PD
₁₁ and data input / output interface buffer IF
_A desired logical operation is realized as a whole of the semiconductor chip while exchanging data synchronized with each other through a data signal line together with a data signal input through the data signal line _11. I / O interface buffer IF ₁₁ and data I / O terminal PD
Output to the outside via ₁₁ .

Next, FIG. 2 shows a synchronous type MO shown in FIG.
FIG. 3 is a block diagram illustrating a floor layout of a semiconductor chip corresponding to the semiconductor integrated circuit formed as an SFET. As shown in FIG.
C ₁ is composed of five blocks IC _1a , IC _1b , IC _1c and IC _1d
And IC _1e.
A clock input terminal (pad: hereinafter referred to as a terminal) PD ₁₂ for inputting / outputting an external signal mainly to C _1e ,
Control terminals PD _{13 to} PD ₁₈ , high-potential power supply terminal VD, low-potential power supply terminal GD, and interface buffer circuit I
Such as F ₁₂ is disposed, another block IC _1a, IC
_1b, the IC _1c and IC _1d, mainly disposed circuit for performing a logical operation operation, particularly, the block IC _1a is synchronized circuit SY ₁₁ is arranged, the same way to block IC _1b synchronous circuit SY ₁₂ is a synchronous circuit SY _{13 in the} block IC _1c.
But synchronizing circuit SY ₁₄ is disposed to block IC _1d. Furthermore, inside the block IC _1e , a block IC
_1a , IC _1b , IC _1c and IC _1d surrounding a high potential power supply main line RLV and a low potential power supply main line RLG
Are supplied, and a power supply voltage is supplied via a high potential power supply terminal VD and a low potential power supply terminal GD, respectively. Then, inside the block IC _1a and IC _1b, is a high potential power source branch line BLV ₁₁ and the low-potential power source branch line BLG ₁₁ is wired to pass through the both blocks, inside the block IC _1c and IC _1d, the two blocks and the high potential power supply branch lines BLV ₁₂ and the low-potential power source branch line BLG ₁₂ are wired so as to pass through the, inside the further blocks IC _1a and IC _1c, similarly high potential power source branch line BLV to penetrate the two blocks ₁₃ and the low-potential power source branch line BLG ₁₃ is wire, the interior of the block IC _1b and IC _1d, a high potential power source branch line BLV ₁₄ and the low-potential power source branch line BLG ₁₄ so as to penetrate through the both blocks are wired.

[0017] In FIG. 2, the synchronization clock signal input to the clock input terminal PD ₁₂ is the interface
Introduced into the semiconductor chip IC ₁ via the buffer circuit IF ₁₂ , branched into two via a CMOS inverter circuit BF ₁₁ arranged substantially at the center of the semiconductor chip IC ₁ , and each of the CMOS inverter circuits BF ₁₂ and is input to the BF _13. Block IC _1a and Block IC _1b
Clock signal output via a CMOS inverter circuit BF ₁₂ disposed substantially in the boundary between the still 2
It is branched and input to the CMOS inverter circuits BF ₁₄ and BF _15, respectively. Similarly, block IC _1c
C which is arranged at a substantially boundary position between the block IC _1d
MOS inverter circuit clock signal output via the BF ₁₃ is further bifurcated, it is input to the CMOS inverter circuit BF ₁₆ and BF _17, respectively. And finally, a clock signal output through the CMOS inverter circuit BF ₁₄ disposed substantially in the center of the block IC _1a is supplied to the synchronizing circuit SY ₁₁ ends, substantially blocks IC _1b s clock signal output via a CMOS inverter circuit BF ₁₅ disposed in the center is supplied to the end of the synchronizing circuit SY _12, further block IC _1c
CMOS inverter circuit B arranged substantially at the center of
Clock signal output via the F ₁₆ is supplied to the end of the synchronizing circuit SY _13, a clock signal output through the CMOS inverter circuit BF ₁₇ disposed substantially in the center of the block IC _1d is terminated It is the supplied to the synchronizing circuit SY _14.

The CMOS inverter circuits BF ₁₂ , BF ₁₃ , BF ₁₄ , BF ₁₅ , BF ₁₆ and B shown in FIG.
Internal structure of the transistor-level F ₁₇ is Tori shown in FIG. 3, terminal _{PD 1, PD 2, PD 3} , P
D ₄ , PD ₅ and PD ₆ are a clock input terminal, a high-potential power supply terminal, a low-potential power supply terminal, a back gate voltage supply terminal for an enhancement P-channel MOS transistor, and a back gate voltage for an enhancement N-channel MOS transistor, respectively. Indicates a supply terminal and a clock output terminal. Regarding the configuration of these CMOS inverter circuits, FIG.
The outline is shown.

The supply of the back gate voltage to each CMOS inverter circuit shown in FIG. 3 is performed as follows. That, is arranged inside the block IC _1e, and a back gate voltage output from the back gate voltage generating circuit VB ₁ which is controlled via a control terminal PD ₁₃ is a back gate voltage source branch line BLP _{11 Contact} and BLN ₁₁ through, is supplied to the enhancement type P-channel MOSFET and an enhancement-type N-channel MOSFET of the CMOS inverter circuit BF ₁₂ respectively, similarly, disposed within the block IC _1e, and a control terminal P
Back-gate voltage generator VB which is controlled via a D _14
The back-gate voltage output from ₂ is applied to CLP via back-gate voltage source branch lines BLP ₁₂ and BLN ₁₂ , respectively.
Enhancement type P _in MOS inverter circuit BF13
It is supplied to a channel MOSFET and an enhancement type N-channel MOSFET. Block I
The back gate voltage output from the back gate voltage generation circuit VB ₃ disposed inside C 1 _e and controlled via the control terminal PD ₁₅ is equal to the back gate voltage source branch line BLN.
₁₃ , the CMOS inverter circuits BF ₁₄ and BF
A back gate voltage output from a back gate voltage generation circuit VB ₅ which is supplied to each of the enhancement type N-channel MOSFETs in _{16 and} is similarly arranged inside the block IC 1 _e and controlled through a control terminal PD ₁₇ through the back gate voltage source branch line BLP _13, CM
Supplied to each of the enhancement type P-channel MOSFET in the OS inverter circuit BF ₁₄ and BF _16. Further, the back gate voltage output from the back gate voltage generation circuit VB ₄ arranged inside the block IC 1 _e and controlled via the control terminal PD ₁₆ is supplied to the CMOS inverter circuit BF via the power supply branch line BLN _14. the enhancement N-channel in the ₁₅ and BF ₁₇ a MOSFET
A back gate voltage output from a back gate voltage generation circuit VB ₆ that is supplied to each of the T and is similarly arranged inside the block IC 1 _e and controlled via a control terminal PD ₁₈ is a back gate voltage source. via the branch line BLP _14, it is supplied to each of the enhancement type P-channel MOSFET in the CMOS inverter circuit BF ₁₅ and BF _17.

Next, a test method according to the present embodiment will be described with reference to FIGS. Note that in this case, the clock skew to a synchronous circuit SY ₁₂ at the end of the synchronization circuit SY _11, assume that the operation timing margin time of the data signal to a synchronous circuit SY ₁₂ in the synchronous circuit SY ₁₁ has only △ M _01. Similarly, the synchronous circuit S
In operation timing margin time △ M ₀₂ of the data signal to the synchronization circuit SY ₁₃ of Y _11, an operation timing margin time △ M ₀₃ of the data signal to the synchronization circuit SY ₁₄ of the synchronizing circuit SY _11, synchronizing circuit SY ₁₂ operation timing margin time of the data signal to a synchronous circuit SY ₁₁ is △ M _04,
Operation timing margin time of the data signal to a synchronous circuit SY ₁₃ of the synchronizing circuit SY ₁₂ is in △ M _05, synchronizing circuit SY ₁₂
Synchronous operation timing margin time of the data signal to the circuit SY ₁₄ is the △ M _06, synchronizing circuit SY operation timing margin time of the data signal with respect to ₁₁ △ M ₀₇ of the synchronizing circuit SY _13, the synchronization of the synchronizing circuit SY ₁₃ in operation timing margin time of the data signal for the circuit SY ₁₂ is △ M _08, an operation timing margin time △ M ₀₉ of the data signal to the synchronization circuit SY ₁₄ of the synchronizing circuit SY _13, further synchronization circuit S
Synchronous circuit operation timing margin time of the data signal with respect to SY ₁₁ is △ M ₁₀ of Y _14, the synchronization circuit S of the synchronization circuit SY ₁₄
In operation timing margin time △ M ₁₁ of the data signal with respect to the Y _12, assumed operation timing margin time for synchronization circuit SY ₁₃ of the synchronizing circuit SY ₁₄ is △ M _12.

Therefore, the control terminals PD ₁₃ , PD _14, P
In response to control signals applied to D ₁₅ , PD ₁₆ , PD ₁₇ and PD ₁₈ , back gate voltage generation circuits VB ₁ , VB _1
2 , VB ₃ , VB ₄ , VB _5, and the back gate voltage generated from VB ₆ cause the propagation delay change amount generated in the CMOS inverter circuits BF ₁₂ , BF ₁₃ , BF ₁₄ , BF ₁₅ , BF ₁₆ , and BF _{17 to} be: △ T ₁ , △
It is assumed that T ₂ , ΔT ₃ , ΔT ₄ , ΔT ₅ , ΔT ₆ . In this case, in the clock signal distribution processing according to the present embodiment, necessary conditions for preventing a timing malfunction from occurring are defined by the following conditional expressions (1) to (12). Any one of the formulas
If the expression is not satisfied, a timing malfunction will occur.

ΔM ₀₁ <(ΔT ₃ −ΔT ₄ )... (1) ΔM ₀₂ <(ΔT ₁ + ΔT ₃ ) − (ΔT ₂ + ΔT ₅ ) (2) ΔM ₀₃ <(ΔT ₁ + ΔT ₃ )-(ΔT ₂ + ΔT ₆ ) ... (3) ΔM ₀₄ <(Δ T ₄ −ΔT ₃ )... (4) ΔM ₀₅ <(ΔT ₁ + ΔT ₄ ) − (ΔT ₂ + ΔT ₅ ) ... (5) ΔM ₀₆ <(ΔT ₁ + ΔT ₄ ) − (ΔT ₂ + ΔT ₅ )... (6) ΔM ₀₇ <(ΔT ₂ + ΔT ₅ ) − (Δ T ₁ + ΔT ₃ ) (7) ΔM ₀₈ <(ΔT ₂ + ΔT ₅ ) − (ΔT ₁ + ΔT ₄ )... (8) ΔM ₀₉ <(Δ) _{T 5 - △ T 6) ..........................................} (9) △ M 10 <(△ T 2 + △ T 6) - (△ T 1 + △ T 3) ......... (10) ΔM ₁₁ <(ΔT ₂ + ΔT ₆ ) − (Δ T ₁ + ΔT ₄ ) (11) ΔM ₁₂ <(ΔT ₆ −ΔT ₅ ) …………………… (12) In this case, in this embodiment, The conditions under which the timing malfunction occurs are shown by the above equations (1) to (12). If any of these equations is not satisfied, the condition causing the timing malfunction is determined. Become. Therefore, the control terminals PD ₁₃ , PD ₁₄ , PD ₁₅ , PD
₁₆ , the control signals input to PD ₁₇ and PD ₁₈
Back gate voltage generation circuits VB ₁ , VB ₂ , VB ₃ , V
B _4, VB ₅ and the back gate voltage is generated from VB ₆ and the CMOS inverter circuit BF _12, BF _13,,
The respective relationships among the propagation delay change amounts ΔT ₁ , ΔT ₂ , ΔT _1, and ΔT ₄ in BF ₁₄ , BF ₁₅ , BF _16, and BF ₁₇ are investigated at the design stage, and an allowable operation timing margin time is determined. M ₀₁ , △ M ₀₂ , △ M ₀₃ , △ M ₀₄ ,
_{△ M 05, △ M 06,} △ M 07, △ M 08, △ M 09, △ M 10, △
On which also determine the M ₁₁ and △ M _12, using the above equations, advance control terminal _{PD 13, PD 14, PD 15} , PD 16, P
By previously quantified control signal amount to be input to D ₁₇ and PD _18, a semiconductor chip which can cause timing malfunction, it can be easily selected at the time of testing.

The back gate voltages for the enhancement type P-channel MOSFET and the enhancement type N-channel MOSFET constituting each of the CMOS inverter circuits BF ₁₄ and BF ₁₆ are controlled by control terminals PD ₁₇ and PD ₁₅ , respectively. Signal, back gate voltage generation circuits VB ₅ and VB _5
3 independently controlled and supplied. Similarly, CM
The back gate voltages of the enhancement-type P-channel MOSFET and the enhancement-type N-channel MOSFET constituting each of the OS inverter circuits BF ₁₅ and BF ₁₇ are controlled by the control signals input via the control terminals PD ₁₈ and PD ₁₆ , respectively. Voltage generation circuit VB6 And it is supplied are controlled independently from VB _4. Accordingly, the operation of not only advancing or delaying the phase relative to other distributed clock signals but also advancing or delaying only the rising time or only the falling time, that is, the clock It is also possible to control the pulse width (clock duty) of the convex portion or concave portion of the clock signal waveform while keeping the frequency of the signal constant. This allows
The minimum pulse width required for recognizing the clock signal in the terminal synchronization circuit can also be tested.
It can be a test target for selecting semiconductor chips of a T integrated circuit.

FIG. 4 is a block diagram further oriented to the floor layout on the semiconductor chip IC ₂ in the second embodiment to which the present invention is applied. The semiconductor chip IC ₂ is composed of four blocks IC _2a , IC _2b , IC _2c and IC _2d, and the block IC _2d mainly has a signal terminal P for inputting / outputting an external signal.
D ₂₁ , D ₂₂ , PD ₂₃ , PD ₂₄ , PD _25, and PD ₂₆ , a high-potential-side power supply terminal VD for supplying power, a low-potential-side power supply terminal GD, interface circuits IF ₂₁ , IF ₂₂ , and I
F ₂₃ , IF ₂₄ , IF ₂₅ , IF ₂₆ and IF ₂₇ are arranged, while the blocks IC _2a , IC _2b and IC
_{In 2c} , a circuit that mainly performs a logical operation is arranged. In particular, in the present embodiment, the block I
The C _2a is arranged synchronizing circuit SY ₂₁ and SY _22, to block IC _2b is disposed synchronous circuit SY ₂₃ and SY _24, synchronizing circuit SY ₂₅ and SY ₂₆ is arranged in the block IC _2c.

Further, inside the block IC _2d , a high-potential power supply main line RLV and a low-potential power supply main line RLG circling so as to surround the blocks IC _2a , IC _2b , and IC _2c are wired, and each of the high-potential power supply terminals VD A power supply voltage is supplied via the low potential power supply terminal GD. Block IC
Inside the _2a, the high potential power supply branch line BLV ₂₁ and the low-potential power source branch line BLG ₂₁ are wired so as to pass through the block, inside the block IC _2b, a high-potential power source branch line BLV to penetrate the block ₂₂ and GND power supply branch line B
LG ₂₂ is wired, and inside the block IC _2c ,
The high potential power supply branch lines BLV ₂₃ and the low-potential power source branch line BLG ₂₃ are wired so as to pass through the block.

[0026] Therefore, synchronous clock signal supplied to the clock input terminal PD ₂₃ is split into two by the data input interface buffers IF ₂₃ after being guided into a semiconductor chip, are arranged on left and right sides Input An input interface buffer IF arranged at the center of the left side and the center of the right side of the semiconductor chip via the interface buffers IF ₂₄ and IF ₂₅ , respectively
₂₆ and IF ₂₇ . The clock signal output via the input interface buffer IF ₂₆ is further divided into three, and then divided into blocks IC _2a and IC _2b , respectively.
And the CMOS inverter circuits BF ₂₁ , BF ₂₃ and BF ₂₅ arranged at the left end of the IC _2c . Similarly, the clock signal output via the input interface buffer IF ₂₇ is further branched into three, and then the CMOS inverter circuits BF ₂₂ and BF ₂₂ arranged on the right ends of the blocks IC _2a , IC _2b and IC _2c , respectively. Input to BF ₂₄ and BF ₂₆ . Then, MOS inverter circuit BF ₂₁ and the MOS inverter circuit clock signal output via the BF ₂₂ is coupled at the center of the block IC _2a, similarly CMOS inverter circuit BF ₂₃
And the clock signal output via CMOS inverter circuit BF ₂₄ are coupled at the center of block IC _2b , and the clock signal output via CMOS inverter circuit BF ₂₅ and CMOS inverter circuit BF ₂₆ is Combined at the center of _2c . In this way, a comb-shaped clock signal distribution circuit as a whole is formed.

The CMOS inverter circuits BF ₂₁ , B
The transistor-level configuration of F ₂₂ , BF ₂₃ , BF ₂₄ , BF ₂₅ and BF ₂₆ is the same as the configuration shown in FIG. Finally, the CMOS inverter circuit BF ₂₁ ,
The clock signals output via BF ₂₂ , BF ₂₃ , BF ₂₄ , BF ₂₅ and BF ₂₆ are respectively output to the terminal synchronous circuits SY ₂₁ , SY ₂₂ , SY ₂₃ , SY ₂₄ , SY ₂₅ and SY ₂₆
To synchronize the semiconductor chip IC _{2 as} a whole. Here, the terminal synchronization circuits SY ₂₁ , Y ₂₂ , SY
_23, SY _24, SY _25, and SY _26, the data input-output terminal PD _21, D ₂₂ and data input and output interface
While exchanging data synchronized with each other via a data signal line together with a data signal input via the buffers IF ₂₁ and IF ₂₂ , a desired logical operation operation is realized as a whole of the semiconductor chip IC ₂ . data output interface buffers IF ₂₁ logic operation result, IF
_The data is output to the outside via the data input / output terminal ₂₂ and data input / output terminals PD ₂₁ and PD ₂₂ .

From the back gate voltage generation circuit VB ₇ arranged in the block IC 2 _d and controlled via the control terminal PD ₂₄ , the CMOS inverter circuit BF is connected via the back gate voltage source branch lines BLP ₂₁ and BLN _{21. 21} and BF ₂₂ , respectively, within the enhancement P-channel MOSFET and the enhancement N
A back gate voltage is supplied to each of the channel MOSFETs, and a back gate voltage is supplied from a back gate voltage generation circuit VB ₈ disposed in the block IC 2 _d and controlled via a control terminal PD _25. source via a branch line BLP ₂₂ and BLN _22, the interior of CMOS inverter circuits BF ₂₃ and BF _24, the back gate voltage is supplied to each of the enhancement type P-channel MOSFET and an enhancement-type N-channel MOSFET included respectively. Similarly, from the back gate voltage generation circuit VB ₉ disposed in the block IC 2 _d and controlled via the control terminal PD ₂₆ , the C gate is supplied via the back gate voltage source branch lines BLP ₂₃ and BLN _23.
MOS inverter circuits BF ₂₃ and BF ₂₄ include enhancement-type P-channel MOSFs respectively included therein.
ET and enhancement type N-channel MOSFET
A back gate voltage is supplied to each of them.

Next, a test method for the second embodiment shown in FIG. 4 will be described. Now, here, the synchronous circuit S
Due to the clock skew of Y ₂₁ and SY ₂₂ with respect to synchronization circuits SY ₂₃ and SY ₂₄ , these synchronization circuits SY ₂₁
It is assumed that there is an operation timing margin time ΔM ₁₃ of the data signal for the synchronization circuits SY ₂₃ and SY _{24 in the} SY ₂₂ and the SY ₂₂ . Similarly, the synchronization circuit SY ₂₁ and SY ₂₂
The operation timing margin time for synchronization circuit SY ₂₅ and SY ₂₆ are △ M _14, synchronizing circuit SY ₂₃ and S
The operation timing margin time of Y ₂₄ with respect to the synchronization circuits SY ₂₁ and SY ₂₂ is ΔM ₁₅ , and the synchronization circuits SY ₂₃ and SY
₂₄ , the operation timing margin time for the synchronization circuits SY ₂₅ and SY ₂₆ is ΔM ₁₆ , and the synchronization circuits SY ₂₅ and SY ₂₆
The operation timing margin time for synchronization circuit SY ₂₁ and SY ₂₂ is △ M _17, synchronizing circuit SY ₂₅ and SY
_26, assume that the operation timing margin time for synchronization circuit SY ₂₃ and SY ₂₄ has only △ M _18.

Therefore, the control terminals PD ₂₄ , PD ₂₅ and P
In response to a control signal input to the D _26, bags gate voltage generating circuit VB _7, the back gate voltage generated in VB ₈ and VB _9, CMOS inverter circuits BF ₂₁ and BF _22, BF ₂₃ and BF _24, Assuming that the propagation delay changes in BF ₂₅ and BF ₂₆ are ΔT ₇ , ΔT ₈ and ΔT ₉ , respectively, the conditions under which the timing malfunction occurs in the present embodiment are as follows (13) to (18).
It is shown by the formula, and if any one of these formulas is not satisfied, a timing malfunction will result.

ΔM ₁₃ <(ΔT ₇ −ΔT ₈ )... (13) ΔM ₁₄ <(ΔT ₇ −ΔT ₉ ) (14) ΔM ₁₅ <(ΔT ₈ −ΔT ₇ ) …………… (15) ΔM ₁₆ <(ΔT ₈ − △ T ₉ ) ………………… (16) ΔM ₁₇ <(△ T ₉ − △ T ₇ ) ………………………………… _{(17) △ M 18 <(} △ T 9 - △ T 8) .......................................... (18) are thus inputted to the control terminal PD _24, PD _{25 Contact} and PD ₂₆ The back gate voltage generation circuit V
And the back gate voltage generated in B _7, VB ₈ and VB _9, CMOS inverter circuits BF ₂₁ and BF _22,
CMOS inverter circuit BF ₂₃ and BF _24, and CMO
In the design stage, the relationship between the propagation delay change amounts ΔT ₇ , ΔT ₈ and ΔT _{9 in} the S inverter circuits BF ₂₅ and BF ₂₆ is investigated, and an allowable operation timing margin time {M ₁₃ ,} _{M 14, △ M 15, △} M 16, △ M 17
And △ M ₁₈ value even after having determined, by using the above equation, by previously quantified control signal amount to be input in advance _control to the control terminal PD _24, PD ₂₅ and PD _26, causing timing malfunction Possible semiconductor chips can be selected in advance during a test.

[0032]

As described above, the present invention has a clock distribution network in response to a clock signal input from the outside to a terminal circuit which ultimately forms a supply target of the clock signal. Then, the present invention is applied to a semiconductor integrated circuit formed as a synchronous MOSFET integrated circuit, and at the time of testing the semiconductor integrated circuit, by externally controlling, by intentionally controlling the back gate voltage input to the CMOS inverter circuit, The threshold value and the propagation delay amount of the CMOS inverter circuit are changed, whereby a semiconductor chip having a small margin of timing operation, that is, a semiconductor chip having low reliability in synchronous operation is intentionally caused to generate a timing malfunction and selected. And a semiconductor chip having a large operation margin in terms of timing, that is, Any time easily becomes possible to select a lower semiconductor chip-risk for causing a timing malfunction on work, there is an effect that it is possible to realize a semiconductor integrated circuit including a more reliable semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram of a layout on the semiconductor chip of the first embodiment;

FIG. 3 is a circuit diagram showing a CMOS inverter circuit according to the first embodiment.

FIG. 4 is a block diagram illustrating a layout on a semiconductor chip according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a layout on a conventional semiconductor chip.

[Explanation of symbols]

IC _1, IC _2, IC ₃ semiconductor chip _{IC 1a, IC 1b, IC 1c} , IC 1d, IC 1e, IC 2a, I
C _2b , IC _2c , I C _2d , IC _3a , IC _3b , IC _3c, I
C _3d block PD _11, PD _21, PD ₂₂ data input terminal PD _12, PD _23, PD ₃₁ clock input terminal PD ₃₂ reference clock input terminal _{PD 13, PD 14, PD 15} , PD 16, PD 17, PD 18
Control terminal VD high-potential power supply terminal GD low potential power supply terminal IF _11, IF ₂₁ the data input-output interface buffer _{IF 12, IF 23, IF 24} , IF 25, IF 26, IF 27
Clock input interface buffer _{BF 11, BF 12, BF 13} , BF 14, BF 15, BF 16, B
_{F 17, BF 21, BF 22} , BF 23, BF 24, BF 25, BF
₂₆ CMOS inverter circuit BF ₃₁ , BF ₃₂ , BF ₃₃ , BF ₃₄ , BF ₃₅ buffer circuit SY ₃ , SY ₁₁ , SY _12, SY ₁₃ , SY ₁₄ , SY ₂₁ , S
_{Y 22, SY2 3, SY 24} , SY 25, SY 26 synchronous circuit _{VB 1, VB 2, VB 3} , VB 4, VB 5, VB 6, V
B7 , VB _8, VB ₉ back gate voltage generation circuit RLV high potential power supply trunk RLG low potential power supply trunk _{BLP 11, BLP 12, BLP1 3} , BLP 14, BLP 21,
_{BLP 22, BLP 23, BLN 11} , BLN 12, BLN 13,
_{BLN1 4, BLN 21, BLN 22} , BLN 23 backgate voltage source branch _{BLV 11, BLV 12, BLV 13} , BLV 14, BLV 21,
_{BLV 22, BLV 23, BLG 11} , BLG1 2, BLG 13,
_{BLG1 4, BLG 21, BLG 22} , BLG 23 power branch line _{PC 31, PC 32, PC 33} , PC 34 clock phase adjusting circuit CK _0, CK _1, CK2 , CK ₃ , CK ₄ , CKD ₁ ,
CKD2 , CKD3 , CKD ₄ clock signals CKR ₀ , CKR ₁ , CKR ₂ , CKR ₃ , CKR ₄
Reference clock signal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 H01L 21/822 H01L 27/04 G06F 1/10 H03K 19/00

Claims (4)

(57) [Claims] 1. A having a predetermined clock input terminal, synchronous with a clock distribution circuit supplying the <br/> more terminal circuits to distribute a clock signal input from the click <br/> clock input terminal in the semiconductor integrated circuit formed by MOSFET integrated circuit, the clock distribution circuit is divided to each of the plurality of terminals circuit the clock signal inputted via the <br/> plurality of branch points
A clock signal line network laid out so as to be sequentially branched in a branch shape for distribution, and an enhancer having a back gate voltage supply terminal inserted and connected to each of the branched wires for each of the plurality of branch points.
Statement P-Channel MOSFET and Enhancement
A plurality of CMOS inverter circuit composed of a type N-channel MOSFET, the control is responsive to a control signal supplied from the outside during the test
It is corresponding with the generating the back gate voltage, usually
In operation, the enhancement is performed in response to the non-supply of the control signal.
Statement P-Channel MOSFET and Enhancement
The same as the source voltage of each
Generating a back-gate voltage, a plurality supplies the back gate voltage to each of the previous SL C MOS inverter circuit
And a back gate voltage generation circuit, contact to the plurality of the wires after branching of the last branch point
The semiconductor integrated circuit and supplying an output clock signal of the CMOS inverter circuit connection was to the end circuits. Wherein said CMOS inverter circuit comprises a pre fangs <br/> Kkugeto voltage supply terminal, connected to the branch point corresponding to the gate, and a source connected to the high-potential power supply, the drain of the clock signal and the enhancing main <br/> cement-type P-channel MOSFET connected to the output line, before with Kiba Kkugeto voltage supply terminal, and commonly connected to the branch point of the gate with the enhancement-type P-channel MOSFET, the drain enhancement The semiconductor integrated circuit according to claim 1, further comprising: an enhancement-type N-channel MOSFET commonly connected to the clock signal output line together with a P-type MOSFET and having a source connected to a low-potential power supply. 3. The back gate voltage is supplied to each of a first CMOS inverter circuit, which is a pair of the CMOS inverter circuits, connected to each wiring after the first branch point of the plurality of branch points. Two first back-gate voltage generating circuits, each of which controls the P-channel MOSFET and the N-channel MOSFET in response to control of the control signal from outside;
And when the control signal is not supplied, the enhancement type P-channel MOSFET and the enhancement type N-channel M
A back gate voltage equal to the source voltage of each OSFET is generated, and each pair of C connected to each wiring after branching after the next branch point
A pair of second CMOS inverter circuits composed of any one of the MOS inverter circuits and the other
In contrast pair third CMOS inverter circuit comprising
Second and third back-gate voltage generator circuit supplies the back gate voltage, respectively are, of CMOS inverter circuit for in response to the control of the second or third of the pair of the external control signals, respectively A back gate for a P-channel MOSFET that generates a common back gate voltage for each of the P-channel MOSFETs and generates the same back gate voltage as the source voltage of the enhancement type P-channel MOSFET when the control signal is not supplied. A voltage generation circuit for generating a common back gate voltage for each of the N-channel MOSFETs of the pair of second or third CMOS inverter circuits in accordance with a control value of the control signal from the outside; When the control signal is not supplied, the enhancement type N-channel MOSFE The semiconductor integrated circuit according to claim 1, characterized in that it consists of a back gate voltage generation circuit for N-channel MOSFET source voltage to generate the same back gate voltage and the. 4. A clock signal input from the clock input terminal and having a predetermined clock input terminal, and a clock signal input from the outside through a CMSO inverter circuit supplied with a back gate voltage by a plurality of back gate voltage generating circuits.
A test method for a semiconductor integrated circuit formed by a synchronous MOSFET integrated circuit having a clock distribution circuit for supplying to a plurality of terminal circuits, wherein a plurality of back gate voltages are selected from the plurality of back gate voltage generation circuits by an arbitrary combination. a first step of selecting a generator, in response to a control signal from the external that correspond to a plurality of back-gate voltage generator circuit selected in the first step, from the back-gate voltage generator circuit, a second step of generating and outputting any back gate voltage, respectively, by inputting the synchronization clock signal to the clock input terminal, predetermined with respect to the semiconductor integrated circuit formed by the synchronous MOSFET integrated circuits A third step of performing an operation test of any one of the plurality of back gate voltage generation circuits; A fourth step of repeatedly executing the second and third steps by using a plurality of back gate voltage generation circuits selected by a combination , and at least a fourth step of testing the semiconductor integrated circuit. .