JP3202271B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.
In particular, the present invention relates to a protective film for a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, after an element is formed on a semiconductor substrate, an insulating film is formed so as to cover the element, and a contact hole is opened in the insulating film at a necessary portion by using a photo-etching technique or the like. An electrode wiring material such as Al is deposited so as to be embedded. The wiring is formed by forming a layer of an electrode wiring material on an insulating film, and removing unnecessary portions by etching using a desired wiring pattern as a mask. After that, an insulating film is further formed to form an upper wiring, or to form a protective film on the wiring surface.

The pad electrode is formed, for example, at the periphery of the semiconductor chip 51 surrounding the active element region 52 where the semiconductor circuit is formed in the center of the semiconductor chip 51, as shown in FIG. After patterning the wiring and forming a protective insulating film on the entire surface of the semiconductor substrate, the electrode pad 53 opens a necessary number of rectangular contact holes in the protective insulating film on the periphery of the semiconductor chip 51 to expose the wiring, It is formed. The wiring is formed of Al, an Al alloy, or the like, and connects a lead electrode of the element to an electrode pad. The electrode pad is connected to a package external terminal by a gold wire or a TAB lead.

[0004]

The electrode wiring material used for the semiconductor device is made of fluorine, sulfur,
Various contaminants such as chlorine, moisture in the air and water from washing are easily attached to the surface.

[0005] For this reason, a corrosion reaction (mainly an oxidation reaction) proceeds on the electrode wiring material, and at the same time, the surface of the electrode wiring is covered with an insulating film, resulting in the following problems.

First, the corrosion reaction erodes the electrode wiring material and causes a disconnection failure, or the wiring becomes thin even when the disconnection does not occur, causing a problem of reliability.

Secondly, in particular, on a bonding surface such as a via contact portion for making contact between the lower and upper electrode wiring materials, a deposit or a film is formed on the lower electrode wiring surface by corrosion or the like, and immediately before bonding. Even if sputter etching is performed using argon gas or the like, conduction failure due to insufficient etching may occur.

Third, work is performed while the electrode pad portion is exposed to the contact hole opening and the bonding step. Therefore, when bonding the electrode pad to a gold wire or the like, the coating due to the corrosion or the like on the surface of the electrode pad cannot be destroyed by external force at the time of bonding, which may result in poor bonding or insufficient bonding strength. . Further, even when a barrier metal film is formed on the surface of the wiring exposed in the contact hole, if a film such as a corrosion is formed on the surface of the barrier metal film, it may cause conduction failure.

Fourthly, there are usually many time constraints and work precautions between the steps in order to prevent surface contamination and moisture absorption during the steps, and contamination and corrosion reactions occur even after the electrode wiring is formed. Strict conditions must be set to prevent the progression of the event.

Although the corrosion reaction of the electrode material proceeds mainly in the presence of water, it is impossible to cut off the water from the manufacturing process of the semiconductor device. There was a strong desire for a way to do that.

[0011]

According to the present invention, a water-repellent coating is formed on a surface of a metal film formed on a semiconductor substrate during a process of forming an element in a semiconductor device. Providing a method of manufacturing a semiconductor device, wherein the surface of the metal film is an electrode pad opening. Further, the present invention includes a step of forming a water-repellent film on a surface of a metal film formed on a semiconductor substrate during a step of forming an element in the semiconductor device, wherein the step of forming the water-repellent film includes etching. An organic silicon compound having a lower specific gravity than the treatment liquid or the cleaning water and the etching treatment liquid or the cleaning water are stored in one tank, and after selectively etching the metal film, the semiconductor substrate is subjected to the etching treatment liquid or A method of manufacturing a semiconductor device, wherein the water-repellent coating is formed by passing through the silicon compound layer when being pulled up from cleaning water.

[0012]

[0013]

[0014]

By forming a water-repellent coating on the surface of the electrode wiring, contamination such as chlorine is prevented, and the corrosion reaction of the electrode wiring material is suppressed. Further, since the organosilicon compound is a good insulating material, surface leakage between electrodes on the insulating film is also suppressed.

[0015]

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. In this embodiment, the present invention is applied to a MOS FET.

As the organosilicon compound used in the present invention, for example, polydiorganosiloxane in polyorganosiloxane (hereinafter referred to as silicone) is shown in FIGS. Silicone can be classified into three basic types, oil, rubber, and resin, depending on its properties. Among them, FIG. 3 shows the chain molecular structure of silicone oil, and 1 represents an integer of 0 or more. Indicates a cyclic molecular structure,
m represents an integer of 3 or more. Here, R is the same or different, substituted or unsubstituted monovalent hydrocarbon group, mainly a methyl group (CH ₃ ), a phenyl group (C ₆ H ₅ ), a long-chain alkyl group (C _n H _{2n + 1} ), trifluoropropyl group (CF ₃
CH ₂ CH ₂ ).

The MOS FET is formed using a conventional method. That is, as shown in FIG. 1 and FIG.
An element isolation region 2 for isolating a memory cell is formed to a thickness of about 800 nm on the surface of the p-type semiconductor substrate 1 by a method such as COS. Thereafter, for example, using hydrochloric acid, 30
A gate insulating film 3 of about nm is formed, and for example, boron is introduced at a concentration of about 1 × 10 ²³ cm ⁻³ by ion implantation or the like to form a channel region 10. Next, for example, CV
By a method D, a polysilicon layer for forming a gate electrode is deposited on the entire surface of the gate insulating film 3 to a thickness of about 400 nm, and impurities are diffused at a concentration of about 1 × 10 21 to 102 1 cm −3.
Thereafter, the polysilicon layer is first etched by a dry etching method or the like to form the gate electrode 4 extending over the channel region 10.

Next, using the gate electrode 4 as a mask, 1 × 10 ¹⁵ cm
^{About -2} arsenic ions or the like are implanted in a self-aligned manner, and an n-type source region 5 is formed on the semiconductor substrate 1 with the gate electrode 4 interposed therebetween.
a, a drain region 5b is formed. Subsequently, the film thickness of 400 nm is formed on the element region including the gate electrode 4 by using a CVD method or the like.
A degree of interlayer insulating film 6 is formed.

Thereafter, parts other than the contact are masked, and the source contact hole 7a is formed in the interlayer insulating film 6 and the gate oxide film 3 on the source region 5a and the drain region 5b.
And a contact hole 7b for the drain, and a contact hole 7c for the gate electrode in the interlayer insulating film 6 on the gate electrode 4 on the element isolation region 2 so that these contact holes are buried. A wiring material such as Al is deposited by the method described above to form a wiring material layer, and then, as shown in FIG.

Subsequently, the semiconductor substrate 1 is immersed in, for example, a silicone oil bath as an organosilicon compound bath, and heated and dried to form a very thin water-repellent coating 11 made of an organosilicon compound such as silicone on the wiring 8. . At this time, if the silicone is heated and dried, the process can be completed quickly, and there is an advantage that the operation is made more efficient. Here, the water-repellent coating 11 was formed on the wiring 8 by dipping in a silicone oil bath.
A silicone oil may be sprayed or applied. In addition, although the coating was dried by heating after application, air drying and natural drying may be used. Even if the coating is kept wet without drying, the effect remains unchanged. Further, it is more effective to form the water-repellent coating 11 after etching away a corrosion substance such as fluorine attached to the surface of the wiring 8. Finally,
A protective insulating film 9 is deposited on the entire surface by using a CVD method or the like.
The OS type FET is completed.

A step of forming a peripheral element may be appropriately included in the middle of the above steps. In particular, after the formation of the water-repellent coating 11, contamination by a metal such as chlorine and permeation of moisture can be prevented. The subsequent steps can be set under much more gradual time conditions than in the past. Further, since the water-repellent coating 11 is also formed on the interlayer insulating film 6, it is possible to prevent moisture absorption and moisture permeation into the interlayer insulating film 6, and to prevent the characteristic deterioration of the element for a long time. . Further, erosion and precipitation such as corrosion of the electrode material can be prevented in the future, so that reliability and durability can be improved. In addition, the water-repellent coating 11 formed as described above has excellent electrical insulation properties, and can effectively suppress surface leakage between electrodes on the insulating film or the like.

In the above, the embodiment for the p-channel MOS type FET has been described.
It can be used as a water-repellent coating on wiring of various semiconductor elements such as an OS-type FET and an EPROM. (Example 2)

Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG. The present embodiment is a method for forming a water-repellent coating using a bath in which an organosilicon compound is floated. As in the first embodiment, the process is performed up to the wiring material layer of the MOS FET.

Thereafter, the wiring material layer is patterned and unnecessary portions are removed by etching to form the wirings 8. At this time, by utilizing the fact that the specific gravity of the silicone oil is less than 1, a processing solution and a silicone The oil is put in one tank, the semiconductor substrate 1 is immersed in a processing tank having two layers of a processing solution and silicone oil, and an etching process is performed. When the semiconductor substrate 1 is lifted, the silicon film is passed through the silicone oil layer. It is formed on the wiring 8. Subsequently, the silicone film is dried by performing a heat treatment,
A thin water-repellent film 11 can be formed thereon. In addition, in the cleaning step after the etching treatment, the water tank for water cleaning is made of two layers of water for cleaning and silicone, and the semiconductor substrate 1 is washed after the water cleaning.
The water-repellent coating 11 made of silicone may be formed by passing through a silicone layer when pulling up. Of course, after the etching process, the water-repellent film 11 can also be formed by a method such as spraying or applying silicone oil. Although the silicone oil is dried by heat treatment, air drying and natural drying may be performed. Thereafter, as in the first embodiment, the protective insulating film 9 is formed and the MOS type FE is formed.
Complete T.

As described above, by performing the etching treatment and the washing treatment in a bath having two layers of silicone and a processing solution or water, the water-repellent coating 1 can be quickly and simply obtained after the treatment.
1 can be formed. The water-repellent coating 11
There is also the advantage that no extensive equipment is required for the formation. In the above, the case where the present invention is used for the MOS FET has been described. However, the present invention can be used for various other methods of manufacturing a semiconductor device. (Embodiment 3) Hereinafter, a third embodiment will be described in detail with reference to FIGS. In the third embodiment, the present invention is used for forming an electrode pad.

As in the prior art, a wiring is formed of Al or the like, a protective insulating film is formed thereon, and a rectangular contact hole for forming an electrode pad is opened in the protective insulating film on the periphery of the semiconductor chip 51. The wiring is exposed, and an electrode pad 53 is formed.

The semiconductor chip 51 on which the electrode pads 53 are formed is immersed in a bath containing silicone as an organosilicon compound in the same manner as in the first embodiment to form a silicone film on the electrode pads 53, and then heat. After drying, a water-repellent film is formed on the barrier metal film. When heat drying is performed on silicone, there is an advantage that the process can be completed promptly and work efficiency can be improved. Here, silicone is applied to the wiring by dipping in a silicone oil bath, but other than that, silicone oil may be sprayed or applied. In addition, although the coating is dried by heating after application, air drying and natural drying may be used, and the effect is not changed even if the coating is kept wet without drying. In addition, a further effect can be expected if a water-repellent film is formed after etching a corrosion substance such as fluorine adhered to the wiring surface.

The method for forming the water-repellent coating is as described in Embodiment 2, when the semiconductor chip 51 is treated in a processing solution or a bath having two layers of water and silicone, and the semiconductor chip 51 is pulled up. A water-repellent coating may be formed through a silicone film.

Thereafter, wire bonding is performed on the electrode pad 53. At this time, even if bonding is performed on the water-repellent film, the water-repellent film is sufficiently thin, so that there is no adverse effect on the bonding property. The coating may be removed. Here, since the water-repellent coating is sufficiently thin, it can be easily removed. In particular, since the water-repellent coating can prevent the corrosion reaction from progressing on the surface of the electrode pad 53, a good electrode surface can be easily exposed.

In the above, after forming the electrode pad on the protective insulating film, a water-repellent coating was formed on the electrode pad and bonding was performed. Before the bonding, the water-repellent coating was once removed and exposed. The bonding may be performed after forming a barrier metal film on the existing wiring material. Also, even if bonding is performed after forming a water-repellent coating on the barrier metal film, or the water-repellent coating is removed immediately before bonding, contamination of the wiring material and the like are avoided, and the corrosion reaction is well prevented. Insufficient conduction with the barrier metal film can be prevented. Further, if the cause of corrosion such as chlorine on the surface is removed by an argon sputtering method or the like before the formation of the water-repellent film, a further effect is obtained.

FIG. 6 shows the results of measuring the rate of decrease in the shear peel strength of the deterioration of the bondability of the gold wire due to humidification after forming the electrode pad. Although the shearing peel strength 61 of the electrode pad according to the conventional method is significantly reduced as the bonding property is left as it is, the bonding property can be maintained favorably without being changed in the present Example 62.

When the oxide film thickness on the electrode pad surface was analyzed, the oxide film thickness in the conventional method 61 increased with the standing time, whereas in the present embodiment, it did not change at about 5 nm. When the oxide film on the surface of the electrode pad is removed by etching again just before bonding the gold wire after forming the water repellent coating as in the present embodiment, the bonding strength is improved.

As described above, by forming the water-repellent coating on the electrode pad, contamination of the electrode pad and adsorption of moisture can be prevented, and the corrosion reaction can be suppressed. As a result, it is possible to prevent the deterioration of the bondability between the electrode pad and the gold wire, and to improve the reliability and durability of the element.

The process of exposing the electrode wiring material includes, in addition to the contact hole opening process for the electrode pad described above, an electrode wiring forming process, an electrode material deposition process, a contact hole opening process for an electrode, and the like. When a water-repellent coating is formed on the exposed electrode wiring material immediately after the process, contamination by fluorine or the like and adsorption of moisture can be prevented, and the progress of the corrosion reaction of the electrode wiring material can be effectively suppressed. Furthermore, if the present invention is used before the wafer back surface grinding step, the wafer pellet cutting step, the chip / frame joining step, the pellet sealing step, etc., it is possible to prevent the electrode wiring exposed portion from being contaminated.

[0035]

FIG. 7 shows the amount of corrosion generated when the wiring after patterning is left humidified. The wiring material is Al-
After sealing with a Si-Cu alloy in a 100% humidity container and leaving it at room temperature, the number of corrosions generated in 10 m of the wiring was measured.

In the conventional method 71, significant corrosion was observed as the standing time progressed, but in the case where the present invention was used and a water-repellent coating was formed, the corrosion hardly occurred.

As is clear from the above description, by forming a water-repellent film on the surface of the electrode wiring, the water-repellent film prevents moisture adsorption and contamination by metals such as sodium, and has a charge retention property. And the like, and the corrosion reaction of the electrode wiring and the like can be suppressed. This allows
Disconnection failure and thinning of the electrode wiring can be prevented, and reliability and durability can be improved. In addition, poor conduction can be effectively prevented at the joint surfaces between the electrode materials. Further, since the water-repellent coating is thin and can be easily removed, no inconvenience is caused in the subsequent steps. In addition, since the water-repellent coating has insulating properties, surface leakage between the electrodes can be effectively suppressed.

Further, even if a delay occurs between the steps, the water-repellent coating is formed on the surface of the insulating film, so that the corrosion reaction can be prevented from progressing. The film can be removed, allowing time between steps, and reducing attention in the steps.

[Brief description of the drawings]

FIG. 1 is a plan view of a MOS-type FET showing first and second embodiments of the present invention.

FIG. 2 is a cross-sectional view of a MOS FET showing first and second embodiments of the present invention.

FIG. 3 is a general formula of a linear polydiorganosiloxane. Here, R is the same or different, substituted or unsubstituted monovalent hydrocarbon group, mainly a methyl group (CH ₃ ), a phenyl group (C ₆ H ₅ ), a long-chain alkyl group (C _n H _{2n + 1} ),
And a trifluoropropyl group (CF ₃ CH ₂ CH ₂ ). L represents an integer of 0 or more.

FIG. 4 is a general formula of a cyclic polydiorganosiloxane. Here, R is the same or different, substituted or unsubstituted monovalent hydrocarbon group, mainly a methyl group (CH ₃ ), a phenyl group (C ₆ H ₅ ), a long-chain alkyl group (C _n H _{2n + 1} ),
And a trifluoropropyl group (CF ₃ CH ₂ CH ₂ ). M represents an integer of 3 or more.

FIG. 5 is a plan view of a semiconductor chip.

FIG. 6 is a diagram showing the results of measuring the rate of decrease in the shear peel strength of a gold wire due to humidification after forming an electrode pad.

FIG. 7 is a diagram showing the result of measuring the amount of corrosion generated when the wiring after patterning is left humidified.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Gate oxide film 4 Gate electrode 5a Source region 5b Drain region 6 Interlayer insulating film 7a Source contact hole 7b Drain contact hole 7c Gate electrode contact hole 8 Wiring 9 Protective insulating film 10 Channel region 11 Water repellent coating 51 Semiconductor chip 52 Active element area 53 Electrode pad 61 Shear peel strength reduction rate by conventional method 62 Shear peel strength reduction rate of third embodiment 71 Number of corrosions by conventional method 72 Number of corrosions by using the present invention

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 23/31 (56) References JP-A-5-21433 (JP, A) JP-A-50-139900 (JP, A) JP-A-63-177444 (JP, A) JP-A-5-82581 (JP, A) Jikken 41-21590 (JP, Y1) Monthly Semiconductor World (Press Journal) October 1990 No. 44-49 Page: “AI alloy film etching process for submicron multilayer wiring” Doichi Shinichi (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/312 H01L 21/316 H01L 21/60 301 H01L 21 / 3205 H01L 21/768

Claims (2)

(57) [Claims] 1. A method according to claim 1, wherein a step of forming an element in the semiconductor device includes the steps of:
Form a water-repellent coating on the surface of the metal film formed on the conductive substrate
Forming a metal film surface with an electrode pad opening
A method for manufacturing a semiconductor device. 2. A semiconductor device comprising :
Form a water-repellent coating on the surface of the metal film formed on the conductive substrate
Forming the water-repellent coating,
Organic lighter in specific gravity than etching solution or cleaning water
The silicon compound and the etching solution or cleaning water
Stored in one tank and selectively etched the metal film
Later, the semiconductor substrate is subjected to the etching solution or washing.
Pass through the silicon compound layer when pulling up from purified water
Forming the water-repellent coating by
Semiconductor device manufacturing method.