JP3201432B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, a medium dose ion implantation technique has been used for forming a ROM, a well, and a channel dope.

FIGS. 6A and 6B are views showing an example of a conventional manufacturing process of a semiconductor device. A method of manufacturing the semiconductor device will be briefly described below.

[0004] First, as shown in FIG.
Next, an element isolation layer oxide film 2 is formed by a conventional forming method. Next, an implantation step is performed using arsenic ions at an acceleration energy of 100 keV and an arbitrary dose in the range of 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ² to form the N ⁻ region 3. Subsequently, as shown in FIG. 6B, a gate oxide film 4 is formed at 1050 ° C. by N ₂ / O ₂ partial pressure oxidation (partial pressure ratio 30%).
Thereafter, the polycrystalline silicon film 5 is formed by LPCVD.
Is grown, and patterning is performed to leave only a portion to be a gate, thereby producing a polycrystalline silicon electrode. Hereinafter, a MOS capacitor is manufactured by a normal manufacturing process.

Here, as much as required as a characteristic of the depletion transistor, as much current as possible may be taken out. Arsenic dose 5 × 10 ¹⁴
/ Cm ² or more, crystal defects occur due to ion implantation at a high dose. For this reason, the dose of arsenic ions is set at an arbitrary dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ² . However, we have found that moderate dose ion implantation has a close relationship with the reliability of the gate oxide, and found that dose control is important. That is, by increasing the dose, a crystal defect is generated or a change in the characteristics of the transistor is caused due to a change in the film thickness due to the accelerated oxidation. In the portion near the edge of the isolation oxide film 2, It has been clarified that the influence of the generated stress has an adverse effect on the semiconductor device. Therefore, if the ion implantation dose is used in a wide range, the reliability of the gate oxide film is adversely affected.

[0006]

In the above-mentioned conventional manufacturing process, the dose of ion implantation is 1 × 10 ^{13 to} 5 × 10 ¹⁴ / c.
Since the value of m ² was arbitrarily set, crystal defects and damage occurred due to specific ion implantation, and the dielectric breakdown characteristics of the gate oxide film were degraded. Therefore, conventionally, when an electrical measurement of the characteristics of the semiconductor element is performed, for example, when a withstand voltage measurement is performed, the dose amount is 5 × 10
^{In the case of 13} / cm ² or in the vicinity thereof, deterioration of the withstand voltage is remarkably observed.

In addition, in the case of arsenic ion implantation, if the dose is 5 × 10 ¹³ / cm ² or in the vicinity thereof, when a minute stress current is applied, dielectric breakdown may occur. The charge amount is as low as about 1 C / cm ² , and there is a problem that it cannot withstand actual use.

Conventionally, when a semiconductor element is formed using phosphorus as an ion implantation species, the dose amount is 1 × 10
Using a dose of ¹⁴ / cm ² or near,
The breakdown voltage is about 4 MV / cm, which is a low value.

Also, in the case of a semiconductor device manufactured using B as an ion-implanted species in the conventional example, if the boron dose is 1 × 10 ¹⁴ / cm ² or a dose in the vicinity thereof, the breakdown withstand voltage is also increased. It is about 4 MV / cm, which is a low value.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a MOS depletion transistor which does not deteriorate the dielectric breakdown characteristics of a gate oxide film and ensures a sufficient transistor drive current.

[0011]

[MEANS FOR SOLVING THE PROBLEMS] To achieve this object
The method of manufacturing a semiconductor device according to the present invention
Ion implantation into the channel region of the transistor
In the process, the breakdown voltage of the gate insulating film
Ions in a dose range that is almost constant with changes in
Injection is performed. According to the invention, the gate
Extracting a large amount of current while ensuring the reliability of the insulating film
Forming a depletion transistor
Becomes possible. In particular, the dose is extremely small in dielectric breakdown voltage.
The value is in the area larger than the dose that gives the value
The greater the effect, the greater the effect. However, if the ion species is boron
In this case, the minimum value is in the middle dose region (1E12 to 1E15).
cm-2), just before the breakdown voltage starts to fall
It is desired to use a dose amount of

[0012]

[0013]

[0014]

[0015]

According to this manufacturing method, generation or increase of crystal defects or damage due to ion implantation can be prevented, and deterioration of the reliability of the gate oxide film can be prevented.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, as one embodiment of the present invention, a mask RO
Description will be made with reference to the drawings, taking a microcomputer having M and EPROM as an example.

First, as shown in FIG. 1A, a channel stopper and an element isolation layer oxide film 12 having a thickness of 500 nm are formed on a P-type (100) silicon substrate 11 having a resistance of 10 to 15 Ω.
It is formed by steam oxidation at 00 ° C. Next, the EEPROM
900 to form the floating gate region of
Temperature 40 ℃ by steam oxidation with addition of 4% by weight hydrochloric acid
Is formed, and a gate oxide film 13 is formed in a predetermined region. Subsequently, a polycrystalline silicon film containing 2 × 10 ²⁰ / cm ³ of phosphorus atoms was deposited at 610 ° C. by LPCVD.
It is formed to a thickness of 00 nm. After that, the polycrystalline silicon film 14 is patterned using a known photolithography technique and a dry etching technique to form the floating gate electrode 4. Thereafter, channel doping is performed on a predetermined transistor region serving as a depletion transistor portion of the transistor array of the mask ROM. In channel doping, arsenic ions are selectively implanted using a photoresist as a mask. The injection condition is an acceleration energy of 100 ke.
V is a dose of 2 × 10 ¹⁴ / cm ² . Thus, N ⁻ region 15 is formed. At this time, the dose of arsenic ions must be in the range of 1 to 5 × 10 ¹⁴ / cm ² .

FIGS. 2 and 3 show the relationship between the dose of arsenic ion implantation and the dielectric breakdown voltage and the amount of charge (Q _BD : Charge to breakdown) leading to dielectric breakdown. Both the dielectric breakdown voltage and Q _BD have a dose of 5 ×
It deteriorates most at 10 ¹³ / cm ² . 5 × 10 ¹³ / cm ²
No degradation occurs at the following doses. For this reason, it is possible to use a dose below this. However, the depletion type MO described in this embodiment
In an S transistor and a depression mask ROM using the same, it is necessary to lower the resistance of the channel region in order to improve the operation speed. For this purpose, the dose is set to 1 to 5 × 10 ¹⁴ / cm as in the present embodiment.
^It is recommended to use a high dose of ² . However, 5 × 10
^At a high dose of ¹⁴ / cm ² or more, problems such as an increase in leak current due to crystal defects occur. Therefore, the upper limit of the dose is set to 5 × 10 ¹⁴ / cm ² . Here, phosphorus may be used instead of arsenic as the ion species of the ions for channel doping. FIGS. 2 and 3 also show the dependence of the dielectric breakdown voltage and Q _BD characteristics on the dose of phosphorus ions when phosphorus is used as the ion species. In the case of phosphorus ion implantation, the dose at which the dielectric breakdown resistance is most deteriorated is slightly higher than that of arsenic, and is about 1 × 10 ¹⁴ / cm ² . Therefore, when phosphorus is used for channel doping, the ion dose is optimally 5 to 7 × 10 ¹³ / cm ² . In this case, the driving capability of the depletion transistor is sufficient with the ion dose in this range, and in particular, 2 × 10 ¹⁴
An implantation dose of more than / cm ² is not required.

Following the ion implantation into the ROM channel, N ₂ / O ₂ at 1050 ° C. as shown in FIG.
Mask ROM and EP by partial pressure oxidation (partial pressure ratio 30%)
The control gate portions of the ROM are simultaneously oxidized to form gate oxide films 16 and 17. At this time, the mask ROM
The gate oxide films 16 and 17 have a thickness of 30 nm and an EPR
The oxide film thickness of the OM control gate on the polycrystalline silicon film 14 is 45 nm.

Next, the polycrystalline silicon films 18 and 1 serving as control gate electrodes of the mask ROM and EPROM are formed.
9 is formed. The thickness of the polycrystalline silicon films 18 and 19 is 4
The thickness is set to 00 nm, and phosphorus atoms are deposited in a state containing 2 × 10 ²⁰ / cm ² . This polycrystalline silicon film 18,
19 is selectively etched to form polycrystalline silicon electrodes for the gate of the ROM section and the control gate (FIG. 1).
(C)).

Thereafter, the source of all the transistors
Arsenic ions are selectively implanted to form a drain region. The injection conditions at this time are as follows: acceleration energy 40 ke
V is a dose of 4 × 10 ¹⁵ / cm ² . Thus, an N ⁺ region 20 is formed. A microcomputer with a built-in EPROM having the mask ROM section formed as described above is manufactured.

In the above embodiment, the silicon substrate 1
If a P-type diffusion layer is formed with 1 as a P-type and a source / drain region, boron ion implantation can be used for channel doping for a depletion transistor in a mask ROM portion. FIG. 2 also shows the dielectric breakdown resistance and the like in this case.
3 and FIG.

According to our investigation results, when boron ion implantation is performed, the dose amount is 5 × 10 ¹⁴ / cm ^2.
It can be seen that the insulation breakdown resistance is most deteriorated. Therefore, the dose amount of boron ions is 5 × 10 ¹³ to 1
× 10 ¹⁴ / cm ² may be used.

It is to be used for channel doping.
Although rare, antimony and P-type N-type species
BF as ion species_TwoSimilarly, when using
A certain dose at which the puncture resistance deteriorates is observed. Anti
In the case of MON, the degradation of dielectric breakdown resistance is 3 to 5 × 10¹³/ C
m^TwoOccurs near the BF_Two7-1 × 10 in case of¹⁴/ Cm ^Two
Occurs near. Therefore, the optimal
The dose is 7 to 1 × 10 for antimony.¹⁴/ Cm^Two, BF^Two
Is 2-3 × 10¹⁴/ Cm^TwoBecomes

The following is an example of the results of electrical measurements performed on the semiconductor device of this example manufactured as described above.

FIG . 5 shows a dose of 5 × 10 ¹⁴ / cm of phosphorus as an ion implantation species for forming a mask ROM based on this embodiment .
² and 5 × 10 ¹³ / cm ² , and doses of 1 × 10 ¹⁴ / cm ² and 1 × 10
It is a result of TDDB measurement of the gate oxide film of the depletion transistor in the ROM part when the ion implantation is performed at ¹³ / cm ² . When the dose is 1 × 10 ¹⁴ / cm ² , the TDDB characteristics are clearly deteriorated. Further, the Q _BD deteriorates by about four digits, and the distribution of the deterioration is not the intrinsic destruction but the accidental destruction mode.

That is, according to the embodiment of the present invention, when the gate oxidation of the formed mask ROM is performed, the initial failure is 5% or less, and the total charge flowing before the dielectric breakdown in the oxide film before the dielectric breakdown occurs. The amount Q _BD is a high value of 10 C / cm ² or more. When this transistor is formed by a conventional technique, the initial failure is 20%, and the total charge Q
_BD was found to be a very low value of 10 ⁻² C / cm ² or less, confirming the effectiveness of the present invention.

In this embodiment, the upper limit of the dose is 5 × 10 ¹⁵ / cm ² for any of the ion-implanted species. In addition, problems such as an increase in the thickness of the gate oxide film due to the accelerated oxidation occur, so that use of a higher dose than this is not preferable.

Although there is no problem in the use in the ion implantation range as in this embodiment, when an arbitrary ion dose is used as in the conventional method, the dielectric breakdown characteristics may be further adversely affected. In the present embodiment, the ion implantation for forming the ROM is performed by directly implanting ions into the silicon substrate 1 and subsequently performing gate oxidation. However, the ion implantation for forming the ROM may be performed through an oxide film, or sacrificial oxidation or annealing may be performed before the gate oxidation. Among them, sacrificial oxidation and annealing after ion implantation
The specific ion dose that deteriorates the dielectric breakdown resistance of the gate oxide film deteriorates the reliability of the gate oxide film formed by the subsequent gate oxidation with respect to the dielectric breakdown.

FIG . 4 shows the TDDB characteristics of the gate oxide film when sacrificial oxidation, annealing and sacrificial oxidation are performed after arsenic ion implantation, and then gate oxidation is performed. As can be seen from these results, the heat treatment before the gate oxide film is formed deteriorates the dielectric breakdown reliability. Thus, they act as instability of the dielectric breakdown properties. Therefore, it is necessary to form a gate oxide film and ROM having high reliability, high stability, and high performance by using an optimum ion dose for each ion species as in this embodiment.

[0031]

According to the present invention, an excellent semiconductor device capable of preventing the deterioration of the reliability of a gate oxide film by forming a gate oxide film by limiting a dose during ion implantation. Can be.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in the order of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the dependency of the dielectric breakdown voltage of a gate oxide film on ion implantation.

FIG. 3 is a diagram showing the ion implantation dependency of the _QBD characteristics of a gate oxide film.

FIG. 4 is a diagram showing TDDB characteristics of a semiconductor device manufactured by the manufacturing method of the present invention.

FIG. 5 is a diagram showing the dependence of TDDB characteristics of a gate oxide film on ion implantation, sacrificial oxidation, and annealing.

FIG. 6 is a sectional view of a conventional method for manufacturing a semiconductor device in the order of steps.

[Explanation of symbols]

Reference Signs List 11 silicon substrate 12 oxide film 13 gate oxide film 14 polycrystalline silicon film 15 N ⁻ region 16, 17 gate oxide film 18, 19 polycrystalline silicon film 20 N ⁺ region

Continuation of the front page (56) References JP-A-3-177064 (JP, A) JP-A-4-61163 (JP, A) JP-A-62-229849 (JP, A)

Claims (5)

(57) [Claims] To 1. A silicon material under a gate oxide film of MOS type transistor, a ^{1 × 10 13 ~5 × 10 14} / The method of manufacturing a semiconductor device which performs a dose of ion implantation cm ^2, pre-silicon material to be measured by forming a gate oxide film after the ion implantation at a predetermined dose was a dose and gain
Based on the relationship between the breakdown voltage of over gate oxide film, a semiconductor dielectric breakdown voltage of the gate oxide film and performing the ion implantation at a substantially constant and becomes the dose area with respect to the change of the dose Device manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment at a temperature of 1000 ° C. or more after the ion implantation. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the dose is a value in a region larger than a dose that gives the minimum value of the dielectric breakdown voltage. 4. The method according to claim 1, wherein the ion species used for the ion implantation is boron, and the dose is a value in a region smaller than the dose that gives the minimum value of the dielectric breakdown voltage. A method for manufacturing a semiconductor device. 5. A method of manufacturing a semiconductor device in which a mask ROM and an EEPROM are simultaneously formed on a substrate, wherein said ion implantation is performed in a channel region of a depletion transistor portion in the mask ROM, and then thermal oxidation is performed at 1050 ° C. or higher. The gate oxide film of the mask ROM and the EEPROM
5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of simultaneously forming a gate oxide film of an M control gate portion.