JP3199207B2 - Multiport semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU having a plurality of independent input / output ports for accessing memory cells.
2-port RAM [R] used as a shared memory for transferring data between [Central Processing Unit]
and a multi-port semiconductor memory device such as a dual-port RAM.

[0002]

2. Description of the Related Art When a shared memory is used for data transfer between two CPUs, each
Mutual exclusion must be performed when access from the Internet competes. The two-port RAM is a semiconductor storage device used as such a shared memory.

FIG. 5 shows a two-port RAM 1 having two CPUs.
The configuration when used as a shared memory between 2 and 3 is shown. The two-port RAM 1 includes a memory cell array 11 composed of a large number of memory cells, and two ports, i.e., an A port 12 and a B port 13. A port 1
The address bus, the control bus and the data bus of each of the CPUs 2 and 3 are separately connected to the 2 and B ports 13, respectively, so that an address and a control signal are sent and data can be input / output.
The ports 12 and 13 can access the memory cell array 11 independently. That is, when the addresses sent to the ports 12 and 13 do not conflict with each other, the memory cell array 11 can be simultaneously accessed independently based on the addresses. In addition, even if addresses conflict, if both are performing a read operation, they can be accessed simultaneously. However, if at least one of the accesses is a write access, the access from one of the ports 12 and 13 needs to be stopped because the access is a target of mutual exclusion. This mutual exclusion is generally realized by a busy wait (busy wait) method.

FIG. 6 shows a configuration of a typical conventional two-port RAM 1 (hereinafter referred to as a "first conventional example").

The addresses ADRA and ADRB sent to the ports 12 and 13 are respectively stored in the address buffers 128.
Alternatively, the data is input to the memory cell array 11 via the address buffer 138. The memory cell array 11 decodes these addresses to select a memory cell. The control signal comprises a write enable signal WEA bar, a WEB bar, an output enable signal OEA bar, an OEB bar, and a chip enable signal CEA bar, CEB bar for controlling writing or reading, controlling data output and selecting a chip. Are input to the I / O control circuit 14 via the control signal buffer 127 or the control signal buffer 137, respectively. The data DQA and DQB are supplied to the I / O control circuit 14.
And input / output to / from the memory cell array 11 through the memory.

Addresses ADRA and A which are input via the address buffer 128 and the address buffer 138
The DRBs are also sent to the conflict generation circuit 15, respectively. The conflict generation circuit 15
This circuit checks whether the address ADRA and the address ADRB conflict with each other, and outputs conflict signals CONFLA and CONFLB (busy signals) which become high level from the ports 12 and 13 when these conflict. The conflict between the addresses ADRA and ADRB can be considered not only when the addresses ADRA and ADRB completely match and the corresponding memory cells become the same, but also when the corresponding separate memory cells cannot be simultaneously accessed due to the memory configuration. However, in the following description, the addresses ADRA, A
It is assumed that a conflict occurs only when the DRBs match. Also,
Similarly, in the following description, for simplicity, the access is shown only in the case of a write access, and it is necessary to always stop this access if addresses ADRA and ADRB conflict.

The operation of the two-port RAM 1 of the first conventional example in the case where there are simultaneous write accesses to consecutive addresses of N, N + 1, N + 2,... Will be described with reference to FIG. However, here, it is assumed that the access cycles of the ports 12 and 13 are completely synchronized, and the access from the A port 12 has priority in the event of contention. Accordingly, the access from the A port 12 does not need to be stopped due to contention, and the conflict signal CONFLA output from the A port 12 is ignored. The chip enable signal CEA sent to the A port 12 is always at the low level (selected) in the cycle shown in FIG.

First, in the T1 cycle, the address ADR
Since both A and ADRB are N, a conflict occurs, and the conflict generation circuit 15 sets the conflict signal CONFLB to a high level (conflict). Thus, the access on the A port 12 side is executed, but the access on the B port 13 side is stopped. At this time, DN is input to the B port 13 as write data DQB, and the write enable signal WEB goes low (write), but these are ignored.

Next, in the T2 cycle, the access is executed by changing the address ADRA of the A port 12 to N + 1. However, on the B port 13 side, the CPU 3 shown in FIG.
The B bar is set to a high level (not selected) to check the conflict signal CONFLB to detect that the access has failed.

In the T3 cycle, the B port 13
Since the CPU 3 on the side detects that the access has failed in the T2 cycle, the same access as in the T1 cycle is repeated again. Then, the address ADRA of the A port 12 this time is N + 2, and the conflict generation circuit 1
5 sets the conflict signal CONFLB to low level (non-contention), so that accesses from the ports 12 and 13 are executed simultaneously.

In the T4 cycle, the access is executed by changing the address ADRA of the A port 12 to N + 3. However, on the B port 13 side, the CPU 3 checks the conflict signal CONFLB in the same manner as in the T2 cycle, detects that the CPU 3 has succeeded in accessing, and then sends out the next N + 1 address ADRB in the T5 cycle. Then, in the same manner, from the A port 12, every cycle, unless a conflict occurs again,
Access is performed sequentially from the B port 13 every other cycle.

As described above, in the first conventional example, the CPU 3 on the side of the B port 13 having a low priority performs the access while checking the conflict signal CONFLB every other cycle to check whether the access was successful.
If it is detected that a conflict has occurred and the access has failed, the same address ADRB is transmitted again. If the cycles of both accesses are not synchronized, accesses performed from the A port 12 during access on the B port 13 may conflict with each other. At this time, the access on the A port 12 side must be stopped, and the CPU is controlled based on the conflict signal CONFLA.
2 needs to perform the same control. For such a case, the conflict generation circuit 15 outputs the conflict signals CONFLA, COFL on the side that stops the access.
Only NFLB is set to high level (competition).

FIGS. 8 and 9 show another conventional two-port RAM.
1 (hereinafter referred to as “second conventional example”).

This two-port RAM 1 uses one cycle for two
A dedicated access time zone for the A port 12 and the B port 13 is provided in a time-division manner. That is, FIG.
In the first half of each cycle T1, T2, T3,..., The chip enable signal CEA bar of the A port 12 is set to low level (selection) to access by the address ADRA. Thirteen chip enable signals CEB bar are set to the low level (selected) to perform access by the address ADRB. Therefore, even if both ports 12 and 13 perform write access to the same address in the same cycle, they do not conflict with each other. Therefore, as shown in FIG. 8, the conflict generation circuit shown in the first conventional example is used. 15 becomes unnecessary, and the control of the busy wait method by the conflict signal CONFL becomes unnecessary.

The adjustment of the dedicated access time zone is controlled on the two-port RAM 1 or on a system including two CPUs 2 and 3 accessing the two-port RAM 1.

[0016]

However, in the case of the above-mentioned first conventional example, a CP having a low priority on the B port 13 side is used.
U3 outputs the conflict signal CONFL every other cycle.
Since access must proceed while checking B, it takes two cycles even if no contention occurs even though one cycle is originally required to perform one access. Requires four cycles, which causes a problem that the data transfer speed is reduced. In addition, when a conflict occurs and the access fails, the CPU 3 needs to send out the same address ADRB, data DQB, and the like again, thus causing a problem that the control in the CPU 3 becomes complicated.

Further, in the case of the second conventional example, originally 2
Since the period of one access is one cycle, the data transfer time is always required to be twice as long as usual, and the system is designed so that both CPUs 2 and 3 access in their dedicated access time zones. It is necessary to synchronize them or to delay and adjust the signals in the two-port RAM 1, which impairs the degree of freedom of the system or causes a variation in the access completion time, and
There is a problem that the processing in U becomes complicated.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a multi-port semiconductor memory device which uses a queue to facilitate the processing of contention by a busy weight system.

[0019]

A multiport semiconductor memory device according to the present invention has a plurality of input / output ports for accessing a memory cell, and accesses an address or the like sent to each input / output port. in multi-port semiconductor memory device information is provided for determining conflict detection means whether or not these should be discontinued access by competition, address
And control signals and write access
A queuing means for accepting the access information such as the write data queue provided on each of the input and output ports of each input and output ports, the first A of the queue
If the dress is not determined access aborted by conflict detection means, a non-competitive time control means for performing access removed by selecting from the queue to the beginning of the access information of the queues for each input and output ports, If the first address of the queue is determined to access aborted by conflict detection means and stops the access by the top accession <br/> Seth information of the queues, it outputs a busy signal from the output port And a conflict control means for causing the above-mentioned object to be achieved.

Further, the multiport semiconductor memory device of the present invention has a plurality of input / output ports for accessing memory cells, and access information such as addresses sent to each of the input / output ports may conflict with each other. In a multiport semiconductor memory device provided with conflict detection means for determining whether access should be stopped, the access information is set to 1
A two-stage shift register to be stored in the second-stage register is provided for each input / output port, and for each I / O port, when the previous cycle has stopped access, the second-stage shift register is accessed. If the access is not suspended, a register switching means using the first stage of the shift register as an access register, and for each input / output port, the first stage of the shift register is an access register. When the access information in the access register is not judged by the conflict detection means to stop the access, a normal control means for executing the access based on the access information, and for each input / output port, the first stage of the shift register is an access register. And the access information in the access register is used as a conflict detection method. If it is determined to access aborted, the stopping access by the access information, to output a busy signal from the input port by,
And a conflict occurrence control means for shifting the shift register to shift the access information from the first stage to the second stage;
The second row is an access register, and when the access information of the access register is determined to stop the access by the conflict detection means, the access by the access information is stopped and the busy signal is output from the input / output port. The continuation control means and, for each input / output port, when the second stage of the shift register is an access register, and the access information of this access register is not judged to be canceled by the conflict detection means, the access information And a contention release control means for executing an access by means of the above, thereby achieving the above object.

Further, in addition to the above configuration, the multiport semiconductor memory device of the present invention has two input / output ports for accessing the memory cell, thereby achieving the above object.

[0022]

With the above arrangement, the conflict detecting means detects an address or a control signal in the access information and detects a conflict as appropriate based on whether or not mutual exclusion is to be performed according to the configuration of the memory cell or the like. And 2
If it is detected that two or more pieces of access information conflict with each other, for each applicable I / O port, whether the I / O port should suspend access due to contention based on the access destination, priority, etc. Determine whether The access information includes address and control signals, write data in the case of write access, and the like.

The queuing means constitutes a queuing (queue) with an array, a shift register, and the like, and controls input / output of this queuing by a FIFO [First-In First-Out] method. That is, the queuing means
The access information is arranged in the order of reception in the queue, and the oldest received access information is always located at the head except for the already extracted access information, and is read (referenced).
And be targeted for removal.

If the access information at the head of the queue at each input / output port does not determine that the access has been stopped by the conflict detection means, the non-contention control means causes the memory cell to be accessed. When the access information is judged to be canceled by the conflict detection means, the conflict control means stops the access,
A busy signal is output from the input / output port. When the busy signal is output, the processing device that accesses from the input / output port detects this in the next cycle, and stops sending access information in the next cycle (for example, when the chip enable signal is deactivated). Control). The queue means does not accept the access information when the transmission of the access information is stopped. Therefore, when the access is stopped by the conflict control means, the addition of the access information to the queue is stopped after two cycles, and even when the access is stopped, the addition of the access information is stopped for the same period. Since the access is resumed at the last cycle in which the addition of the access information is stopped, the access information held in the queue is at most two cycles. The access information to be read out for checking for conflicts and the address information to be taken out when performing an access are those at the head of this queue, and in which cycle this is accepted is determined by the previous cycle. Depends on whether or not the access was suspended.

As a result, according to the present invention, the suspension of the transmission of the access information in the event of contention is postponed until the next cycle, so that the transmission of the access information and the inspection of the busy signal can be performed simultaneously for each cycle. Thus, it is not necessary to uselessly use cycles only for the inspection of the busy signal in the busy weight system. Also, since the access information is not retransmitted even when a conflict occurs, the cycle for retransmission is not wasted, and the access control on the processing device side can be simplified.

According to a second aspect of the present invention, the queuing means of the first aspect is realized by operating the shift register by the register switching means and the shift operation in the conflict occurrence control means. Then, the register switching means includes:
By switching between the first stage and the second stage of the shift register, the head of the queue is always indicated by the access register. It corresponds to the conflict control means. Further, the shift operation of the shift register in the conflict occurrence control means is merely an operation of opening the first stage to accept the next access information while retaining the previous access information, and thus the conflict operation with the conflict occurrence control means is not performed. Both the continuous control means correspond to the conflict control means of claim 1.

The shift operation of the shift register in the conflict occurrence control means is normally performed at the beginning of the next cycle, so that the next access information is stored in the first stage at the same time. In addition, this shift register generally performs a shift operation only to store access information in the first stage, except in the case of the conflict occurrence control means. In this case, the shift register shifts from the first stage to the second stage. Since the shifted access information is meaningless, the shift operation is not necessarily required if there is another means for forcibly storing the access information in the first-stage register.

According to a third aspect of the present invention, the present invention is applied to a multiport semiconductor memory device having two input / output ports, such as a two-port RAM.

[0029]

Embodiments of the present invention will be described below.

1 to 4 show an embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a two-port RAM, FIG. 2 is a state transition diagram showing a control operation of the two-port RAM, FIG. 3 shows a two-port RA when a conflict occurs only once.
FIG. 4 is a time chart showing the operation of the two-port RAM when a conflict frequently occurs. Note that the same reference numerals are given to constituent members having functions similar to those of the above-described conventional example.

In this embodiment, the two-port R shown in FIG.
A case where the present invention is applied to AM1 will be described. In this embodiment, as in the first conventional example, CPUs 2 and 3 are used.
The case where the access from the CPU 2 is synchronized and the access from the CPU 2 is prioritized will be described.

As shown in FIG. 1, the two-port RAM 1
Memory cell array 11, A port 12, B port 13,
It comprises an I / O control circuit 14 and a conflict generation circuit 15. Among them, the memory cell array 11, the I / O control circuit 14, and the conflict generation circuit 15 are the same as those in the conventional example shown in FIG. The conflict signals CONFLA and CONFLB output from the conflict generating circuit 15 are output via the A port 12 or the B port 13, respectively.

The A port 12 has three shift registers 1
21 to 123 and three multiplexers 124 to 126. Each of the shift registers 121 to 123 is a shift register in which a multi-bit register is provided in two stages. The A port 12 is connected to the address bus, control bus, and data bus of the CPU 2 shown in FIG. 5, and the address ADRA and the control signals WEA bar, OEA bar,
The CEA bar is sent in, and data DQA can be input and output. That is, the address ADRA of a plurality of bits is input to each bit of the first stage of the shift register 121. Multiplexer 12
A circuit 4 selects one of the addresses ADRA stored in both stages of the shift register 121 and sends the selected address to the memory cell array 11 and the conflict generation circuit 15. The 3-bit control signals WEA bar, OEA bar, and CEA bar are input to each bit of the first stage of the shift register 122. The multiplexer 125 selects one of the sets of the control signals WEA bar, OEA bar, and CEA bar stored in both stages of the shift register 122 and selects the I / O control circuit 14
It is a circuit to send to. Furthermore, a plurality of bits of data DQA
Is input to each bit of the first stage of the shift register 123. However, this shift register 1
The first stage register 23 has a configuration in which input and output can be performed in both directions.
A can also be output to the data bus. The multiplexer 126 is a circuit that selects one of the data DQA stored in both stages of the shift register 123 and sends it to the I / O control circuit 14. The multiplexer 126 can also store the data DQA sent from the I / O control circuit 14 in the first stage of the shift register 123.

The B port 13 also has three shift registers 1
31 to 133 and three multiplexers 134 to 136, which are shift registers 121 to 123 and multiplexers 124 to 126 of the A port 12, respectively.
It has the same configuration as. However, the address bus of the CPU 3 shown in FIG.
The address ADRB is input. The control bus of the CPU 3 is connected to the shift register 132, and the control signals WEB bar, OEB
The bar and the CEB bar are input. Further, a data bus of the CPU 3 is connected to the shift register 133 so that data DQB can be input and output. The CPU 3 includes a conflict generation circuit 15
, A conflict signal CONFLB output via the B port 13 is also sent.

The multiplexers 124 to 126, 13
4 to 136 are the shift registers 121 to 123 and 131 to 1 when the conflict generation circuit 15 has not detected the conflict in the initial state and the previous cycle.
33, the access information stored in the first row is selected to perform input / output, and if a conflict is detected, the access information stored in the second row is selected to perform input / output. ing. Further, each of the shift registers 121 to 123, 1
31 to 133 are chip enable signals CEA in the control signals sent to the ports 12 and 13.
The shift operation is performed when the bar and the CEB bar are at the low level (selection), and the access information is stored (latched) in the first stage. The CPU 3 outputs the conflict signal C
When ONFLB becomes a high level (contention), this is detected in the next cycle, and the chip enable signal CE in the next cycle is accessed even when accessing is performed subsequently.
The control is set so that the B bar is set to the high level (not selected) and the access is delayed by one cycle. In this embodiment, since the access from the A port 12 is prioritized, the conflict signal CONFLA does not become a high level (contention), and the CPU 2 always performs a normal access. For this reason, the multiplexers 124 to 126 on the side of the A port 12 always keep the shift registers 12
The access information stored in the first row of 1 to 123 is selected and input / output is performed.

The configuration of the control unit of the two-port RAM 1 will be described with reference to FIG.

[0037]

[Table 1]

The control unit of the two-port RAM 1 executes control based on transitions of four internal states including a normal cycle a, a conflict occurrence cycle b, a conflict continuation cycle c, and a conflict release cycle d.

(1) Normal cycle a (normal control means) In the normal cycle a, the multiplexer 1 of the B port 13
34 to 136 read the access information stored in the first stage of the shift registers 131 to 133. Access to the memory cell array 11 is executed based on the first-stage access information of the shift registers 131 to 133. The transition to the normal cycle a becomes possible from the initial state or when the conflict signal CONFLB is at a low level (non-conflict) in the previous cycle, that is, after the same normal cycle a (a → a) or after. Only from the conflict release cycle d (d → a) described. Also, the transition actually occurs only when the conflict signal CONFLB is at the low level (non-contention) in the current cycle. When transitioning from the normal cycle a to the next state, the shift registers 131 to 133
Performs a shift operation, and new access information is stored in the first row. At this time, the access information that was in the first stage is shifted to the second stage, but this is meaningless already accessed and is substantially extracted here.

(2) Conflict occurrence cycle b (control means when conflict occurs) In the conflict occurrence cycle b, the multiplexers 134 to 136 of the B port 13 shift the shift registers 131 to 1
The access information stored in the first row of 33 is read. Further, access to the memory cell array 11 from the B port 13 side is stopped. This conflict generation cycle b
Can be changed when the conflict signal CONFLB is at the low level (non-conflict) in the previous cycle, that is, the normal cycle a (a → b) or the conflict release cycle d (d → b) described later. Only from. Also, the transition actually occurs only when the conflict signal CONFLB is at the high level (contention) in the current cycle. Thus, the conflict signal CO
When NFLB goes high (conflict), the CPU 3
This is detected in the next cycle, and the transmission of address information is stopped in the next cycle. When transitioning from the conflict occurrence cycle b to the next state, the shift register 1
31 to 133 perform a shift operation to move the first-stage access information to the second stage, and store new access information in the first empty stage. It is only in this case that the access information that has not been accessed is moved from the first stage to the second stage. In other shift operations, the access information has been accessed and the invalid access information that has been substantially taken out is invalid. The shift operation is performed only to store new access information in the first stage, just to move.

(3) Conflict continuation cycle c (control means during contention continuation) In the conflict continuation cycle c, the multiplexers 134 to 136 of the B port 13 shift the shift registers 131 to 136.
The access information stored in the second row of 33 is read. Further, access to the memory cell array 11 from the B port 13 side is stopped. This conflict continuation cycle c
Is possible when the conflict signal CONFLB is at the high level (contention) in the previous cycle, that is, from the conflict occurrence cycle b (b → c) or the same conflict continuation cycle c (c → c). Only in cases. Also, the transition actually occurs only when the conflict signal CONFLB is at the high level (contention) in the current cycle. Also in this case, the conflict signal CONFLB becomes high level (competition).
No. 3 detects this in the next cycle and stops sending address information in the next cycle. At the time of transition from the conflict continuation cycle c to the next state, the CPU 3 is canceled due to the stop of the access two times before (the previous time when viewed from the current state).
Stops transmission of access information, so that the shift registers 131 to 133 do not perform a shift operation.

(4) Conflict Release Cycle d (Control Unit for Resolving Conflict) In the conflict release cycle d, the multiplexers 134 to 136 of the B port 13 shift the shift registers 131 to 136.
The access information stored in the second row of 33 is read. Access to the memory cell array 11 is performed based on the second-stage access information of the shift registers 131 to 133. The transition to the conflict release cycle d is enabled when the conflict signal CONFLB is at the high level (contention) in the previous cycle, that is, the conflict generation cycle b (b → d) or the conflict continuation cycle c (c → c). Only from d). Also, in the current cycle, the conflict signal C
A transition actually occurs only when ONFLB is at a low level (non-contention). When transitioning from the conflict release cycle d to the next state, the CPU 3 stops sending access information due to the stop of access two times before (previous when viewed from the current state).
No. 3 performs no shift operation.

In the two-port RAM 1 having the above configuration, A
The same N, N + 1, N + 2 for port 12 and B port 13
The operation in the case where there is a write access to consecutive addresses of... Will be described with reference to FIG.

First, in the T1 cycle, the chip enable signal CEB from the CPU 3 goes low (selected).
Therefore, the shift registers 131 to 133 perform the shift operation and store N of the address ADRB in the first stage. Here, assuming that no conflict has occurred in the previous cycle, the multiplexer 134 reads N of the address ADRB of the first stage, so that it matches N of the address ADRA, and the conflict generation circuit 15 outputs the conflict signal C
ONFLB is set to a high level (competition). Therefore, the control state of this T1 cycle is the conflict generation cycle b
Therefore, the access from the B port 13 is stopped.

Next, also in the T2 cycle, since the chip enable signal CEB goes low (selected), the shift registers 131 to 133 perform a shift operation and move N of the address ADRB in the first stage to the second stage. At the same time, N + 1 of the new address ADRB is stored in the first row.
Also, since a conflict occurred in the previous T1 cycle, the multiplexer 134 outputs the shifted address A of the second stage.
Read N of DRB. However, the address ADRA is N +
Therefore, the conflict signal CONFLB becomes low level (non-contention). Therefore, the control state of this T2 cycle is the conflict release cycle d,
Access is made from the port 13 based on N of the address ADRB in the second stage, DN of the data DQB for writing, and the like. At this time, the first stage of the shift register 133 stores DN + 1 of the write data DQB. Note that C
The PU3 detects the high level (contention) of the conflict signal CONFLB in the T2 cycle, and sets the internal conflict flag to the high level.

In the cycle T3, the CPU 3 stops transmitting the access information based on the conflict flag which has become high level in the cycle T2, and sets the chip enable signal CEB.
Since the bar is set to the high level (not selected), the shift registers 131 to 133 do not perform the shift operation. However, since no conflict occurred in the previous T2 cycle, the multiplexer 134 reads N + 1 of the address ADRB stored in the first stage. And the address ADRA
Changes to N + 2, the conflict signal CONFLB
Becomes low level (non-competition). Accordingly, since the control state of the T3 cycle is the normal cycle a, access is performed from the B port 13 based on N + 1 of the first-stage address ADRB, DN + 1 of the write data DQB, and the like.

In the cycle T4, the chip enable signal CEB goes back to the low level (selected), so that the shift registers 131 to 133 perform the shift operation and the address A
N + 2 of DRB is stored in the first row. Since no conflict has occurred in the previous T3 cycle, the multiplexer 134 reads N + 2 of the address ADRB in the first stage. Then, since the address ADRA changes to N + 3, the conflict signal CONFLB becomes low level (non-contention). Therefore, since the control state of the T4 cycle is also the normal cycle a, the B port 13 outputs N + 2 of the address ADRB of the first stage and the data DQB for writing.
, And access is performed simultaneously from the A port 12 and the B port 13 in the subsequent cycles.

As described above, in the two-port RAM 1 of this embodiment, not only the CPU 2 of the A port 12 having the higher priority but also the CPU 3 of the B port 13 having the lower priority check and access the conflict signal CONFLB in each cycle. Can be performed simultaneously, so that the data transfer speed can be improved. Further, even when a conflict occurs, the CPU 3 stops sending the access information in the T3 cycle two cycles after the occurrence of the conflict and delays the access information by one cycle, thereby continuously transmitting the access information without retransmitting the access information. Access to continue.

In the two-port RAM 1, the B port 13 has write access to consecutive addresses of N, N + 1, N + 2,..., And the A port 12 has N, N,
The operation when there is a write access in which the same address is repeated twice at the beginning, such as N + 1, N + 1, N + 2, N + 3,..., Will be described with reference to FIG.

First, in the T1 cycle, as in the T1 cycle of FIG. 3, the addresses ADRA and ADRB both become N and a conflict occurs, and the control state becomes the conflict occurrence cycle b. Is aborted. Next, even in the T2 cycle, the address ADR is again
Since A and ADRB both become N and a conflict occurs, and the control state becomes the conflict continuation cycle c, the B port 13
Access from the side is stopped.

In the subsequent T3 and T4 cycles, the CPU 3 stops sending access information and sets the chip enable signal CEB to a high level (non-selected) due to the previous two conflicts. T2
The access information sent in the cycle continues to be held in the two-stage shift registers 131 to 133. Also, this T
In three cycles, the multiplexer 134 reads N of the address ADRB from the second stage of the shift register 131, whereas the address ADRA on the A port 12 side is N + 1.
Therefore, the conflict is resolved and the control state transits to the conflict release cycle d, and the access by the address ADRB by N is executed. However, in the T4 cycle, N + 1 of the address ADRB read from the first stage by the multiplexer 134 is the address AD of the A port 12 side.
After competing with N + 1 of RA, the control state returns to the conflict occurrence cycle b again.

However, in the T5 cycle, the multiplexer 134 reads N + 1 of the address ADRB from the second stage of the shift register 131, whereas the address ADRA on the A port 12 side is N + 2. Transitions to the conflict release cycle d, and the access by the address ADRB by N + 1 is executed. Then, in the T6 cycle, the multiplexer 134 outputs the address A from the first stage of the shift register 131.
Since the address ADRA on the A port 12 side is N + 3 while reading N + 2 of DRB, the control state transits to the normal cycle a without any conflict here, and the A port 12 And B port 13
Access is executed simultaneously from.

As a result, when conflicts occur successively or when the control state is in the conflict resolving cycle d while the conflicts are being resolved.
In the case where the conflict occurs again, the two-port RAM 1 of this embodiment causes the CPU 3 to stop sending the access information in the T3 cycle, T4 cycle and T6 cycle two cycles after the conflict occurs. Only by this, it was confirmed that access could be continued normally.

Here, the data transfer time of the two-port RAM 1 of this embodiment, the first conventional example, and the second conventional example will be compared. The setting conditions for this comparison are as follows: T is the cycle time of the two-port RAM1.

The number of data transfers is 1,000.

Assume that the number of times of occurrence of competition is 50 times.

The average overhead per cycle for synchronization in the two-port RAM 1 of the second conventional example is α.

The following results were obtained when the calculation was performed.

This embodiment: (1000 + 50) T = 1
050T ・ First conventional example: (1000-50) × 2T + 50 × 4T
= 2100T ・ Second conventional example: 1000 × (2T + α) = 2000T +
1000α As a result, it was found that the present embodiment can reduce the data transfer time to half or less as compared with the first conventional example and the second conventional example.

In this embodiment, the access conflict is determined only based on whether or not the addresses match. However, the present invention is not limited to this. The address, the write enable signal, and the like are appropriately determined in accordance with the structure of the memory cell array 11 by inspection. can do. Further, in the present embodiment, the accesses of the CPUs 2 and 3 are synchronized. However, if they are not synchronized, the access from the CPU 2 may conflict and be eliminated during the access of the CPU 3. . However, also in this case, the same processing as described above is performed on the A port 12 side using the shift registers 121 to 123 and the multiplexers 124 to 126, and the conflict signal C
The CPU 2 performs the same processing as the CPU 3 based on ONFLA, thereby realizing mutual exclusion based on the present invention.

[0061]

As is apparent from the above description, according to the multiport semiconductor memory device of the present invention, the processing device accessing the memory cell can check the busy signal and retransmit the access information. Since the cycle is not wasted, the data transfer efficiency can be improved. Further, by eliminating the need to retransmit the access information, access control on the processing device side can be simplified.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a configuration of a two-port RAM.

FIG. 2, showing an embodiment of the present invention, is a state transition diagram illustrating a control operation of a two-port RAM.

FIG. 3, showing an embodiment of the present invention, is a time chart illustrating an operation of the two-port RAM when a conflict occurs only once.

FIG. 4, showing an embodiment of the present invention, is a time chart illustrating an operation of a two-port RAM when contention frequently occurs.

FIG. 5 is a block diagram showing a configuration when a two-port RAM is used as a shared memory between two CPUs.

FIG. 6 shows a first conventional example, in which a two-port RA is used.
FIG. 3 is a block diagram showing a configuration of M.

FIG. 7 shows a first conventional example, in which a two-port RA is used.
6 is a time chart showing the operation of M.

FIG. 8 shows a second conventional example, in which a two-port RA is used.
FIG. 3 is a block diagram showing a configuration of M.

FIG. 9 shows a second conventional example, in which a two-port RA is used.
6 is a time chart showing the operation of M.

[Explanation of symbols]

 1 2-port RAM 11 Memory cell array 12 A port 13 B port 15 Conflict generation circuit 121-123 Shift register 131-133 Shift register 124-126 Multiplexer 134-136 Multiplexer

Claims (3)

(57) [Claims] An input / output port having a plurality of systems for accessing a memory cell, and whether or not access information such as an address sent to each input / output port should interrupt access due to contention. An address and control signal and a write access in a multiport semiconductor memory device having a conflict detecting means for determining
And a queuing means for receiving access information such as write data in a queue provided for each input / output port, and for each input / output port, an address at the head of the queue.
If the scan is not determined access aborted by conflict detection means, a non-competitive time control means for performing access removed by selecting from the queue to the beginning of the access information of the queues for each input and output ports, Address at the head of the queue
And a contention control means for stopping access by the access information at the head of the queue and outputting a busy signal from the input / output port when the access detection is determined by the contention detection means. Semiconductor storage device. 2. It has a plurality of input / output ports for accessing a memory cell, and determines whether or not access information such as an address sent to each input / output port should interrupt access due to contention. In a multi-port semiconductor memory device provided with a conflict detection means for determining, a two-stage shift register for storing access information in a first-stage register is provided for each input / output port. A register switching means for setting the second stage of the shift register as an access register when the cycle is the access stop, and setting the first stage of the shift register as the access register when the access is not stopped; Regarding the output port, the first stage of the shift register is an access register, and this access register If the conflict detection means does not judge the access stop of the access information, the normal control means for executing the access based on the access information, and for each input / output port, the first stage of the shift register is an access register. If the access information in the access register is determined to be interrupted by the conflict detection means, the access based on the access information is stopped, a busy signal is output from the input / output port, and the shift register is shifted. Contention control means for shifting the access information from the first stage to the second stage, and for each input / output port, the second stage of the shift register is an access register, and the access information of the access register is in conflict. If the detection means determines that access is Contention continuation control means for stopping access by access information and outputting a busy signal from the input / output port; and for each input / output port, the second stage of the shift register is an access register. A multiport semiconductor memory device comprising: a conflict release control means for executing an access based on the access information when the access information is not judged to be canceled by the conflict detection means. 3. The multiport semiconductor memory device according to claim 1, wherein there are two input / output ports for accessing the memory cells.