JP3193817B2 - Pattern generator for IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for inspecting the electrical characteristics of an IC (integrated circuit), and more particularly, to an IC test apparatus for generating an expected value of a device under test. The present invention relates to a pattern generator of an IC test apparatus capable of performing simple and high-speed data writing and reading.

[0002]

2. Description of the Related Art In order to ship an IC whose performance and quality are guaranteed as a final product, it is necessary to extract all or a part of the IC product in each process of a manufacturing department and an inspection department and to inspect its electrical characteristics. There is. An IC test device is a device for inspecting such electrical characteristics. The IC test apparatus supplies predetermined test pattern data to the device under test, reads the output data of the device under test, and compares and determines the output data of the device under test with an expected value. We analyze whether there is any problem in the dynamic operation and function.

[0003] DC tests (D
C measurement test) and a function test (FC measurement test). In the DC test, a predetermined voltage or current is applied from the DC measuring means to the input / output terminal of the device under test to check whether there is any defect in the basic operation of the device under test. On the other hand, in the function test, predetermined test pattern data is given from the pattern generator to the input terminal of the device under test, and the output data of the device under test is read, and whether there is no problem in the basic operation and function of the device under test Is to be inspected.

FIG. 6 is a block diagram showing a schematic configuration of a conventional IC test apparatus. The IC test equipment consists of a tester 70 and an I
C mounting device 7D. The tester unit 70 includes the control unit 7
1. DC measuring means 72, timing generating means 73, pattern generating means 74, pin controlling means 75, pin electronics 76, and fail memory 77. There are various other components in the actual tester unit 70, but only necessary parts are shown in this specification.

The tester section 70 and the IC mounting device 7D are connected by signal lines including a plurality of (m) coaxial cables or the like corresponding to the total number m of input / output terminals of the IC mounting device 7D. The connection relationship between them is associated by a relay matrix (not shown), and transmission of various signals is performed between predetermined terminals. This signal line is physically connected to the IC mounting device 7D.
Of the same number as the total number m of input / output terminals.

The IC mounting device 7D is configured so that a plurality of devices under test 7E can be mounted on a socket. Input / output terminals of device under test 7E and IC mounting device 7
The input / output terminals of D are connected in one-to-one correspondence. For example, in the case of an IC mounting device 7D capable of mounting 10 devices under test 7E having 28 input / output terminals, the device has 280 input / output terminals in total.

The control means 71 controls the entire IC test apparatus,
It performs operations and management, and has a microprocessor configuration. Therefore, although not shown, the control means 71 has a ROM for storing a system program, a RAM for storing various data, and the like. The control means 71
DC measuring means 72, timing generating means 73, pattern generating means 74, pin control means 75, and fail memory 7
7 is connected via a tester bus (data bus, address bus, control bus) 7C.

[0008] The control means 71 converts the data for DC test into D
The timing data for starting the function test is output to the timing generating means 73, and the program and various data necessary for generating the test pattern are output to the C measuring means 72 and the pattern generating means 74. Control means 7
Numeral 1 outputs various data to respective components via a tester bus 7C. Further, the control unit 71 reads out the test results (fail data and DC data) from the fail memory 77 and the DC measurement unit 72, performs various data processing and the like, and analyzes the test data.

The DC measuring means 72 receives the DC test data from the control means 71 and performs a DC test on the device under test 7E of the IC mounting device 7D based on the data.
The DC measurement means 72 starts a DC test by inputting a measurement start signal from the control means 71, and writes data indicating the test result to a register. When the writing of the test result data is completed, the DC measurement means 72 outputs an end signal to the control means 71. The test result data written in the register in the DC measuring means 72 is read by the control means 71 via the tester bus 7C and analyzed there. Thus, the DC test is performed. Also, the DC measuring means 72
Are the reference voltages VIH, VIL, VO for the driver 7A and the comparator 7B of the pin electronics 76.
H and VOL are output.

The timing generating means 73 includes a control means 71
Is stored in an internal memory, and a high-speed operation clock φ is output to the pattern generation means 74 and the pin control means 75 based on the timing data. Therefore, the operation speed of the pattern generation means 74 and the pin control means 75 is determined by the operation clock φ from the timing generation means 73. Further, the timing generating means 73 receives the timing switching control data CH from the pattern generating means 74, and is capable of appropriately switching the operation cycle, phase, and the like based on the control data CH.
H is output to the pin control means 75 and the fail memory 77.

The pattern generating means 74 has a program system for generating regular test pattern data by various arithmetic processes according to the microprogram, and stores the same data as the device under test in an internal memory (hereinafter referred to as a pattern memory). Write it and read it at the same address as the device under test, so that it is irregular (random)
It operates in a memory-stored manner that generates a simple pattern (expected value data). In the programming method, the device to be measured is R
It corresponds to the case of a volatile memory such as an AM (Random Access Memory), and the memory stored method corresponds to the case of a nonvolatile memory such as a ROM (Read Only Memory). Note that, even in the case of the memory stored method, the generation of the address supplied to the device to be measured is performed by the program method.

The pin control means 75 comprises a formatter 78 and a comparator logic circuit 79. The formatter 78 has a flip-flop circuit and a logic circuit formed in multiple stages, and variously processes the test pattern data from the pattern generating means 74 to synchronize a predetermined applied waveform with the timing signal PH from the timing generating means 73. To the driver 7A of the pin electronics 76. The comparator logic circuit 79 includes the comparator 7
The measured data P3 from B is compared with the expected value data P4 from the pattern generating means 74, and the result of the comparison is output to the fail memory 77 as fail data FD.

The pin electronics 76 comprises a plurality of drivers 7A and comparators 7B. One driver 7A and one comparator 7B are provided for each input / output terminal of the IC mounting device 7D, and are connected via signal lines. That is, when the number of input / output terminals of the IC mounting device 7D is m, the number of the drivers 7A and the number of comparators 7B are each m. However, when measuring a memory IC or the like, the number of comparators may be small because no comparator is required for the address terminal.

The driver 7A responds to the test pattern data P1 from the formatter 78 of the pin control means 75,
A test signal is applied to input / output terminals of the IC mounting device 7D, that is, signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal of the device under test 7E, and desired data is transmitted to the device under test 7E. Write.

The comparator 7B receives data output from a signal output terminal such as a data output terminal of the device under test 7E and compares it with reference voltages VOH and VOL at the timing of a strobe signal from the control means 71. The comparison result (high level “1” or low level “0”) is output to the comparator logic circuit 79 as the measured data P3.

The fail memory 77 stores the fail data FD output from the comparator logic circuit 79, and is constituted by a RAM which has a storage capacity similar to that of the device under test 7E and which can be read and written at any time. The fail memory 77 has a data input / output terminal fixedly corresponding to the data output terminal of the IC mounting device 7D.

For example, when the total number of input / output terminals of the IC mounting device 7D is 280 and 179 of them are data output terminals, the fail memory 77 is equal to or smaller than the number of data output terminals. It is composed of a memory having the above data input terminals. The fail data FD stored in the fail memory 77 is read by the control means 71, transferred to a data processing memory (not shown), and analyzed. The function test is performed in this manner.

[0018]

The IC test apparatus is composed of hardware for performing data processing at about several tens of MHz. The IC test apparatus uses an operation clock (system clock) from the timing generation means 73 by using a pipeline method in many cases. ) A clock machine that operates at high speed based on φ. That is, the IC test apparatus sets the operating conditions of each unit through the tester bus 7C, writes desired pattern data in the pattern memory in the pattern generating unit 74, and then starts the timing generating unit 73. Over
The high-speed operation clock φ is output to the pattern generation means 74 and the pin control means 75, and these are operated at a high speed of about several tens of MHz.

The pattern generating means 74 generates test pattern data at a high speed of about several tens of MHz by using a part of the test pattern data as a read address of the pattern memory since the test pattern data is generated by a program method. be able to. Since the pattern generation means 74 adopts a memory stored method in which the expected value data previously stored in the pattern memory is read out at high speed in accordance with the read address as described above, the pattern generation means 74 An address bus (tester bus) for transferring a write address when writing value data and an address bus (high-speed bus) for transferring a read address when reading expected value data from the pattern memory are mixed.
It consists of a system bus.

FIG. 7 is a diagram showing details of a pattern generating means composed of two buses for generating expected value data by such a memory stored method. In the figure, the pattern memory is composed of two pattern memories 8A and 8B capable of accessing two types of memory, a two-way interleave access method and a non-interleave access method.

The flip-flop circuits 81, 86, 87,
8C, 8D and 8F operate in accordance with the operation clock φ from the timing generation means 73, and are flip-flop circuits for pipeline processing. These flip-flop circuits 81, 86, 87, 8C, 8D and 8
F starts its operation only when the operation clock φ is inputted after the timing generation means 73 is started, and therefore the read addresses RAD are stored in the pattern memories 8A and 8B.
It takes several cycles for the number of clocks to arrive, and is basically incompatible with a tester bus having no pipeline configuration.

Therefore, conventionally, a multiplexer (MU) is provided before the address shifter 83 and the pattern memories 8A and 8B.
X) 82, 88 and 89 are provided, and by switching these, test pattern data can be written in one cycle of the tester bus 7C. Note that MUX
Reference numerals 82, 88 and 89 allow the control means 71 to select and set the connection state. Therefore, MUX8
When the upper input terminals 2, 88 and 89 are selected, the bus becomes a high-speed bus, and high-speed reading processing of test pattern data is performed. Conversely, when the lower input terminal is selected, the bus becomes a tester bus. Write processing of expected value data and the like is performed.

First, the operation of each unit when the lower input terminals of the MUXs 82, 88 and 89 are selected and the test pattern data is written into the pattern memories 8A and 8B, that is, in the test pattern data write mode will be described. . Since the write address is temporarily stored in the address register 8L via the tester bus 7C, the MUX 82 outputs the write address WAD stored in the address register 8L to the address shifter 83.

In the test pattern data write mode, the address shifter 83 does not perform a shift process but directly writes the write address to the upper input terminals of the MUXs 84 and 85 and the MUX.
Output to lower input terminals of 88 and 89. The address shifter 83 outputs the least significant bit of the address to the MUX 8H. By the way, since the lower input terminals of the MUXs 88 and 89 are selected, the write addresses WAD output to the MUXs 84 and 85 have no meaning. MUX
Reference numerals 88 and 89 output the write address WAD to the address terminals of the pattern memories 8A and 8B.

At this time, since the test pattern data is input to the pattern memories 8A and 8B via the tester bus 7C and the gate 8P to the data input terminal Din, the test pattern data is sequentially written to a predetermined write address WAD. When confirming the contents of the written test pattern data, the address register 8L, MU
The read address is input to the address terminals of the pattern memories 8A and 8B via the X82, the address shifter 83, the MUXs 88 and 89, and the test pattern data from the data output terminal Dout is read via the MUX 8M, the gate 8N and the tester bus 7C.

Next, the operation of each unit in the case where the upper input terminals of the MUXs 82, 88 and 89 are selected and the test pattern data is read from the pattern memories 8A and 8B, that is, the test pattern data read mode will be described. The read address RAD created by the program processing in the pattern generating means 74 is taken into the flip-flop circuit 81 according to the operation clock φ, and is output to the upper input terminal of the MUX 82. MUX8
2 outputs the read address RAD from the flip-flop circuit 81 to the address shifter 83 because the upper input terminal is selected.

The address shifter 83 stores the pattern memories 8A and 8B in the test pattern data read mode.
When the memory access method is a 2-way interleave access method, the read address RAD shifted by one bit is read, and when the memory access method is a non-interleave access method, the read address RAD not shifted is input to the upper input terminals of the MUXs 84 and 85 and the MUX 88, respectively. And 89 to the lower input terminal. Further, the address shifter 83 sets the least significant bit of the read address RAD to MUX.
Output to the upper input terminal of 8H. However, in the test pattern data read mode, MUXs 88 and 89 are not used.
Since the upper input terminal is selected, the read address RAD directly input from the address shifter 83 to the lower input terminals of the MUXs 88 and 89 becomes meaningless.

The MUX 8H selects the lower input terminal when the memory access method of the pattern memories 8A and 8B is the 2-way interleave access method in the test pattern data read mode, and the count value from the counter 8G and its inverted output value To the selection terminals S of the MUXs 84 and 85, and the read address R output from the address shifter 83 in the case of the non-interleave access method.
The least significant bit of AD and its inverted output value are output to the selection terminals S of the MUXs 84 and 85.

Each of the MUXs 84 and 85 inputs a read address RAD from the address shifter 83 to an upper input terminal,
The flip-flop circuits 86 and 8 of the next stage are connected to the lower input terminal.
7 and outputs one read address RAD to flip-flop circuits 86 and 87 according to the input level of select terminal S.

The flip-flop circuits 86 and 87 have M
The read addresses RAD output from the UXs 84 and 85 are fetched at the cycle of the operation clock φ, and the MUXs 84 and 85 are read.
Feedback to the lower input terminal of the
And 89 to the upper input terminal. At this time, MUX
Since the upper input terminals of 88 and 89 are selected,
The read address RAD from the flip-flop circuits 86 and 87 is transferred to the address terminals A of the pattern memories 8A and 8B.
Output to DR.

An address terminal ADR of the pattern memories 8A and 8B has a read address R at the cycle of the operation clock φ.
Since AD is input, test pattern data corresponding to the read address RAD is sequentially output from the data output terminals Dout of the pattern memories 8A and 8B to the flip-flop circuits 8C and 8D at the cycle of the operation clock φ.

MUX 8E is a flip-flop circuit 8C
Is input to the upper input terminal, and the test pattern data from the flip-flop circuit 8D is input to the lower input terminal. On the other hand, the delay circuits 8J and 8K
8H is output to the selection terminal S of the MUX 8E with a delay corresponding to two operation clocks φ. Therefore, M
The UX 8E outputs the read address RAD output from the address shifter 83 two clocks earlier to the flip-flop circuit 86 or 87.
4 or 85 is selected.

That is, the read address RAD from the address shifter 83 two clocks before the operation clock is M
In the case where the data is taken into the flip-flop circuit 86 via the UX 84, the upper input terminal of the MUX 8E is selected, so that the test pattern data taken into the flip-flop circuit 8C is outputted through the flip-flop circuit 8F. You. Conversely, the read address RAD from the address shifter 83 corresponding to two operation clocks before is MU.
When the data is taken into the flip-flop circuit 87 via X85, the lower input terminal of the MUX 8E is selected, so that the test pattern data taken into the flip-flop circuit 8D is output via the flip-flop circuit 8F. Is done.

As described above, conventionally, the MUX 8 is provided before the address shifter 83 and before the pattern memories 8A and 8B.
2, 88, and 89 are provided. When the upper input terminals of the MUXs 82, 88, and 89 are selected, high-speed reading processing of test pattern data is performed as a high-speed bus, and when the lower input terminals are selected, a tester bus is used. Thus, the writing processing of the test pattern data by the control means 71 has been performed.

However, conventionally, a multiplexer (MUX 82, 8) is used to switch between a high-speed bus and a tester bus.
8 and 89), there is a problem that the amount of hardware becomes too large. In addition, this multiplexer causes an increase in the data arrival time from the pipeline processing flip-flop circuits 86 and 87 to the next-stage flip-flop circuit 8F, which causes a problem that the operation margin of the entire system is reduced.

The present invention has been made in view of the above points, and has been made in consideration of the above-described problems. A pattern generation method for an IC test apparatus capable of reducing the amount of hardware for bus switching and generating test pattern data without lowering an operation margin is provided. It is intended to provide a device.

[0037]

According to the present invention, there is provided a pattern generator for an IC test apparatus, in which test pattern data to be supplied to a device under test is stored in a pattern memory in advance in accordance with a first clock. A pattern generator for an IC test apparatus for generating desired test pattern data by reading it out in synchronization with a second clock; a counter for counting the second clock and outputting a count value; Value and said second
A first address generated in synchronism with the clock of FIG. 1, shifts the first address by a predetermined bit in accordance with the interleave access method, and outputs the count value from an empty bit generated by the shift processing. An address shifter that generates an interleaving address and outputs a predetermined range of the shifted first address as the read address, and decodes an interleaving address from the address shifter to generate a first selection signal. And a second selection signal and a second signal to be supplied to the pattern memory.
A memory control means for generating an address of the pattern clock in synchronization with the first clock and supplying a read / write control signal and the test pattern data to the pattern memory; a second address; a read address from the address shifter; A plurality of multiplexers for inputting addresses supplied to the pattern memory and switching and outputting these in accordance with the first and second selection signals, and latching the read address output from the multiplexer and A latch circuit which is controlled so as to output to the memory and to feed back to the input terminal of the multiplexer, and to directly output the second address to the pattern memory without latching.

[0038]

Conventionally, a pattern generator of an IC test apparatus stores test pattern data to be supplied to a device under test in a pattern memory in advance in accordance with a low-speed CPU clock (first clock), and stores it in advance. The desired test pattern data is generated by reading out in synchronization with a high-speed system clock (second clock).

In the present invention, an interleaving address and a read address are generated using a counter and an address shifter. That is, the counter counts the high-speed second clock and outputs the count value. The address shifter inputs the count value and a first address (system address) generated in synchronization with the second clock, shifts the first address by a predetermined bit according to the interleave access method, An interleave address is generated by outputting a count value from empty bits generated by the shift processing.

For example, if the pattern memory is divided into four segments, 1Way (non), 2W
Since the interleave access method of four ways is possible, the lower two bits of the first address are used as the interleave address. Then, in the case of 1-way (non-) interleaving, the address shifter outputs the lower 2 bits of the first address as an interleaved address without performing a shift process, and outputs the 2 way.
In the case of interleaving, only one bit is shifted,
A total of 2 bits of the lower 1 bit of the counter value and the lower 1 bit of the first address are output as an interleave address. In the case of 4-way interleaving, a shift process is performed by 2 bits, and 2 bits of the counter value are output as an interleave address.

The address shifter outputs a predetermined range of the shifted first address as a read address. That is, in the case of 1-way (non) interleaving, the address shifters
A first address other than the bits, that is, a value obtained by dividing the first address by 4 is output as a read address, and 2 Way
In the case of interleaving, a first address other than the lower two bits shifted by one bit, that is, a value obtained by dividing the first address by 2 is output as a read address,
In the case of 4-way interleaving, the first address other than the lower 2 bits shifted by 2 bits, that is, the first address is output as a read address as it is.

The decoder decodes the interleaving address from the address shifter and outputs a first selection signal. Here, the first selection signal is for selecting a segment constituting the pattern memory. The memory control means operates mainly when writing test pattern data to the pattern memory, and stores the second selection signal and the second address to be supplied to the pattern memory in the first memory.
, And supplies a read / write control signal and test pattern data to the pattern memory.

Each multiplexer receives the second address, the read address from the address shifter, and the address supplied to the pattern memory, and switches and outputs these in accordance with the first and second selection signals. The latch circuit is controlled so as to latch the read address output from the multiplexer, output the read address to the pattern memory, feed it back to the input terminal of the multiplexer, and directly output the second address to the pattern memory without latching. ing.

That is, the multiplexer reads the test pattern data from the pattern memory at a high speed.
When the read address from the address shifter or the address supplied from the latch circuit to the pattern memory is alternately supplied to the pattern memory according to the interleaving address from the decoder, and the test pattern data is written to the pattern memory at a low speed. Supplies the second address from the memory control means to the pattern memory without operating the latch circuit. As a result, the pattern generator of the present invention can reduce the amount of hardware for bus switching and can generate test pattern data without lowering the operation margin.

[0045]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a pattern generator of an IC test apparatus according to the present invention. FIG.
Is the pattern memory (memory segment # 0) in FIG.
FIG. 4 is a diagram showing details of peripheral circuits of # 3 to # 3. FIG. 3 is FIG.
3 is a diagram showing a detailed configuration of an internal memory control means 1D of FIG.
FIG. 4 is a diagram showing details of an interleave access address distribution circuit including the flip-flop circuit 11, the counter 12, the address shifter 13, the decoder 14, the multiplexers MUX0 to MUX3, and the latch circuits 16 to 19 in FIG.

First, the circuit configuration around the pattern memory (memory segments # 0 to # 3) will be described in detail with reference to FIG. The pattern memory of the present embodiment can perform three types of memory access of a 4-way interleave access system, a 2-way interleave access system, and a non- (1Way) interleave access system.
It has a variable I / O mechanism of O, 8 I / O, 16 I / O, and 32 I / O, and is composed of a total of four memory segments # 0 to # 4. 4 is divided into eight memory blocks # 0 to # 7. That is, a total of 32 pattern memories
It is composed of the memories M00 to M37.

Memory M00-M of memory segment # 0
07 is a write enable signal WE0 from the write enable control 46 of FIG.
Is being entered. Similarly, memory segments # 1 to
# 3 memories M10 to M17, M20 to M27 and M3
0 to M37 input write enable signals WE1, WE2 and WE3 from the write enable control 46 to enable terminals WE1, WE2 and WE3, respectively.

The memories M00 to M30 of the memory block # 0 of each of the memory segments # 0 to # 3 receive the chip select signal CS from the chip select control 44 of FIG.
0 is input to the chip select terminal CS0. Similarly, the memories M01 to M3 of the memory blocks # 1 to # 7
1, M02 to M32, M03 to M33, M04 to M3
4, M05 to M35, M06 to M36 and M07 to M3
7 designates chip select signals CS1 to CS7 from the chip select control 44 as chip select terminals CS1.
To CS7.

The memories M00 to M30 of the memory block # 0 of the memory segments # 0 to # 3 input the test pattern data MD0 to MD3 from the data shifter 48 of FIG. 4 to data input terminals Din0 to Din3. Similarly, the memories M01 to M3 of the memory blocks # 1 to # 7
1, M02 to M32, M03 to M33, M04 to M3
4, M05 to M35, M06 to M36 and M07 to M3
7 is the test pattern data MD from the data shifter 48
0-MD3 to the data input terminals Din4-7, Din8-
11, Din12-15, Din16-19, Din2
0-23, Din24-27 and Din28-31, respectively.

Memory M00-M of memory segment # 0
07 are data output terminals Dout0-3, Dout4-
7, Dout8-11, Dout12-15, Dout
16-19, Dout20-23, Dout24-27
, And 32-bit test pattern data MD0-MD31 output from Dout28-31 to the 0th terminal of the multiplexer (MUX) 1A.

Similarly, memory segments # 1 to # 3
Memories M10 to M17, M20 to M27 and M30 to
M37 is a data output terminal Dout0-3, Dout4
-7, Dout8-11, Dout12-15, Dout
t16-19, Dout20-23, Dout24-2
7 and 32-bit test pattern data MD0-MD31 output from Dout28-31 to the 0th to 3rd terminals of the multiplexer (MUX) 1A, respectively.

The multiplexer (MUX) 1A converts the addresses A0-A1 from the selection circuit 15 into selection terminals S0 and S0.
1, the memory segments # 0 to #
3 from which to output the test pattern data MD0-MD31 to the data shifter 1B. The data shifter 1B controls the output bit width of the test pattern data MD0-MD31 by shifting the test pattern data MD0-MD31 according to the upper three bits of the address A20-A22. The data shifter 1B includes four ICs of an 8-bit shift matrix.

The flip-flop circuit 1C operates in response to the operation clock φ1 from the timing generating means 73, and is a flip-flop circuit for pipeline processing. The flip-flop circuit 1C operates according to the operation clock φ1 from the timing generation means 73, and outputs the test pattern data MD0 to MD3 from the data shifter 1B.
Input 1 and output sequentially.

As shown in FIG. 2, the selection circuit 15 includes an AND circuit 21, a flip-flop circuit 22, an OR circuit 23,
24, and selectively outputs either the read address RA0-RA1 from the address shifter 13 or the write address WA0-WA1 from the internal memory control means 1D to the multiplexer (MUX) 1A. 13 or the write address WA20 from the internal memory control means 1D.
-WA22 is selectively used as a data shifter 1B.
Output to

Next, the internal memory control means 1 will be described with reference to FIG.
The detailed configuration of D will be described. Internal memory control means 1
D is a pattern memory (each memory segment # 0 to # 4)
The operation is performed when writing and reading of the test pattern data MD0 to MD31 to and from the CPU in synchronization with the CPU clock via the tester bus 7C. Address counter 4
1, 42 and 43 designate write addresses and read addresses of the pattern memory, and are controlled by the carry control 45 corresponding to the interleave mode, and operate as three types of counters.

That is, the address counters 41 and 42
Is a 1-bit counter, and the address counter 43 is 2
It is a 1-bit counter, but in the non-interleave mode, the carry control 45
It operates as a bit (WA0-WA22) counter. In the 2-way interleave mode, the address counter 41 operates as a 1-bit (WA0) counter, and the address counters 42 and 43 operate on a 22-bit (WA).
1-WA22).

In the 4-way interleave mode, the address counters 41 and 42 have 2 bits (WA0-WA).
1), and the address counter 43 operates as a 21-bit (WA2-WA22) counter. The address counter 43 stores the upper 3 bits W
A20-WA22 to chip select control 44,
Output to the address shifter 47 and the selection circuit 15. The address counter 41 writes the count value and the least significant bit address (WA0) into the write enable control 46.
, And the address counter 42 outputs the count value and the lower bit address (WA1) to the first terminal W0 of the write enable control 46.

The carry control 45 controls the outputs of the address counters 41 and 42 according to the interleave mode signal EM input to the mode terminal MODE as described above. The carry control 45 inputs the memory port enable signal MPE to the master enable terminal ME to control the output of the pattern memory.

The write enable control 46 applies an interleave mode signal EM to the mode terminal MODE,
Write control signal CPU to write / read control terminal R / W
R / W, the lower bit address WA1 of the address counter 42 is input to the first terminal W0, and the lowest bit address WA0 of the address counter 41 is input to the second terminal W1, and a write enable signal WE0 is input in response to these signals.
-Control the output of WE3.

For example, when the interleave mode signal EM indicates the non-interleave mode, the first terminal W
Only one of the write enable signals WE0 to WE3 is enabled according to 0 and the low level “0” or the high level “1” of the second terminal W1, and one segment of the pattern memory is enabled. In the case of the two-way interleave mode, any two of the write enable signals WE0 to WE3 are enabled according to the low level “0” or the high level “1” of the first terminal W0 or the second terminal W1, and the pattern Enable two segments of memory. Further, in the case of the 4-way interleave mode, all of the write enable signals WE0 to WE3 are enabled, and all the segments of the pattern memory are enabled.

The chip select control 44 supplies a memory port enable signal MPE to the enable terminal EN.
Is connected to the mode terminal MODE by the variable output control signal I / O M
ODE and the upper 3-bit addresses WA20-WA22 from the address counter 43 are input to the chip select terminal CC, respectively, and chip select signals CS0-CS7 based on these signals are input to the respective memory blocks # 0- # 7 of the pattern memory. Output to the chip select terminal.

For example, the variable output control signal I / O MOD
When E is in the 4 I / O mode, the address counter 43
And only one of the memory blocks is selected based on the upper three-bit address WA20-WA22 from
In the case of the 8 I / O mode, any two memory blocks are selected. In the case of the 16 I / O mode, any four memory blocks are selected. In the case of the 32 I / O mode, all memory blocks are selected. Select

The address shifter 47 outputs the upper three bits of the address WA20-W from the address counter 43.
A22 is shifted according to the variable output control signal I / O MODE. The data shifter 48 shifts the test pattern data MD0-MD31 according to the upper three bits shifted by the address shifter 47. The data shifter 48 includes four ICs of an 8-bit shift matrix.

Next, a detailed configuration of an address distribution circuit for interleaved high-speed access will be described with reference to FIG. This address distribution circuit operates when reading test pattern data from the pattern memory (memory segments # 0 to # 3) at high speed. The input-stage flip-flop circuit 11 outputs the read address RAD created by the program processing in the pattern generating means 74 to the operation clock φ.
1 and output to the address shifter 13.

The 2-bit counter 12 generates an interleave address, is constituted by a binary counter, and outputs the count value to the address shifter 13. When the memory access method of the pattern memory is the 4-way interleave access method in the test pattern data read mode,
Multiplexers MUX0 to MUX3 each represent a read address shifted by one bit, a read address shifted by one bit in the case of the 2-way interleave access method, and a read address not shifted in the case of the non- (1 Way) interleave access method.
To the 0th input terminal D0.

In the test pattern data read mode, if the memory access method of the pattern memory is the 4-way interleave access method, the address shifter 13 counts the count value R from the 2-bit counter 12.
In the case of the 2-way interleave access method, the interleave address RA0 from the 2-bit counter 12 and the least significant bit RA1 of the read address RAD from the input-stage flip-flop circuit 11 that has been shifted by 1 bit are set to non- (A0-RA1). 1Way) In the case of the interleave access method, the least significant two bits RA0-RA1 of the read address RAD which is not subjected to the shift processing are output to the decoder 14 and the selection circuit 15 as an interleave address, respectively. That is, in the case of the non- (1 Way) interleave access method, the 2-bit counter 12
Becomes meaningless. Further, the address shifter 13 stores the upper three bits RA20-R of the read address RAD.
A22 is output to the selection circuit 15.

The decoder 14 inputs the interleaving addresses RA0-RA1 from the address shifter 13,
Based on the selection signal, the multiplexers MUX0 to MUX0
It selectively outputs to the selection terminal S0 of MUX3. That is, the decoder 14 outputs the interleave address RA1.
A multiplexer MUX0 when RA1 is "00"
In the case of "01", MUX1 is used, and in the case of "10", MUX1 is used.
A selection signal is output to UX2 and to MUX3 in the case of "11".

The multiplexers MUX0 to MUX3 input the read address RA2 to RA19 from the address shifter 13 to the 0th input terminal D0, and input the read address RA2 to RA19 to the first input terminal D1 one clock before output from the next-stage latch circuits 16 to 19. , The write addresses WA2-WA19 from the internal memory control means 1D are input to the second and third input terminals D2 and D3, and the selection terminals S0 and S1 are input.
Address A2-A according to the input level of
19 is output to the latch circuits 16 to 19.

When the latch clock LC from the internal memory control means 1D falls at the time when the output of the decoder 14 is at the low level "0", the latch circuits 16 to 19 input via the multiplexers MUX0 to MUX3 at that time. Address A2 to A19 to be stored, and keeps its own output otherwise. Therefore, the latch circuits 16 to 19
The function of extending the period of the address given to the pattern memory to four times the operation clock φ1.

On the other hand, at the time of CPU access, the multiplexers MUX0 to MUX3 input the high-level "1" CPU clock CLK to the selection terminal S1, so that
The address WA2-WA19 from the address counter 43 of the internal memory control means 1D is output to the latch circuits 16-19.

The latch circuits 16 to 19 receive the CPU clock CLK and the operation clock φ2 (clock having a phase different from that of the operation clock φ1) from the internal memory control means 1D, and output a negative value of a logical sum thereof. Since the latch clock LC is input from the circuit 1E, CP
When the U clock CLK is input, the through state is established, and the addresses WA2 to WA19 from the address counter 43 of the internal memory control means 1D are directly output to the pattern memories (memory segments # 0 to # 3).

The above operation will be described with reference to the time chart of FIG. FIG. 5 is a time chart showing the operation at the time of interleaved high-speed access, and FIG.
At the time of interleave high-speed access, (b) is a read address RAD at the time of 2-way interleave high-speed access, (c) is a read address RAD at the time of 1-way interleave high-speed access,
It shows the relationship with the address given to each pattern memory (memory segments # 0 to # 3).

In FIG. 5, the operation clock φ1 is several tens to
This is a frequency of one hundred and several tens of MHz. Since the frequency of the operation clock φ1 is determined by the access cycle time of the device under test 7E, it is not fixed as in a large-sized computer, but is determined by a program according to a reading method. Therefore, (a) to (c) of FIG.
Assuming that the minimum access cycle time of the device under test is Ta, the operation clock φ1 becomes a quarter of the minimum access cycle time Ta in the case of the 4-way interleave access method, and Ta in the case of the 2-way interleave access method. , Which is the same as Ta in the case of the 1-way interleave access method.

First, the case of the 4-way interleaving high-speed operation shown in FIG. The input stage flip-flop circuit 11 has "0",
"0", "1", "3", "3", "3", "4",
The read addresses RAD of “5”, “6”, and “7” are sequentially input. At this time, the address shifter 13 shifts the read address RAD by 2 bits, and
, The least significant two bits RA0-R
A1 is output to the decoder 14 as an interleave address. At this time, the decoder 14 sets the multiplexer MUX0 when the interleaving address RA1-RA1 is “00”, the MUX1 when the interleaving address RA1-RA1 is “01”, and sets “1” in the multiplexer MUX0.
A selection signal is output to MUX2 in the case of "0" and to MUX3 in the case of "11". In this case, MUX0, MUX
UX1, MUX2, MUX3, MUX0, MUX1, M
A selection signal is output in the order of UX2 and MUX3 in synchronization with the operation clock φ1.

At this time, the latch circuit 16 operating clock φ
The first read address “0” is latched in synchronization with “1”. However, the second to fourth read addresses “0”,
At the time of input of “1” and “3”, the selection terminal S of MUX0
Since no selection signal is input to 0, the output of the latch circuit 16 is circulated during this time to supply the same read address "0" to the memory segment # 0 of the pattern memory. Hereinafter, similarly, MUX1 to MUX3 and latch circuits 17 to 19
Also operates to supply the read address ADR to the memory segments # 0 to # 3 during the minimum access cycle time Ta. Accordingly, the read addresses “0”, “0”, “1”, “3”,
"3", "3", "4", "5", "6", and "7" are supplied.

A description will be given of the case of the 2-way interleaving high-speed operation shown in FIG. In the case of the 2-way interleaved access method, the operation clock φ1 has a cycle of half of the minimum access cycle time Ta. That is, 2
The operation clock φ1 in the Way interleave access method has a cycle twice that in the case of FIG. The read addresses RAD of “0”, “0”, “3”, “3”, and “3” are sequentially input to the input-stage flip-flop circuit 11 in synchronization with the operation clock φ1. At this time, the address shifter 13 shifts the read address RAD by one bit, sets the count value from the counter 12 as the least significant bit RA0 of the interleave address, and sets the least significant bit of the read address RAD as the lower bit RA1 of the interleave address. Output to the decoder 14.

Therefore, at the time of the first read address “0”, the decoder 14 supplies the interleave address R
Since "00" is input as A1-RA1, MUX0
Output the selection signal to Similarly, when the second read address is "0", RA1-RA0 is "01" and MUX1 is selected. When the third read address is "3", RA1-RA0 is "10" and MU is selected.
When X2 is selected and the fourth read address is "3", RA1-RA0 is "11", MUX3 is selected and when the fifth read address is "3", RA1-RA0 is RA1-R0.
A0 becomes “10”, and MUX2 is selected. At this time, the read address RA2-RA19 is input to MUX0-MUX3 as a read address shifted by one bit, so that "0", "0", "1", "1", "1" are supplied as read addresses.

A description will now be given of the one-way interleave high-speed operation shown in FIG. In the case of the 1-way interleaved access method, the operation clock φ1 has the same cycle as the access cycle minimum time Ta. That is, 1 Way
The operation clock φ1 of the interleave access method is shown in FIG.
The period is four times that of the case (a). Read addresses RAD of “0”, “1”, and “3” are sequentially input to the input stage flip-flop circuit 11 in synchronization with the operation clock φ1. At this time, the address shifter 13 does not shift the read address RAD without changing the lower two bits RA.
Decoder 1 using 1-RA0 as an interleave address
4 is output.

Therefore, in this case, the read address RAD
And the memory segments have a one-to-one correspondence. That is, when the read address RAD is “0”, the address “0” of the memory segment # 0 is accessed, and when the read address RAD is “1”, the address “0” of the memory segment # 1 is accessed. When the read address RAD is "3", the address "0" of the memory segment # 3 is accessed.

[0080]

As described above, according to the present invention, the amount of hardware for bus switching can be reduced, and the test pattern data can be generated without lowering the operation margin.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a pattern generator of an IC test apparatus according to the present invention.

FIG. 2 is a diagram showing details of a peripheral circuit of a pattern memory (memory segments # 0 to # 3) in FIG. 1;

FIG. 3 is a diagram showing a detailed configuration of an internal memory control unit of FIG. 1;

FIG. 4 is a diagram showing details of an interleave access address distribution circuit including a flip-flop circuit, a counter, an address shifter, a decoder, a multiplexer, and a latch circuit in FIG. 1;

FIG. 5 shows interleaved high-speed access in FIG.
FIG. 5 is a time chart illustrating the operation of the embodiment.

FIG. 6 is a block diagram showing a schematic configuration of a conventional IC test apparatus.

7 is a diagram showing a two-system bus configuration of the pattern generating means of FIG. 6 for generating expected value data by a memory stored method.

[Explanation of symbols]

71 control means, 72 DC measurement means, 73 timing generation means, 74 pattern generation means, 75 pin control means, 76 pin electronics, 77 fail memory, 78 formatter, 79 comparator logic, 7A Driver, 7B: comparator, 7C: tester bus, 7D: IC mounting device, 7E: IC to be measured, 1
1, 1C: flip-flop circuit, 12: counter, 1
3 ... Address shifter, 14 ... Decoder, 15 ... Selection circuit, MUX0, MUX1, MUX2, MUX3, MUX
... Muxes, 16, 17, 18, 19 ... Latch circuits, 1B ... Data shifters, 1D ... Internal memory control means

Claims (2)

(57) [Claims] 1. A test pattern data to be supplied to a device under test is previously stored in a pattern memory in accordance with a first clock, and read out in synchronization with a second clock to obtain a desired test pattern. A pattern generator for an IC tester for generating data, comprising: a counter for counting the second clock and outputting the count value; and a first counter generated in synchronization with the count value and the second clock. An address is input, the first address is shifted by a predetermined bit in accordance with an interleave access method, and the count value is output from an empty bit generated by the shift processing to generate an interleaving address and shift processing. A predetermined range of the first address is output as the read address. An address shifter, a decoder that decodes an interleaving address from the address shifter and outputs a first selection signal, and a second selection signal and a second address to be supplied to the pattern memory are stored in the first memory. A memory control unit that generates a read / write control signal and the test pattern data to the pattern memory in synchronization with a clock, and supplies the second address, a read address from the address shifter, and the pattern memory. A plurality of multiplexers for inputting addresses and switching them according to the first and second selection signals and outputting the read addresses; latching the read addresses output from the multiplexers and outputting the read addresses to the pattern memory; Feedback to the input end of the second Pattern generator of the IC tester being characterized in that comprises a latch circuit which is controlled to output directly to the pattern memory without latching respect dresses. 2. The test pattern data output from the pattern memory in accordance with an address other than the interleaving address and the read address out of the first addresses output from the address shifter, to a desired output bit width. 2. The pattern generator according to claim 1, further comprising a data shifter for performing a shift process so as to satisfy the following condition.