JP3180729B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art With the increase in the density and integration of semiconductor devices, a multilayer wiring structure has been used in which wiring is separated by an insulating film and divided into a plurality of layers. When forming a multi-layer wiring structure, if the surface shape after the lower wiring layer is covered with an insulating film has a projection, a fine pattern cannot be formed in the photo process, or the upper wiring is disconnected or short-circuited. Occurs.

Therefore, a flattening means such as a chemical mechanical polishing method (CMP method) is used. At this time, if the wiring has a large difference in density, the cross-sectional structure after flattening cannot be completely flattened, and a step occurs in the insulating film. In addition, when the wiring layout data rate is reduced to some extent, there is a problem that it is not possible to automatically determine the end of etching by an etching apparatus during etching.

Conventionally, in order to solve the above problem, there is a method of laying a dummy wiring having a minimum width determined by a semiconductor device to be manufactured in a region where no wiring is provided at a minimum interval determined by a semiconductor device to be manufactured. Was used. Further, by connecting the dummy wiring 8 to a potential opposite to the substrate potential of the semiconductor device and forming a capacitance between the dummy wiring 8 and the semiconductor substrate, fluctuations in the power supply voltage are prevented, and a stable voltage is supplied to the internal circuit. Was like that.

FIG. 6 shows a conventional semiconductor device. In the conventional semiconductor device shown in FIG. 6, a dummy wiring 8 is provided in an empty area where no real wiring 2 exists, and a minimum interval S0 defined by a semiconductor device to be manufactured is provided between the dummy wiring 8 and the real wiring 2.
They are laid out in a grid with a minimum width W0 and a minimum interval S0.

FIG. 7 is a view showing a conventional semiconductor device. In the conventional semiconductor device shown in FIG. 7, a dummy wiring 8 is provided in an empty area where the actual wiring 2 does not exist, and a minimum distance S0 defined by a semiconductor device to be manufactured is provided between the dummy wiring 8 and the actual wiring 2.
The layout was linear in the minimum width W0 and the minimum interval S0. Also, by adding the wiring 6, the dummy wiring 8
Is connected to a wiring 2v having a potential opposite to the potential of the substrate of the semiconductor device, and a capacitance is formed between the wiring and the semiconductor substrate to prevent fluctuation of the internal power supply voltage and supply a stable voltage to the internal circuit. I was

FIG. 8 shows a CM when cut along the line BB in FIG. 6 and a CM when cut along the line CC in FIG.
It is sectional drawing which shows the shape after planarization by P method. As shown in FIG. 8, the surface shape of the insulating film 5 is flattened by the CMP method. In FIG. 8, reference numeral 4 denotes a semiconductor substrate or an insulating film of a lower wiring.

[0008]

However, the structure of the semiconductor device shown in FIGS. 6 and 7 has a problem that it takes a lot of time to verify design rules and generate reticle creation data.

The reason is that the total wiring amount including the dummy wiring becomes enormous by adding the dummy wiring to all the regions other than the actual wiring.

Further, when the potential of the dummy wiring is not fixed, there is a problem that the delay time of the signal flowing through the actual wiring adjacent to the dummy wiring cannot be accurately estimated by calculation.

The reason is that the capacitance value of the capacitance generated between the dummy wiring and the actual wiring cannot be calculated because the potential of the dummy wiring is not fixed.

Further, when the potential of the dummy wiring is fixed, there is a problem that the delay time of the signal flowing through the real wiring adjacent to the dummy wiring becomes unnecessarily large.

The reason is that the distance between the dummy wiring and the actual wiring is the minimum distance determined by the semiconductor device to be manufactured, so that the capacitance value generated between the dummy wiring and the actual wiring becomes extremely large. is there.

An object of the present invention is to minimize the total amount of wiring including dummy wirings and the delay time of signals flowing through actual wirings adjacent to the dummy wirings, thereby improving reliability and production efficiency. And to provide a semiconductor device with improved performance.

[0015]

In order to achieve the above object, a semiconductor device according to the present invention comprises a dummy device having a wiring width of 2 to 5 times the actual wiring in an empty area where no actual wiring exists on the semiconductor device. Arrange wiring in block units , at least before
The dummy wiring in the block adjacent to the real wiring
Are arranged orthogonally to the actual wiring, and
The adjacent dummy wiring is connected to a substrate potential.
You .

[0016] The blocks may include a distance between the blocks.
The distance between the block and the actual wiring is determined by the semiconductor device to be manufactured.
Are arranged to be larger than the specified minimum wiring interval.
And the distance between the dummy wirings in the block is
This is the minimum wiring interval .

[0017]

[0018]

The size of the dummy wiring block is suppressed to a size that does not cause a protrusion on the insulating film during planarization by the CMP method, and the insulating film is formed when the dummy wiring blocks are planarized by the CMP method. The surface shape of the insulating film after flattening by the CMP method is flattened by separating the insulating film by a distance that does not generate a convex portion. Further, by forming the dummy wiring so that the layout data rate of the total wiring including the dummy wiring exceeds a level that can automatically determine the end of the etching by the etching apparatus at the time of the etching, the dummy wiring is formed. It is possible to automatically determine the end of etching by an etching apparatus.

The dummy wiring has a wiring width of 2 to 5 times the minimum wiring width determined by the semiconductor device to be manufactured, and the layout data ratio of the total wiring is easily achieved. In addition, by setting the width of the dummy wiring to five times the minimum wiring determined by the semiconductor device to be manufactured, the CMP
During the planarization by the method, no convex portion due to the dummy wiring is generated in the insulating film.

Further, by arranging the dummy wiring as far as possible from the actual wiring which satisfies the above conditions, the capacitance value of the capacitance generated between the dummy wiring and the actual wiring can be minimized.
The delay time of the signal flowing through the actual wiring is reduced. Also,
By fixing the potential of the dummy wiring adjacent to the real wiring, the capacitance value generated between the real wiring and the dummy wiring adjacent thereto can be accurately calculated, and the delay time of the signal passing through the real wiring can be accurately estimated. be able to. Further, by arranging the dummy wiring adjacent to the real wiring in a direction orthogonal to the real wiring, the capacitance value generated between the real wiring and the dummy wiring adjacent thereto can be minimized.

[0022]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing layout data of real wiring and dummy wiring according to Embodiment 1 of the present invention. In FIG. 1, a dummy wiring block 1 is placed in an empty area where no actual wiring 2 exists, and a distance S between blocks is set.
A plurality of 3a and S4a are arranged so as not to generate a convex portion (for example, 500 μm or more) in the insulating film at the time of planarization by the CMP method. At this time, the layout data rate of the total wiring including the dummy wiring exceeds an extent (for example, 20%) at which the end of the etching can be automatically judged by the etching apparatus at the time of the etching, and when the flattening by the CMP method is performed. The difference is set to a minimum value that can eliminate a difference in density that causes a convex portion in the insulating film. Then, the distances S1a, S1b, S1 between the dummy wiring block 1 and the real wiring 2 are set so that the parasitic capacitance between the real wiring and the dummy wiring is sufficiently reduced.
A plurality of c and S2a are arranged so as to be as far apart as possible and at least as long as the minimum wiring interval defined by the semiconductor device to be manufactured.

FIG. 2 is a diagram showing layout data of the dummy wiring block shown in FIG. In the dummy wiring block 1 shown in FIG. 2, the dummy wiring 3 having a wiring width W1a that is 2 to 5 times the minimum wiring width determined by the semiconductor device to be manufactured.
Is determined in a rectangular region having a length L1a (for example, 500 μm or less) and a width L2a (for example, 500 μm or less) of such a size as not to generate a convex portion in the insulating film at the time of planarization by the CMP method. Minimum wiring interval S
It is spread at 0.

FIG. 3 is a cross-sectional view of the planarized insulating film taken along line AA of FIG. Embodiment 1 of the present invention
In FIG. 3, when the wiring pattern of FIG. 1 is formed of a metal on a semiconductor substrate or a flat insulating film 4 and is flattened by a CMP method after being covered with the insulating film 5, as shown in FIG.
The insulating film 5 after the flattening was flat.

FIG. 9 is a cross-sectional view showing a shape after flattening when a region where dummy wirings having the minimum wiring width are arranged at minimum intervals is widened. As shown in FIG. 9, for example, a dummy wiring 8 having a minimum wiring width W0 determined by a semiconductor device to be manufactured as a wiring width is formed at a minimum wiring interval S0 determined by a semiconductor device to be manufactured and a vertical length and Horizontal length L3 is CM
When the layout is performed in a region having a length (for example, 500 μm or less) or more that does not cause a protrusion in the insulating film during the planarization by the P method, the protrusion 9 occurs during the planarization by the CMP method, and the insulating film becomes flat. do not become.

As is clear from the results shown in FIG. 9, if the amount of dummy wirings is simply reduced for the purpose of shortening the time required for verifying the design rules and generating the data for producing the reticle, the insulating film does not become flat. You can see that. In order to flatten the insulating film, the dummy wiring is divided and a block (for example, having a vertical length of 500 μm or less;
It is necessary to divide the block into a horizontal length of 500 μm or less, and to set the distance between the blocks to a level that does not cause a protrusion in the insulating film (for example, 500 μm or more) during planarization by the CMP method.

FIG. 10 is a cross-sectional view showing a flattened shape when dummy wirings having the minimum wiring width are arranged at a minimum interval. In order to satisfy the above-described conditions, the vertical length L4a and the horizontal length L4a of the dummy wiring 8 having the wiring width of the minimum wiring width W0 determined by the semiconductor device to be manufactured are flattened by the CMP method. Dummy wiring blocks arranged at a minimum wiring interval S0 determined by a semiconductor device to be manufactured are arranged in a region where a convex portion is not generated (for example, 500 μm or less) in the insulating film. In the case where the insulating film is arranged so as to have a distance (for example, 500 μm or more) at which no convex portion is generated, as shown in FIG. 10, the insulating film becomes flat when flattened.

However, in the case shown in FIG. 10, since the wiring width is the minimum wiring width W0 determined by the semiconductor device to be manufactured, the layout data ratio of the total wiring including the dummy wiring does not exceed 20%, and the wiring width does not exceed 20%. In this case, there is a disadvantage that it is not possible to automatically determine the end of the etching by the etching apparatus. Therefore, it is necessary to make the width of the dummy wiring larger.

In FIG. 11, the width of the dummy wiring 10 is increased,
That is, the minimum wiring width S determined by the semiconductor device to be manufactured
If the value is 5 times or more than 0, the cross section is formed after flattening by the CMP method. In this case, as shown in FIG. 11, the projections 9 are generated at the time of flattening irrespective of the interval S6 between the dummy wirings, and the insulating film is not flattened.

From the above considerations, in the layout of the dummy wirings as shown in FIG. 1, the layout data ratio of the total wiring including the dummy wirings is large enough that the etching apparatus can automatically determine the end of the etching at the time of etching. Satoshi,
The insulating film after planarization by the CMP method is kept flat, and
It can be seen that the layout is optimal to minimize the wiring data rate.

In FIG. 1, the dummy wiring is separated from the actual wiring as far as possible to satisfy other conditions, and unnecessary capacitance is prevented from being generated between the dummy wiring and the actual wiring. It is possible to minimize the increase in the delay time of the signal flowing through the actual wiring due to the addition, and to improve the performance of the semiconductor device.

Therefore, in the semiconductor device according to the first embodiment of the present invention, the wiring width is set to 2 to 5 times the minimum wiring width W0 determined in the semiconductor device to be manufactured in the empty area where the actual wiring 2 does not exist. The dummy wiring 3 (Wa1 in FIG. 2) is connected to the minimum wiring spacing (S in FIG. 2) determined by the semiconductor device to be manufactured.
0), the distance between the blocks (S3a and S4a in FIG. 1) and the distance between the block and the actual wiring (S1a, S1b, S1c and S2a in FIG. 1) are determined by the semiconductor device to be manufactured. Are arranged so as to be larger than the minimum wiring interval.

(Embodiment 2) FIG. 4 is a diagram showing layout data of actual wiring, dummy wiring, and wiring for fixing the potential of the dummy wiring according to the first embodiment of the present invention. FIG.
In the layout data shown in (1), the distances S2b and S1d between the dummy wiring block 7 and the real wiring 2 have a large capacitance generated between the dummy wiring block 7 and the real wiring 2, and flow through the real wiring adjacent to the dummy wiring. It is an example showing a case where the delay time of a signal is close to a level that cannot be ignored.

Among the dummy wirings included in the dummy wiring block 7, the wiring 6 whose distance from the actual wiring 2 is short as described above.
Is added, and the wiring 6 is connected to the wiring 2g connected to the potential of the semiconductor substrate. Thus, the potential of the dummy wiring adjacent to the real wiring 2 can be fixed, the capacitance generated between the dummy wiring and the real wiring 2 can be accurately calculated, and the potential flows to the real wiring adjacent to the dummy wiring. It is possible to accurately estimate the signal delay time.

FIG. 5 shows the dummy wiring block 7 shown in FIG.
FIG. As shown in FIG. 5, the dummy wiring 3 having a wiring width W1c that is 2 to 5 times the minimum wiring width W0 determined by the semiconductor device to be manufactured generates a convex portion in the insulating film during planarization by the CMP method. Vertical L1 of size not to let you do
c (for example, 500 μm or less), the horizontal L2b (for example, 500 μm).
(μm or less) are arranged at the minimum wiring interval S0 determined by the semiconductor device to be manufactured. The dummy wiring adjacent to the real wiring 2 is laid out in a direction orthogonal to the real wiring, and the capacitance generated between the dummy wiring and the real wiring 2 is reduced as compared with the case where the dummy wiring is laid out in parallel with the real wiring 2. Therefore, the delay time of the signal flowing through the real wiring adjacent to the dummy wiring can be minimized, and the performance of the semiconductor device can be improved.

[0037]

As described above, according to the present invention, unnecessary time required for verifying design rules and generating reticle creation data can be reduced.

The reason is that the wiring amount of the dummy wiring is
Under the condition that the insulating film is flattened by the flattening by the P method, and the layout data rate of the total wiring including the dummy wiring exceeds a degree that the etching apparatus can automatically judge the end of the etching at the time of etching. This is because it is possible to minimize it.

Further, the delay time of the signal flowing through the actual wiring adjacent to the dummy wiring can be accurately estimated by calculation.

The reason is that since the potential of the dummy wiring adjacent to the actual wiring is fixed, the capacitance value of the capacitance generated between the dummy wiring and the actual wiring can be accurately calculated.

Further, it is possible to prevent the delay time of the signal flowing through the actual wiring due to the addition of the dummy wiring from becoming unnecessarily long.

The reason is that it is possible to arrange the dummy wiring as far as possible from the actual wiring as far as the above conditions are satisfied.

[Brief description of the drawings]

FIG. 1 is a diagram showing layout data of a real wiring and a dummy wiring according to a first embodiment of the present invention.

FIG. 2 is a diagram showing layout data of a dummy wiring block shown in FIG. 1;

FIG. 3 is a cross-sectional view of the planarized insulating film taken along the line AA of FIG. 1;

FIG. 4 is a diagram showing layout data of real wiring, dummy wiring, and wiring for fixing the potential of the dummy wiring in the first embodiment of the present invention.

FIG. 5 is an enlarged view of the dummy wiring block shown in FIG. 4;

FIG. 6 is a diagram showing layout data of a dummy wiring and a wiring for fixing the potential of the dummy wiring in the conventional example.

FIG. 7 is a diagram showing layout data of actual wiring, dummy wiring, and wiring for fixing the potential of the dummy wiring in the conventional example.

8 is a cross-sectional view showing a shape after planarization by a CMP method when cut along a line BB in FIG. 6 and a line CC in FIG. 7;

FIG. 9 is a cross-sectional view showing a shape after flattening when a region where dummy wirings are arranged at minimum intervals with a minimum wiring width is widened;

FIG. 10 is a cross-sectional view showing a flattened shape when a region where dummy wirings are arranged with minimum wiring width at a minimum interval is taken in the same manner as in the present invention.

FIG. 11 is a cross-sectional view showing a shape after flattening when laying down without gaps.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 dummy wiring block 2 real wiring 2 g real wiring connected to potential of semiconductor substrate 2 v real wiring connected to potential opposite to the potential of semiconductor substrate 3 dummy wiring 4 semiconductor substrate or flat insulating film 5 insulating film 6 dummy Wiring potential fixing wiring 7 Dummy wiring block 8 Dummy wiring with minimum wiring width 9 Convex part generated in insulating film 10 Dummy wiring with wide width S0 Minimum wiring interval defined by semiconductor device to be manufactured S1a Dummy wiring block 1 and real wiring 2 S1b Distance between dummy wiring block 1 and real wiring 2 S1c Distance between dummy wiring block 1 and real wiring 2 S1d Distance between dummy wiring block 7 and real wiring 2 S2a Distance between dummy wiring block 1 and real wiring 2 S2b Dummy wiring block 7 and actual wiring 2 S3a Distance between dummy wiring blocks 1 S4a Dummy wiring block 1 S5 Distance between dummy wiring blocks S6 Wiring spacing of dummy wiring 10 W0 Minimum wiring width defined by semiconductor device to be manufactured W1a Wiring width of dummy wiring 3 W1b Wiring width of dummy wiring 3 W1c Wiring width of dummy wiring 3 Wiring width of dummy wiring 10 L1a Vertical length of dummy wiring block 1 L1b Vertical length of dummy wiring block 1 L1c Vertical length of dummy wiring block 7 L2a Horizontal length of dummy wiring block 1 L2b Dummy wiring block 7 L3 Length of one side of dummy wiring block L4a Length of one side of dummy wiring block L4b Length of one side of dummy wiring block

Claims (2)

(57) [Claims] 1. A dummy wiring having a wiring width of 2 to 5 times the actual wiring is arranged in block units in an empty area on a semiconductor device where no actual wiring exists , and at least a dummy wiring in the block adjacent to the actual wiring is arranged . Said
The dummy wiring is arranged orthogonally to the actual wiring, and
The dummy wiring adjacent to the actual wiring is connected to the substrate potential.
A semiconductor device characterized by the above-mentioned. 2. The method according to claim 1, wherein the blocks include a distance between the blocks and
The distance between the block and the actual wiring is determined by the semiconductor device to be manufactured.
Are arranged so that they are larger than the minimum wiring interval
And the distance between the dummy wirings in the block is minimum.
2. The semiconductor device according to claim 1, wherein the interval is a small wiring interval .