JP3173093B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to polycrystalline silicon (polysilicon: p-type).
The present invention relates to a Bipolar or BiCMOS type LSI using poly-Si) or the like for a resistance element, an electrode lead-out portion or the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Polysilicon (poly-Si)
The resistor used is silicon dioxide (SiO 2). _Two) Etc. on insulating film
It can be miniaturized and has a small parasitic capacitance.
Well, because the substrate bias effect resistance is large,
Diffuses impurities into single crystal silicon (Si)
Advantages compared to diffusion resistors formed by
Have been.

[0003] Generally, the resistivity of poly-Si is controlled by the concentration of impurities. Therefore, when a plurality of poly-Si layers having different resistivity are formed by a single process, the poly-Si layers are formed by changing the impurity concentration in the poly-Si by the following steps.

(A) First, an impurity is implanted into a predetermined portion of poly-Si by an impurity concentration corresponding to the highest predetermined resistivity.

(B) The high-resistance portion (region) formed in the step (a) is masked by photolithography.

(C) Next, an impurity is implanted into a predetermined portion of the poly-Si by an impurity concentration corresponding to the low resistivity.

(D) Using photolithography technology,
The high-resistance portion formed in the steps (a) and (c) is masked.

(E) Then, an impurity is implanted into a predetermined portion of the poly-Si by an impurity concentration corresponding to the next lower resistivity. Hereinafter, similar steps are continued.

[0009]

As described in the above steps, the method of changing the impurity concentration at each predetermined portion of poly-Si causes an increase in the number of processes (steps) and a mask in a photolithography process. Causes misalignment.

Furthermore, the controllability of the resistivity of the poly-Si resistance is deteriorated due to the non-uniformity of the concentration caused when the impurities are implanted into the predetermined portion of the poly-Si and the diffusion of the impurities caused by the heat treatment in the later step. .

Accordingly, the present invention provides a semiconductor device having silicon layers having the same impurity concentration and different resistivity, and a method for manufacturing the same.

[0012]

Means for Solving the Problems The above-mentioned problems have been solved at least.
Also, a semiconductor having two or more independent resistors on the same substrate
Body device, wherein each resistor comprises a first and a second insulation.
Between the films with the same impurity implanted at the same concentration
Consisting of a silicon thin film or a single silicon thin film
It has a multilayer body and at least one resistor
No. 1 sandwiching a silicon thin film or a single silicon thin film
The first insulating film or the second insulating film forms the other resistor.
Polysilicon thin film or single silicon thin film
And the thickness and / or thickness of the first insulating film or the second insulating film
Or, by making the material different, this multilayer body is
Simultaneously formed by lamp annealing
Is solved by a semiconductor device characterized in that
You. Further, the above problem is solved by forming a polysilicon layer on the first insulating film.
Of forming a thin silicon film or single silicon thin film
And polysilicon thin film or single silicon thin film
A step of implanting ions of a predetermined concentration;
At least two films or single silicon thin films
To form multiple silicon patterns
Forming a second insulating layer on the plurality of silicon patterns.
Forming a plurality of multilayer bodies by forming an edge film;
Lamp annealing the multilayer body under predetermined heat treatment conditions;
And at least one of the plurality of silicon patterns
In the formation of the first insulating film or the second insulating film,
The first insulating film or the second insulating film of another silicon pattern
It is characterized by different thickness and / or material from the rim
The problem is solved by a method of manufacturing a semiconductor device.

According to the present invention, there is further provided a step of forming a polysilicon thin film or a single silicon thin film on a first insulating film, a step of implanting ions of a predetermined concentration into the polysilicon thin film or the single silicon thin film, Patterning the polysilicon thin film or single silicon thin film on at least two or more portions to form a plurality of silicon patterns; forming a second insulating film on the plurality of silicon patterns to form a plurality of multilayer bodies; Forming the first insulating film or the second insulating film in at least one of the plurality of silicon patterns. According to a method of forming a semiconductor device, the material and / or the thickness of the film are varied. It is solved.

[0014]

The semiconductor device of the present invention and the method of manufacturing the semiconductor device
According to the method, in the lamp annealing step of a polysilicon thin film or a single silicon thin film in which the same impurity is implanted at the same concentration, the structure (material and / or thickness) of the polysilicon thin film or the single silicon thin film is different from each other. Since the temperature rise / fall characteristics and the maximum attainable temperature of a multilayer resistor having a different structure can be controlled , the activation rate of impurities in each silicon thin film via the first and second insulating films and the grain (Grain) of the silicon thin film ) Grows, and as a result, the temperature rise and fall characteristics of each multilayer
Performance and maximum temperature can be easily controlled.
Under one lamp annealing heat treatment condition, each resistivity is different
Independent resistors on the same substrate easily and simultaneously.
Can be built.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Under the conditions of 1050 ° C. for 10 seconds (the temperature change of the monitored wafer is shown in FIG. 1) set on the BareSi substrate (wafer) (single silicon), a multilayer semiconductor wafer having a different structure shown in FIG. Infrared (I
RA) treatment was performed. That is, Si as an insulating film having a thickness of 400 nm and a predetermined thickness x is sandwiched between poly-Si3 having a thickness of 150 nm on the surface of the BareSi substrate 1.
O ₂ (2, 4) is provided. Also, on the back surface of the Si substrate 1, a SiO ₂ (5,400 nm-thickness and a predetermined thickness y, with poly-Si 6 having a thickness of 150 nm interposed therebetween.
7) is formed.

During the above-mentioned IRA process, the temperature change of the monitored wafer has rise and fall temperature characteristics that differ depending on the structure (thickness in this case) as shown in FIGS. 3 to 6, and the maximum attainable temperature is 100 at the maximum (Max). ° C was different. That is, in FIG. 5, the maximum temperature when x = y = 200 nm (see the sample structure in FIG. 2) is 980 ° C., and in FIG. 6, the maximum temperature when x = y = 800 nm is 1077 ° C. is there. Note that x = y = 100 nm
The maximum temperature reached 1028 ° C. as shown in FIG.
The highest temperature reached when x = y = 400 nm was 1038 ° C. as shown in FIG. As a result, poly-Si
(Sheet resistance) became different values reflecting the highest temperature.

[0018] shows the relationship between the resistivity and the impurity concentration of the poly-Si in the case where the thickness of the film thickness of the underlying SiO ₂ and the front surface and the rear surface of the SiO ₂ is different polysilicon in FIG 7 (poly-Si). BareSi wafer multilayer structure shown in FIG. 2 (SiO ₂ films (2, 4) and (5, 7) are formed on the top and bottom of the Si substrate on and under the poly-Si thin film (3, 6))
(A) x = y = 200 nm, (b) x = 800 nm,
When the concentration of the impurity (BF ₂ ⁺ ) is changed from 1 × 10 ¹⁹ / cm ³ to about 3 × 10 ²¹ / cm ³ for each of the three kinds of samples of y = 200 nm and (c) x = y = 800 nm, FIG. 7, the resistivity is 1 × 10 ⁻¹ Ωcm.
It can be seen that the respective values vary from about to about 3 × 10 ⁻³ Ωcm. The thickness of poly-Si3 and 6 is 150
nm. Therefore, the film thickness of SiO ₂ is I from FIG 7
This has an effect on the elevating temperature characteristics during RA and the maximum attainable temperature.

Further, poly-Si and Si as a lower layer
The wafer structure in which a silicon nitride film (SiN) was inserted to a thickness of 35 nm between layers with O ₂ had a higher resistivity by 20 to 30% than the structure in which SiN was not inserted.

Further, similar results can be obtained by halogen lamp annealing for heating a semiconductor wafer with a multilayer structure similar to that of the IRA.

On the other hand, when the IRA treatment was not performed on a sample having the same structure as that described above, no significant difference was found in the sheet resistance ρs of the poly-Si resistor.

Hereinafter, specific examples of the present invention (poly-
The production of a Si resistor will be described with reference to FIG.

First, a LOCOS forming step is performed by a normal process. For example, an oxide film (SiO ₂ ) is formed on a P-type silicon substrate by thermal oxidation, a silicon nitride film (Si ₃ N ₄ ) is further formed thereon, and the Si ₃ N ₄ film is patterned and selectively oxidized. Form an area. Then, Si
₃ N ₄ film implanted boron ions for channel stop as a mask, and then a field oxide film (LOCOS oxide film).

FIG. 8A shows a part of the LOCOS oxide film 11 obtained by the above-described ordinary LOCOS forming process, and a 100 nm thick SiN film 12 selectively formed on the upper surface thereof. I have. The SiN patterning was performed by RIE.

Next, as shown in FIG.
150 nm po on the entire surface by D (chemical vapor deposition) method
The ly-Si layer 13 is formed. Then, an impurity, for example, boron (B ⁺ ) is doped on the entire surface by a usual ion implantation technique by a predetermined concentration.

Impurities are implanted into the electrode take-out portion with a resist mask at a high concentration.

Next, as shown in FIG. 8C, the photolithography technique and the RIE technique
The ly-Si film pattern 13a, then the SiO ₂ as the insulating film by the CVD method to the entire surface is deposited to a thickness of 300~400nm to form a SiO ₂ film 14 (FIG. 9 (a)),
Although not shown, an IRA process, which is normal annealing, is performed after the other device shaping processes. In this IRA process, poly-Si having a different lower layer structure of the wafer has different temperature rise / fall characteristics and maximum temperature, so that it is differently affected by the activation rate of impurities and the growth of grains, and exhibits different resistivity.

Next, as shown in FIG. 9B, an opening is formed by patterning the SiO ₂ film 14 for taking out an electrode.

Subsequently, Ti / TiN / Al-Si or polysilicon / WSi ₂ (tungsten silicide)
And the like are deposited on the entire surface and patterned to form an electrode 17.

As described above, poly-Si having the same shape and the same impurity concentration but different resistance values is obtained.
The resistance is completed.

Instead of poly-Si in the above embodiment,
A similar phenomenon is obtained with single silicon (single crystal silicon).

The poly-Si and poly-Si of the emitter (Em) of the bipolar transistor (BipTr) portion
An example in which a resistor and a resistor are formed simultaneously will be described.

In this case, due to the characteristics of the transistor, the poly-Si of Em makes the resistivity low, and the resistivity of the poly-Si resistance portion is not made low from the viewpoint of the design and the space limitation of the layout.

As described above, p of the same material but different in resistivity is used.
A poly-Si resistor having a desired resistivity can be formed by combining the upper layer, the lower layer structure, and the back surface structure of the poly-Si resistor with a predetermined thickness in forming the poly-Si resistor.

[0035]

According to the semiconductor device of the present invention, the same
Each of the two or more independent resistors on the substrate is the same impurity
Polysilicon thin film or shing with the same concentration of material injected
Silicon thin film, the thickness and / or the material
A multilayer body sandwiched between the first and second insulating films;
The lamp was annealed under specified heat treatment conditions.
It was formed more simultaneously. With this structure,
Easily control the temperature rise / fall characteristics and maximum temperature of each multilayer body.
Since it can be trolled, independent resistors with different resistivity
It can be manufactured easily and simultaneously on the same substrate. Ma
According to the method for manufacturing a semiconductor device of the present invention,
Polysilicon thin film with the same concentration of impurities
Single silicon thin film with different thickness and / or material
Forming a multilayer body sandwiched between the first and second insulating films
After that, the multilayer body is ramped under a predetermined heat treatment condition.
It is made to be neal. With this configuration, each multilayer
You can control the temperature rise and fall characteristics and maximum temperature of the body,
Under one lamp annealing heat treatment condition, each resistivity is different
Independent resistors on the same substrate easily and simultaneously.
Can be built.

[Brief description of the drawings]

FIG. 1 shows a monitored I of a BareSi substrate (wafer).
It is a figure which shows the temperature rise / fall characteristic (at 1050 degreeC and 10 second conditions) at the time of RA.

FIG. 2 is a schematic sectional view of a BareSi wafer sample multilayer structure.

FIG. 3 shows an example in which x =
FIG. 9 is a diagram showing the temperature rise / fall characteristics of a wafer during IRA when y = 100 nm.

FIG. 4 is a diagram illustrating a sample multi-layer structure shown in FIG.
FIG. 9 is a diagram illustrating temperature rise / fall characteristics of a wafer during IRA when y = 400 nm.

FIG. 5 is a diagram illustrating a sample multi-layer structure shown in FIG.
FIG. 9 is a diagram illustrating temperature rise / fall characteristics of a wafer during IRA when y = 200 nm.

FIG. 6 shows a sample multi-layer structure shown in FIG.
FIG. 9 is a diagram illustrating temperature rise / fall characteristics of a wafer during IRA when y = 800 nm.

FIG. 7 is a diagram showing a relationship between an impurity concentration implanted into polysilicon (poly-Si) and resistivity.

FIG. 8 is a first-half sectional view of a poly-Si resistor according to the present invention;

FIG. 9 is a cross-sectional view of the second half of the poly-Si resistor according to the present invention.

[Explanation of symbols]

Reference Signs List 1 BareSi substrate (wafer) _{2, 4, 5,} 7 SiO ₂ (thin film) 3, 6 poly-Si (thin film) 11 LOCOS oxide film 12 SiN film 13 poly-Si film 13 a poly-Si film pattern 14 SiO ₂ film 17 electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-161750 (JP, A) JP-A-63-224324 (JP, A) JP-A-3-293731 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (3)

(57) [Claims] At least two or more independent substrates on the same substrate
A semiconductor device having an upper resistor , wherein each of the resistors has the same impurity sandwiched between a first and a second insulating film;
Polysilicon thin film or single silicon
The polysilicon having a multilayer body made of a silicon thin film and constituting at least one of the resistors.
The first film sandwiching the thin film or the single silicon thin film
Or the second insulating film forms the other resistor.
The polysilicon thin film or the single silicon
The first insulating film or the second
The multilayer body was lamp-annealed under a predetermined heat treatment condition with a different thickness and / or material from the insulating film .
Characterized by being formed at the same time
Semiconductor device. 2. The semiconductor device according to claim 1, wherein the lamp annealing is performed by infrared annealing or halogen lamp annealing. 3. A process for forming a polysilicon thin film or single silicon thin film on the first insulating film, a step of performing ion implantation of a predetermined concentration in the polysilicon thin film or single silicon thin film, the polysilicon thin film or single forming a plurality of silicon pattern a silicon thin film is patterned into at least two or more sites, on the plurality of silicon pattern, a step of forming a second insulating film to form a plurality of multi-layer body, and a step of lamp annealing the plurality of multilayer bodies at a predetermined heat treatment conditions, the other silicon pattern is formed of the first insulating film or the second insulating film in at least one of the plurality of silicon pattern The first insulating film or the
A method of manufacturing a semiconductor device, wherein the thickness and / or the material of the second insulating film are different.