JP2001144258A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize mounting of a capacitance element which relaxes the concentration of electric field, after a nitride film which is used as an insulation film of capacitor is deposited, by controlling the polysilicon surface condition to reduce the degree of projection of polysilicon. SOLUTION: When doping an impurity to a polysilicon film formed on an oxide film for element isolation, a sheet resistance value of the polysilicon film is adjusted by adjusting the doping time to control roughness of the polysilicon film surface. The surface roughness can be set to 20 nm or less, and a lower sheet resistance may be assured to manufacture a highly reliable and highly accurate capacitance element, by setting the impurity doping time to 30 minutes or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called BiCMOS semiconductor device in which a MOS type semiconductor device and a bipolar transistor are formed on the same semiconductor substrate, and more particularly to a polysilicon film formed on element isolation. As a lower electrode, a nitride film as an insulating film, and an aluminum wiring as an upper electrode of a capacitor.

[0002]

2. Description of the Related Art The so-called BiCMOS manufacturing technology for forming a bipolar device and a CMOS device on the same substrate has been widely spread depending on the required performance.
The advantage of the BiCMOS technology is that analog and digital can coexist, but conversely, the number of manufacturing steps and the complexity in consideration of the element performance are becoming important issues. In particular, as for semiconductor devices for storage media devices represented by FDD and MFD, the cost of the set itself has been reduced, and the semiconductor devices are also in a fierce cost competition, and there is a strong demand for an approach for low cost. .

[0003] As one of the approaches for lowering the cost, a step of forming a buried diffusion and a step of forming an epitaxial layer, which are characteristic steps of the BiCMOS process, are omitted, and complete compatibility with CMOS is achieved. With the addition of an insulating film pattern forming step for forming a base diffusion layer and a capacitor of a bipolar transistor, a simplified NPN
There is a method of forming a semiconductor device having a built-in filter circuit so that a bipolar transistor and a high-precision capacitive element can be formed.

[0004] Hereinafter, a conventional low cost BiCM.
A particularly high-precision capacitive element in a device structure formed by the OS technology will be described.

FIG. 4 is a cross-sectional view of a BiCMOS element, in which an NMOS, a PMOS, a diffused resistor, and a capacitor are formed, and shows a state after forming an aluminum electrode of each device. FIG. 5 is a cross-sectional view in the middle of the device manufacturing process, and shows a state in which impurities are doped after a polysilicon film for a gate electrode is deposited. FIG. 6 is a cross-sectional view showing a state immediately after formation of a sidewall on a gate sidewall for the purpose of improving the reliability of a transistor in which impurity-doped polysilicon is patterned for a gate electrode and a lower electrode of a capacitor. FIG. 7 is a cross-sectional view showing a state where the CVD film is etched only in the capacitor element region after the field CVD film is subjected to a surface flattening process.

4 to 7, reference numeral 1 denotes a P-type semiconductor substrate, 2 denotes an N-type well diffusion layer, 3 denotes a P-type well diffusion layer,
Denotes a thermal oxide film for element isolation (hereinafter referred to as a LOCOS film),
Reference numeral 5 denotes a gate oxide film of a MOS transistor, 6 denotes a gate electrode and a lower electrode of a high-concentration N-type polysilicon film, 7 denotes a sidewall of a gate side wall, 8 denotes a P-type diffusion resistance layer, and 9 denotes an N-type source diffusion. Layer and drain diffusion layer, 1
0 is a P-type source diffusion layer and a drain diffusion layer, 11 is a planarization CVD film, 12 is a nitride film for forming a capacitor, 13 is an aluminum electrode, and 14 is an impurity doped into a polysilicon film and contains P (phosphorus). Compound 15 is a polysilicon film deposited by CVD before impurity doping.

[0007] The configuration and operation of the BiCMOS device element configured as described above, particularly the capacitance element, will be described below.

Since the manufacturing technique is a well-known technique, it will be briefly described. First, an N-type well diffusion layer 2 is formed on a P-type semiconductor substrate 1.
And a P-type well diffusion layer 3 are formed by a twin well method or the like, and a LO is formed in a desired element isolation region and a capacitor element formation region.
After the COS film 4 is selectively grown, a thin gate oxide film 5 is grown by thermal oxidation, and then a non-doped polysilicon film 15 is deposited to a thickness of about 400 nm. Next, in this state, the compound 14 containing P (phosphorus) was heated at 900 ° C to 1 ° C.
The polysilicon film 15 is supersaturated by heat treatment at about 000 ° C. and is doped to such an extent that impurities do not diffuse into the semiconductor substrate through the thin gate oxide film by the subsequent heat treatment so that the sheet resistance of the polysilicon film becomes 4Ω or less. Is processed. The steps up to here are the steps shown in the sectional view of FIG.

Next, after processing a desired pattern as a gate electrode of a transistor and a lower electrode of a capacitor by processing a polysilicon film by photolithography and dry etching techniques, a TEOS film or the like is deposited by a CVD method, and the entire surface is deposited. Dry etching is performed to form sidewalls 7. FIG. 7 is a sectional view showing the state up to now.

Next, after forming a desired resist pattern, ions of corresponding impurities are implanted to form a P-type diffusion resistance layer 8, an N-type source diffusion layer and a drain diffusion layer 9, a P-type source diffusion layer and a drain diffusion layer. Form 10. Thereafter, in order to flatten the surface, for example, a BPSG film or the like, which is a CVD film containing B (boron) and P (phosphorus), is deposited, and a flattening CVD film 11 is formed on the surface reflowed by a heat treatment at about 900 ° C. Form. After that, only the region N necessary as a capacitor is flattened by dry etching technology.
The film 11 is etched. This state is a sectional view shown in FIG.

Thereafter, a nitride film for forming a capacitor is formed on the entire surface by CV.
After the growth by the method D, the nitride film is processed into a desired pattern, and thereafter, a contact window of each device is opened, a wiring material is adhered to the semiconductor substrate by aluminum sputtering, and then patterned into a desired shape. Thus, the aluminum electrode 13 is formed, and the transistor, the diffusion resistance, and the capacitor are formed on the same substrate. Thus, an element having the configuration shown in FIG. 4 is manufactured.

The capacitive element constructed by such a manufacturing method has a structure in which a polysilicon film is provided as a lower electrode on an oxide film for element isolation, and a nitride film and an aluminum electrode are provided thereon.

[0013]

However, in the structure of the conventional semiconductor device, in order to realize a demand for miniaturization of the element or shrinkage and high precision of the semiconductor element, the lower electrode must be replaced with the gate electrode of the MOS transistor. When a nitride film is deposited on a doped polysilicon film, the polysilicon film is exposed at least twice or more and is damaged by dry etching or the like. As a result, the roughness of the surface state in the polysilicon film becomes large.

In a capacitor structure in which an aluminum electrode is formed by growing a nitride film in this state, when an electric field is formed as an actual device, an electric field concentration occurs at uneven portions due to the surface roughness of the lower electrode, and the electric field concentration is higher than the actual use state. Is applied to the local portion of the nitride film, which not only significantly reduces the life of the capacitor, but also increases the variation in capacitance value because the thickness of the nitride film is not stable. Particularly, in order to increase the capacitance value per unit area, it is necessary to make the nitride film thinner, so that the reliability of the element and the accuracy of the capacitance value are further deteriorated.

If the thickness of the nitride film cannot be reduced, especially in the case of a semiconductor device that frequently uses a filter circuit,
The capacitance element occupying the chip becomes so large that it cannot be ignored. As a result, chip shrink cannot be realized, and if the variation cannot be suppressed, a high-performance semiconductor integrated circuit cannot be expected.

The present invention has been made to solve the above-mentioned conventional problems, and it is possible to reduce the number of protrusions of polysilicon and to integrate a large-capacity capacitive element having excellent reliability.
It is an object of the present invention to provide a method for manufacturing a semiconductor device applicable to iCMOS.

[0017]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a polysilicon as a gate electrode of a CMOS transistor on an oxide film for isolating a CMOS transistor on a semiconductor substrate; Depositing a film with a thickness of about 250-450 nm;
Next, a step of doping impurities into the polysilicon film to reduce the resistance value, and then forming a source / drain diffusion layer of the CMOS transistor, depositing a CVD film over the entire surface, and performing a reflow process, Flattening a film, then etching the CVD film in the capacitive element region on the polysilicon film, depositing a thin nitride film of 45 nm or less and patterning it into a desired shape; A step of forming a contact window by etching a film; and forming an aluminum electrode on the nitride film and the contact window to form a CMOS transistor and a capacitor. 950-1000 ° C
The surface roughness of the polysilicon film is controlled by controlling the resistance value of the polysilicon film to 4.0 Ω or more by adjusting the doping time when the heat treatment is performed by the method described above. The electric field concentration applied as a capacitive element to a nitride film deposited on a polysilicon film having a controlled surface roughness can be reduced,
Even when a thin nitride film is used, a highly reliable capacitive element can be easily mounted simultaneously with the formation of a CMOS device element.

Further, according to the method of manufacturing a semiconductor device of the present invention, a step of forming an oxide film for element isolation of a CMOS transistor on a semiconductor substrate and performing an annealing process at 950 to 1000 ° C. Depositing a polysilicon film having a thickness of about 250 to 450 nm by growing the polysilicon film by a CVD method while doping impurities, and depositing a CVD film over the entire surface after forming source and drain diffusion layers of a CMOS transistor. Performing a reflow process for planarization;
After the D film is etched, a step of depositing a thin nitride film and patterning it into a desired shape, and a step of etching a predetermined portion of the CVD film to form a contact window are provided. According to this method, the amorphous silicon is grown by the CVD method while doping impurities, whereby the grain size can be reduced by suppressing the growth of the grains. As a result, the use of an electrode having a reduced surface roughness of the polysilicon film enables mounting of a highly reliable capacitive element.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a correlation diagram of the impurity doping time of the polysilicon film and the sheet resistance and surface roughness of the polysilicon film in the semiconductor device manufactured by the first embodiment of the semiconductor device manufacturing method according to the present invention. FIG. 2 is an enlarged view of a capacitive element portion obtained by controlling the sheet resistance of the polysilicon film in the present embodiment, and FIG. 3 is an explanatory view showing an enlarged capacitive element portion having a lower electrode formed under conventional conditions. is there.

The respective structures in the process of forming the nitride film are the same as those described with reference to FIGS. 4 to 7, and the same members as those already described are denoted by the same reference numerals and detailed description is omitted. I do.

The structure of the high-precision capacitive element according to the present embodiment will be described below with reference to FIGS. 4 to 7 on the assumption that the structure is applied to a BiCMOS manufacturing method.

First, phosphorus ions are implanted into the P-type semiconductor substrate 1 and boron ions are implanted into another portion, and then a heat treatment at a relatively high temperature (about 1200 ° C.) is performed. A diffusion layer 2 is formed, and a well region is formed by a so-called twin well method in which a P-type well diffusion layer 3 is formed at a location where boron is implanted. Next, the region where the thin thermal oxide film and the nitride film are grown is left as an element formation region, and the other region is removed by etching the nitride film. Then, after growing a LOCOS film (thick oxide film for element isolation) 4 by oxidation at about 1000 ° C., the nitride film is removed by wet processing. As shown in FIG. 5, the LOCOS film 4 distinguishes the element formation region from the other. After the wet treatment of the nitride film, the thin thermal oxide film in the element formation region is completely removed by a slight wet etching, and after a cleaning treatment, the thin gate oxide film 5 is removed by an oxidation treatment at 900 ° C. to 250-450.
nm (about 400 nm in this example).
A non-doped polysilicon film 15 is grown by a continuous process by a CVD method.

Thereafter, a step of doping the polysilicon film 15 with impurities is performed. In this example, an impurity 14 containing P (phosphorus), for example, POCl ₃ or PH ₃ is used,
The impurity 14 is doped into the non-doped polysilicon film 15 by a heat treatment at 950 ° C. to 1000 ° C. as shown in FIG. Specifically, when PH ₃ is used as an impurity, heat treatment is performed at about 1000 ° C.
_When using ₃ , heat treatment is performed at about 950 ° C.

This process is an essential step for reducing the resistance in order to use the polysilicon film as a gate electrode and a wiring. Generally, however, the doped polysilicon film is doped with impurities so as to be in a supersaturated state. Then, the impurity atoms in the polysilicon are almost stable in the polysilicon film and there is no change due to thermal stress or the like.

In the impurity doping process of this embodiment, there is a correlation between the doping time and the sheet resistance of the polysilicon film and the surface roughness of the polysilicon film as shown in FIG. The surface roughness is 20 nm or more at a sheet resistance value of 4 Ω or less, which has been standardized so far, and the conventional polysilicon film 6-b as shown in FIG. I have. For this reason, when a voltage is applied to the aluminum electrode 13, the electric field concentrates at that location because the amount of unevenness is large, as shown at B in FIG. On the other hand, in the present embodiment, based on the correlation shown in FIG. 1, the doping time is adjusted to control the sheet resistance of the polysilicon film to 4 Ω or more and the surface roughness to 20 nm or less, as shown in FIG. It is possible to form a polysilicon film 6-a having relatively few surface irregularities.

Next, the polysilicon films for the gate electrode and the lower electrode of the capacitor are processed into desired patterns. After the electrodes are formed, the entire surface is formed by CVD for spacer formation.
After the film 7 is grown, dry etching is performed to form sidewalls on the side walls of the gate electrode and the lower electrode as shown in FIG.

Next, the P-type diffusion resistance layer 8, the N-type source and drain diffusion layers 9, and the P-type source and drain diffusion layers 10 are formed by ion implantation using a desired resist pattern as a mask. , All over BPSG
A CVD film such as a film is deposited, and thereafter, a planarized CVD film 11 is formed by a reflow process at 900 ° C. In this state, only the region N where the capacitor is to be formed is etched as shown in FIG.

Next, after growing the thinned nitride film 12 on the entire surface of the nitride film 12 serving as a capacitor insulating film, dry etching is performed so as to leave only a desired capacitor element formation region as shown in FIG. . Then, after opening the contact window of each device, the aluminum electrode 13 is formed by using techniques such as sputtering, photolithography, and dry etching.

As described above, in this embodiment, the polysilicon film 6 serving as the lower electrode is formed before the growth of the capacitive nitride film.
In the dry etching at the time of forming the sidewall shown in FIG. 6 and the dry etching of the capacitor forming region shown in FIG. 7, the surface thereof is damaged by the etching.
Therefore, the surface unevenness of the lower electrode at the time of impurity doping is further increased. Therefore, when the lower electrode is used as a lower electrode, controlling the surface unevenness makes it possible to increase the unit capacitance and obtain a highly accurate capacitive element. Can be formed.

Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described. Since the method of the second embodiment has the same steps as those of the first embodiment, the characteristic steps will be described.

That is, in the second embodiment, in forming the polysilicon film 15 shown in FIG. 5, instead of the polysilicon film growing method at about 600 ° C. as in the first embodiment,
An amorphous silicon film at 00 to 540 ° C. is deposited by a CVD method, and at the same time, an amorphous silicon film is deposited while being doped with an impurity, thereby forming a conductive film.

By adopting the film forming method, the thermal history of the conductive film is only 500 to 540 ° C. as described above, and the impurity doping in the process of the first embodiment is 9 to 540 ° C.
Heat treatment at 50 to 1000 ° C. is not required. In the case of using this film forming method, it is necessary to perform annealing at the time of impurity doping at 950 to 1000 ° C. at the time of forming an oxide film before forming an amorphous silicon film to add a similar heat history. It is. Steps other than this step are performed in the same manner as the steps described in the first embodiment.

In the second embodiment, since the film is in an amorphous state at the time of film formation, there is no grain boundary in the film itself.
Since the size of the grain boundary is changed to polysilicon by a subsequent heat treatment, the size of the grain boundary can be suppressed to a very small growth since the subsequent heat treatment is 900 ° C. or less. As a result, similarly to the first embodiment, a polysilicon film having less surface irregularities (FIG. 2)
The lower electrode 6-a) of the polysilicon film can be formed, and the concentration of the electric field can be reduced by using this polysilicon film as the lower electrode of the capacitor.

[0035]

As described above, according to the method of manufacturing a semiconductor device of the present invention, in the impurity doping for lowering the resistance value of the capacitor using the same polysilicon film as the gate electrode, the doping is performed. By controlling the time or growing the polysilicon film in an amorphous state, the sheet resistance of the polysilicon film can be determined and the surface roughness of the polysilicon film can be suppressed, resulting in an increase in reliability. An excellent capacitive element can be easily formed, can be easily incorporated into a CMOS transistor manufacturing process, can be applied to an analog / digital mixed BiCMOS field, and has excellent performance. A semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a correlation between an impurity doping time, a sheet resistance of a polysilicon film and a surface roughness thereof according to a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view of a boundary portion between a polysilicon film and a nitride film of the capacitive element according to the first embodiment of the present invention.

FIG. 3 is an enlarged cross-sectional view of a boundary portion between a polysilicon film and a nitride film of a conventional capacitive element.

FIG. 4 is a cross-sectional view of a BiCMOS device to which a capacitor is added for explaining a conventional example and a first embodiment of the present invention;

FIG. 5 is a cross-sectional view of a BiCMOS device during a manufacturing process when a capacitor is added for explaining a conventional example and a second embodiment of the present invention;

FIG. 6 is a cross-sectional view in the middle of a manufacturing process of a BiCMOS device when a capacitor is added for explaining a conventional example and a second embodiment of the present invention;

FIG. 7 is a cross-sectional view of a BiCMOS device during a manufacturing process when a capacitor is added for explaining a conventional example and a second embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 P-type semiconductor substrate 2 N-type well diffusion layer 3 P-type well diffusion layer 4 LOCOS film (oxide film for element isolation) 5 Gate oxide film 6 Polysilicon film for gate electrode and capacitor lower electrode 6-a Impurity amount 6-b Conventional electrode of polysilicon film 7 Gate electrode side wall 8 P-type diffusion resistance layer 9 N-type source / drain diffusion layer 10 P-type source / drain diffusion layer 11 Flat CVD film 12 Nitride film for capacity formation 13 Aluminum electrode 14 Compound containing P (phosphorus) 15 Polysilicon film before impurity doping A Surface irregularities of polysilicon film in the present invention B Surface of polysilicon film in conventional example Uneven part

Claims (4)

[Claims] A polysilicon film as a gate electrode of a CMOS transistor is formed on an oxide film for isolating a CMOS transistor on a semiconductor substrate.
A step of depositing a film having a thickness of 450 nm, a step of lowering the resistance value by doping the polysilicon film with impurities, and a step of forming a source / drain diffusion layer of the CMOS transistor and then forming a CVD film on the entire surface A step of flattening the CVD film by performing a reflow process after the deposition, and a step of flattening the CVD film in the capacitive element region on the polysilicon film.
After the D film is etched, a step of depositing a thin nitride film of 45 nm or less and patterning it into a desired shape, and a step of etching the CVD film to form a contact window are further provided. In the case where a CMOS transistor and a capacitor are formed by forming an aluminum electrode on the contact window, the doping time when the impurity doping of the polysilicon film is heat-treated at 950 to 1000 ° C. is adjusted. A method for manufacturing a semiconductor device, comprising: controlling the surface resistance of a polysilicon film by controlling the resistance value of the film to 4.0 Ω or more. 2. The method according to claim 1, wherein the polysilicon film has a thickness of about 250 to 45.
2. The method according to claim 1, wherein the semiconductor device has a thickness of 0 nm and is doped so that the impurities are saturated. 3. The method according to claim 1, wherein a surface roughness of the polysilicon film is limited by controlling an impurity doping time of the polysilicon film so that an average value of the roughness is 20 nm or less. Item 2. A method for manufacturing a semiconductor device according to Item 1. 4. A step of forming an oxide film for element isolation of a CMOS transistor on a semiconductor substrate and performing an annealing process at 950 to 1000 ° C., and forming an amorphous polysilicon film on the oxide film by doping impurities. CVD while
Depositing a film having a thickness of about 250 to 450 nm by growing by a method, and depositing a CVD film on the entire surface after forming source and drain diffusion layers of the CMOS transistor;
Performing a reflow process for planarization, etching the CVD film in the capacitor element region, depositing a thin nitride film and patterning the nitride film into a desired shape; A method for manufacturing a semiconductor device, comprising a step of forming a contact window by etching.