JP3545229B2 - Semiconductor storage device and method of manufacturing the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a transistor structure having a stacked gate electrode in a nonvolatile memory and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, there are the following technologies in such a field.
[0003]
3A and 3B are configuration diagrams of a conventional semiconductor memory device. FIG. 3A is a plan view of the semiconductor memory device, and FIG. 3B is a cross-sectional view taken along line AA 'of FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor memory device.
[0004]
As shown in FIG. 3A, in this semiconductor memory device, a floating gate 2 and a control gate 3 of a transistor are formed on an active region 1.
[0005]
Further, as shown in FIG. 3B, a field oxide film 12 is formed on a silicon substrate 11, and a floating gate electrode 14 of the transistor is disposed via a first gate oxide film 13. Further, the control gate electrode 16 of the transistor is arranged via a second gate oxide film 15 formed on the floating gate electrode 14.
[0006]
Hereinafter, a manufacturing process of the semiconductor memory device will be described with reference to FIG. Here, an N-channel type will be described.
[0007]
(1) First, as shown in FIG. 4A, a separation pattern is formed on a silicon substrate 21 using a normal LOCOS technique or the like, and a field oxide film 22 is formed.
[0008]
(2) Thereafter, as shown in FIG. 4B, the first gate oxide film 23 is formed by ordinary thermal oxidation, and the first polysilicon film is doped with N ⁺ by CVD (Chemical Vapor Deposition). 24 are formed on the entire surface.
[0009]
(3) Next, as shown in FIG. 4C, the first polysilicon film is patterned by photolithography to form the floating gate electrode 25.
[0010]
(4) Next, as shown in FIG. 4D, a second gate oxide film 26 is formed on the floating gate electrode 25 by ordinary thermal oxidation, and a second polysilicon film doped with N ⁺ by CVD. 27, a W silicide film 28 is formed on the entire surface.
[0011]
(5) Although not shown, patterning is performed by photolitho etching to form a control gate electrode, arsenic or phosphorus is implanted by ion implantation using the control gate electrode as a mask, and an N ⁺ diffusion layer is formed on the silicon substrate 21. A desired transistor structure is obtained by forming the transistor in a self-aligned manner.
[0012]
[Problems to be solved by the invention]
However, such a conventional transistor having a stacked electrode structure is relatively easy to reduce the memory cell size compared to a DRAM or an SRAM cell because a capacitor and a plurality of transistors are not required. On the other hand, the structure is advantageous in that it can be formed, but the alignment accuracy of each layer with respect to the base is poor. In addition, the stacked electrode structure has a problem that the shape in the vertical direction is greatly changed, which causes a decrease in cell yield due to a defective gate electrode shape.
[0013]
In order to prevent this, it is necessary to apply a buried oxide film technology such as STI (Shallow Trench Isolation) to element isolation to reduce the step structure from the base, but the process is complicated and the cost increases. In addition, if the oxide film used for isolation is not sufficiently buried, the filament that remains when forming the gate electrode remains on that part, causing a short circuit failure. There was a disadvantage that it could not be obtained.
[0014]
The present invention eliminates the above problems, facilitates patterning of the floating gate electrode itself, and also improves patterning performance and prevents a decrease in wiring yield in patterning an upper layer such as a control gate electrode formed later. It is an object of the present invention to provide a semiconductor memory device and a method of manufacturing the same.
[0015]
[Means for Solving the Problems]
The present invention, in order to achieve the above object,
[1] In the semiconductor memory device, a part on the active side is removed and embedded in an element isolation insulating film that directly insulates a gate electrode and a step formed by the active region and the element isolation insulating film. A first gate electrode formed so that its height is equal to or less than the height of the element isolation insulating film; and a second gate electrode further selectively formed on the first gate electrode. Are provided.
[0016]
[2] In a method of manufacturing a semiconductor memory device, a step of selectively etching away a part of an element isolation insulating film that directly insulates a first gate electrode, and a step formed by an active region and the element isolation insulating film. Forming a first gate electrode so as to be buried in a portion and having a height equal to or lower than the height of the element isolation insulating film; and further selecting a second gate electrode on the first gate electrode. And a step of forming the target.
[0017]
[3] In the semiconductor memory device, the semiconductor device extends over a step formed by an active region and an element isolation insulating film that directly insulates the first gate electrode, and has a height equal to the height of the element isolation insulating film. A first gate electrode formed below and a second gate electrode further selectively formed on the first gate electrode are provided.
[0018]
[4] In the method for manufacturing a semiconductor memory device, a step of forming a first gate electrode over a step formed by an element isolation insulating film that directly insulates the first gate electrode and an active region; Polishing and removing only the first gate electrode portion present on the element isolation insulating film, and forming the remaining first gate electrode to have a height equal to or less than the height of the element isolation insulating film; And a step of selectively forming a second gate electrode on the first gate electrode.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail.
[0020]
FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention. Here, an N-channel type will be described.
[0021]
(1) First, as shown in FIG. 1A, a pad oxide film (not shown) is formed on a silicon substrate 101 by a 50-500 ° thermal oxidation method. The pad oxide film can be oxidized in an oxygen atmosphere at 700 to 900 ° C. in several tens of minutes. Thereafter, a nitride film (not shown) is formed at a thickness of 500 to 3000 ° by a CVD method. Thereafter, a resist (not shown) is applied, a separation pattern is formed by the photolithography method using the resist, and the nitride film is etched using the resist as a mask. Thereafter, the resist is removed, and a field oxide film (element isolation insulating film) 102 is formed.
[0022]
(2) Next, as shown in FIG. 1B, the field oxide film 102 is thermally oxidized in a wet atmosphere of 800 to 1000 ° C. to form a thickness of 3000 to 10000 °. After removing the nitride film and the pad oxide film, a pattern slightly smaller than the separation pattern shown in FIG. 1A is formed by a resist again by the photolithography method, and a part 102A of the field oxide film 102 is formed using the resist as a mask. Is anisotropically etched.
[0023]
(3) Then, as shown in FIG. 1C, a first gate oxide film 103 is formed by a thermal oxidation method at 40 to 200 degrees, and a first polysilicon film 104 serving as an electrode is formed to a thickness of 1000 to 3000 degrees. It is formed by the CVD method. The impurity is doped with phosphorus or arsenic by 1 to 6 × 10 ²⁰ cm ⁻³ by thermal diffusion or ion implantation.
[0024]
(4) Thereafter, as shown in FIG. 1D, the first polysilicon film 104 is patterned by photolithography and etching to form a floating gate electrode 105. At this time, since the end of the floating gate electrode 105 is sufficiently flattened, filament defects do not occur at the time of electrode formation, and there is also a flattening effect for formation of an upper layer pattern. It can be expected that the wiring yield will be improved. It is important here that the height of the floating gate electrode 105 be equal to or less than the height of the field oxide film 102.
[0025]
(5) Thereafter, as shown in FIG. 1 (e), thermal oxidation is performed under a relatively high temperature condition of 900 to 1000 ° C. in a dry oxygen atmosphere to grow a thin oxide film by 50 to 100 °, and silicon is formed by a CVD method. A second gate oxide film is formed by growing a nitride film on the entire surface at 100 to 200 ° and further performing thermal oxidation at a relatively low temperature of 800 to 900 ° C. in a wet oxygen atmosphere to grow a thin oxide film at 50 to 100 °. 106 is formed.
[0026]
Finally, a second polysilicon film 107 serving as an electrode is formed by a CVD method to a thickness of about 1000 to 3000 °, and the impurity is doped with phosphorus or arsenic by 1 to 6 × 10 ²⁰ cm ^{− by} thermal diffusion or ion implantation. ^{After three} doping, a W silicide film 108 is formed by a CVD method.
[0027]
(6) Although not shown, the above-mentioned second polysilicon film 107 and W silicide film 108 are patterned by photolithography and etching to form a control gate electrode, and ion implantation is carried out in a self-aligned manner using this as a mask. As a result, arsenic or phosphorus is implanted at 1 to 10 × 10 ¹⁵ cm ⁻² to form an N ⁺ diffusion layer, thereby completing the formation of the stacked transistor. Thereafter, the semiconductor storage device according to the present invention is completed by forming each electrode lead-out wiring by a known technique.
[0028]
With the configuration as described above, according to the first embodiment,
(1) A floating gate electrode for a transistor, which is conventionally formed so as to be straddled over the active region and the upper part of the field oxide film, is formed so as to be buried in the active region in a portion which becomes a valley of the field oxide film. Since the step in the direction can be reduced, patterning of the floating gate electrode itself becomes easy, and patterning performance can be expected to improve in the patterning of the upper layer such as the control gate electrode to be formed later, and the reduction in wiring yield is prevented. Can be.
[0029]
(2) Since the control gate electrode is formed by embedding a pseudo electrode material in the active region, a self-aligned process in the gate / active region can be realized by applying this embodiment.
[0030]
(3) In the manufacturing method, the LOCOS method, which is a conventional technology, can be applied to the element isolation process, and no new process technology is required, and the stability of the manufacturing process and the electrical reliability of the transistor are maintained. Can be.
[0031]
FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor memory device according to a second embodiment of the present invention. Here, an N-channel type will be described.
[0032]
(1) First, as shown in FIG. 2A, a pad oxide film (not shown) is formed on a silicon substrate 201 by a 50-500 ° thermal oxidation method. This pad oxide film can be oxidized in an oxygen atmosphere at 700 to 900 ° C. for several tens of minutes. Thereafter, a nitride film (not shown) is formed at a thickness of 500 to 3000 ° by a CVD method. Thereafter, a resist (not shown) is applied, a separation pattern is formed by the photolithography method using the resist, and the nitride film is etched using the resist as a mask. Thereafter, the resist is removed, and a field oxide film 202 is formed.
[0033]
(2) Next, as shown in FIG. 2B, after forming a field oxide film 202 on a silicon substrate 201, a first gate oxide film 203 is formed by 40 to 200 [deg.] By thermal oxidation to form an electrode and A first polysilicon film 204 is formed by a CVD method with a thickness of about 1000 to 3000 °. The impurity is doped with phosphorus or arsenic by 1 to 6 × 10 ²⁰ cm ⁻³ by thermal diffusion or ion implantation.
[0034]
(3) Next, as shown in FIG. 2C, the first polysilicon film 204 is polished and removed to the top of the field oxide film 202 by a CMP (Chemical Mechanical Polish) method.
[0035]
(4) Next, as shown in FIG. 2D, the first polysilicon film 204 is patterned by photolithography to form a floating gate electrode 205. At this time, since the end portion of the floating gate electrode 205 is sufficiently flattened, a filament effect does not occur at the time of forming the electrode, and the flattening effect also exists for the formation of the upper layer pattern. It can be expected that the wiring yield will be improved.
[0036]
(5) Thereafter, as shown in FIG. 2E, thermal oxidation is performed under a relatively high temperature condition of 900 to 1000 ° C. in a dry oxygen atmosphere to grow a thin oxide film by 50 to 100 °, and silicon is formed by a CVD method. A second gate oxide film is formed by growing a nitride film on the entire surface at 100 to 200 ° and further performing thermal oxidation at a relatively low temperature of 800 to 900 ° C. in a wet oxygen atmosphere to grow a thin oxide film at 50 to 100 °. Step 206 is formed.
[0037]
Finally, a second polysilicon film 207 serving as an electrode is formed to a thickness of about 1000 to 3000 ° by CVD, and impurities are doped with phosphorus or arsenic by thermal diffusion or ion implantation at 1 to 6 × 10 ²⁰ cm ^{−. After three} doping, a W silicide film 208 is formed by a CVD method.
[0038]
Hereinafter, although not shown, if each electrode lead-out wiring is formed by a known technique, the semiconductor device according to the present invention is completed.
[0039]
With this configuration, according to the second embodiment,
(1) Conventionally, a floating gate electrode for a transistor, which is formed so as to be stacked over an active region and an upper portion of a field oxide film, is replaced with a field oxide film except for a portion near the active region which is a valley of the field oxide film. Unnecessary parts at the top are removed to reduce the vertical steps, so patterning of the floating gate electrode itself is facilitated, and patterning performance is improved in patterning of upper layers such as the control gate electrode that is formed later. It is possible to prevent a decrease in yield and wiring yield.
[0040]
(2) Since the control gate electrode is formed by embedding a pseudo electrode material in the active region, a self-aligned process in the gate / active region can be realized by applying this embodiment.
[0041]
(3) In the manufacturing method, the LOCOS method, which is a conventional technique, can be applied to the element isolation process, and no new process technology is required, so that the stability of the manufacturing process and the electrical reliability of the transistor are the same as those of the conventional method. Can be maintained.
[0042]
In the above description, a P-type silicon substrate has been described as an example, but the same effect can be obtained by using an N-type silicon substrate. The substrate and the electrode material are not limited to the silicon substrate and the polysilicon / W silicide, and other substrates and electrode materials can be used sufficiently.
[0043]
Further, the present invention is not limited to the above embodiments, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
[0044]
【The invention's effect】
As described above, according to the present invention,
(A) According to the first or second aspect of the present invention, the floating gate electrode is formed so as to be buried in the active region serving as the valley of the field oxide film so that the vertical step can be reduced. The patterning itself is facilitated, and patterning performance can be expected to be improved in patterning an upper layer such as a control gate electrode to be formed thereafter, and a decrease in wiring yield can be prevented.
[0045]
(B) According to the third or fourth aspect of the present invention, the floating gate electrode is left only at a portion near the active region which is a valley of the field oxide film, and an unnecessary portion above the field oxide film is removed to remove the vertical step. , The patterning of the floating gate electrode itself is facilitated, and patterning performance can be expected to be improved in the patterning of an upper layer such as a control gate electrode to be formed later, and a reduction in wiring yield can be prevented. .
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 3 is a configuration diagram of a conventional semiconductor memory device.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor memory device.
[Explanation of symbols]
101, 201 Silicon substrate 102, 202 Field oxide film (element isolation insulating film)
102A Anisotropically etched part of field oxide film 103, 203 First gate oxide film 104, 204 First polysilicon film 105, 205 Floating gate electrode 106, 206 Second gate oxide film 107, 207 2 polysilicon films 108, 208 W silicide film

Claims (4)

In a semiconductor memory device in which an active region is defined on the substrate surface by an element isolation insulating film provided on the substrate surface,
Wherein the said element isolation insulating film that defines the end of the channel width direction of the active region, the pre-Symbol removing an end portion of the active region side projecting from the substrate surface in a configuration in which a step is formed,
A first oxide film on the active region; a first oxide film formed on the first oxide film, having a height equal to or less than a height of the device isolation insulating film, and a step portion of the device isolation insulating film; A first gate electrode formed by patterning an electrode material so as to be separated from the first gate electrode; and an electrode material formed on the patterned first gate electrode via a second oxide film. A second gate electrode formed by patterning
A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein the patterning for forming the first and second gate electrodes is performed using a photolithographic etching method. In a method for manufacturing a semiconductor memory device, an active region is defined on a surface of a substrate by an element isolation insulating film provided on the surface of the substrate.
The device isolation insulating film that defines the end of the channel width direction of the active region, a step of providing a step to remove the end portion of the active region side projecting from front Stories substrate surface,
Providing a first oxide film on the active region;
In order to form a first gate electrode, an electrode material is provided so as to cover the first oxide film, and has a height equal to or less than the height of the element isolation insulating film. Patterning the electrode material so as to be spaced apart from the step portion of,
Providing a second oxide film so as to cover the patterned electrode material;
Providing an electrode material over the second oxide film to form a second gate electrode, and patterning the electrode material;
A method for manufacturing a semiconductor memory device, comprising: 4. The method according to claim 3, wherein patterning performed to form the first and second gate electrodes is performed using a photolithographic etching method.

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