JP3170048B2 - ATM test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (asynchronous transfer).
The present invention relates to an ATM test system as a transmission line test system performed by measuring a bit error rate, a cell loss ratio, and a cell mixing ratio in a cell transmission line according to a mode.

[0002] It goes without saying that a transmission path includes a transmission device and an exchange.

[0003]

2. Description of the Related Art The ATM mode is a communication system for providing various communications from low-speed data to high-speed image communication in a unified and economical manner. Information to be transmitted is divided into fixed-length blocks. It is transmitted in a transmission format of a cell to which a destination called a header is added.

A network using the ATM mode has a problem that bit errors, cell loss, and cell mixing occur during transmission as inherent phenomena.

[0005] Here, the loss means that the cell disappears somewhere and disappears, and the mixing means that the cell comes into the cell from another place.

[0006] The ATM test system measures the number of error bits, the number of lost cells, the number of mixed cells, and the like in a transmission line, thereby conducting a continuity test for setting a new virtual path and a new virtual channel in an ATM network. This is a method for performing a characteristic test whether the virtual channel satisfies the quality and a fault location isolation test for specifying a failure location at the time of a failure such as a transmission path.

In the ATM mode, the CCITT recommendation
As described in 1.610, OAM (Operation Administration and Maintenance)
ance) Define the cell to achieve the required function.

As prior art in this field, as well-known documents, “Kanayama, et al .:“ Study of virtual path test method in ATM network ””, Proceedings of the 1992 IEICE Spring Conference,
B-726 "has an ATM test method.

FIG. 13 shows a conventional technique for realizing this.
1 is a schematic explanatory diagram of an ATM test system according to the present invention. In FIG.
Here, 10 is the test cell insertion point, 11 is the test cell detection
Measurement points, 12 indicates a test between devices, 13 indicates a test between multiple devices
You.

In this report, an OAM cell having a pseudo random pattern for testing and a serial number is defined for testing.

In the following, the OAM cell used for this test is simply called a test cell.

As shown in FIG. 13, by arbitrarily specifying a test cell insertion point 10 and a test cell detection / measurement point 11, an arbitrary test section such as an inter-device test 12 and a multi-device test 13 can be obtained. Can transmit and receive test cells.

At the test cell detection / measurement point 11, the number of erroneous bits, the number of lost cells, and the number of mixed cells are measured using the test pattern and the serial number mounted on the test cell, whereby any transmission in the ATM network is performed. This is a way to test roads.

[0014]

However, the known document "Kanayama et al .:" Study of Virtual Path Test Method in ATM Network ", Proceedings of the 1992 IEICE Spring Conference, B-726" describes the number of error bits. It mentions the necessity of measuring the number of lost cells and the number of mixed cells, but does not show a specific test processing algorithm.

The major problems to be solved in realizing the test processing algorithm include the following.

1) A method for identifying that a test cell has been lost.

A method for detecting the number of test cells lost at that time.

2) A method for specifying that another cell is garbled and mixed into the test cell.

A method for detecting the number of other cells mixed in at that time.

For example, when a test cell loss or other cell contamination occurs, it must be detected, and it must be specified whether a cell loss or contamination has occurred.

Furthermore, the number must be accurately detected and counted.

3) A method for accurately measuring erroneous bits during the test.

For example, when other cells are mixed, a large number of error bits are generated, but these bits should not be counted as the number of error bits.

The object of the present invention is to focus on these problems,
An object of the present invention is to provide an ATM test method having an efficient test processing algorithm for accurately measuring the number of error bits, lost cells, and mixed cells generated during the test.

[0025]

Means for Solving the Problems The above problems have been solved and the present invention
In order to achieve the object of the present invention, the present invention provides a test cell in which a test PN pattern is divided into several parts, and a test cell in which a serial number and an error detection and correction code are added to the test cell. In an ATM test system in which cells are transmitted from a transmitting side to a transmission line in an ATM (asynchronous transfer) mode in that order, and the test cells are received or monitored, a test cell detecting means is used.
(101) and reference PN pattern generation means (102)
And the comparing means (103) and the out-of-synchronization detecting means (10
4) , a reception test cell number counter (301) , a serial number error detection and correction unit (302), and a determination unit (105)
, An error bit counter (106) , a lost cell counter (107) , and a mixed cell counter (108) .

The test cell detecting means (101) includes a transmission line
(100) Delimited test PN sent over
A test cell on which the pattern is mounted is detected from the transmission path (100) .

For referencePNPattern generation means(102)
Is the test cell detecting means(101)Detected by
Synchronization that matches bit-by-bit with the pattern mounted on the cell
For referencePNGenerate patterns.

[0028] By comparing means (103), a PN pattern reference generated by the reference PN pattern generating means (102), compares the mounting pattern in the cell for each bit.

The out-of-synchronization detecting means (104) includes a reference to a comparison result of the comparing means (103), mounted with the generated reference PN pattern into the cell by the reference PN pattern generating means (102) pattern when There rate matching is equal to or less than a predetermined value, means for determining that the synchronization of the both patterns is out, and the reference PN pattern synchronized to the mounting pattern again to the cell to said reference PN pattern generating means Means for instructing the generation of

The out-of-synchronization detecting means (104)
Can stop the operation of the error bit counter (106) when the two patterns are out of synchronization.

The discriminating means (105) is provided in the reference PN pattern generating means (102) instructed by the out-of-synchronization detecting means (104) to generate a reference PN pattern synchronized with the pattern mounted on the cell. It is monitored whether a reference PN pattern synchronized with the pattern mounted on the cell is obtained again within a certain period.

The reception test cell number (SNR) counter (30
1) counts the number of cells detected by the test cell detecting means (101) .

A serial number (SN) error detecting and correcting means (30)
2) using an error detection / correction code mounted on the cell to check whether there is an error with respect to the serial number of the cell.

Here, the error of the serial number indicates a case where the error occurring in the serial number cannot be corrected even by using the error detection and correction code.

Further, the discriminating means (105) calculates the serial number of the cell determined to be error-free by the serial number (SN) error detection and correction means (302), the received test cell number (SNR) counter value, Can monitor the difference.

An error bit counter (106) counts mismatch bits of the two patterns obtained from the comparison result .

The lost cell counter (107) counts the number of lost cells obtained as a result of the determination means (105) .

The mixed cell counter (108) is provided with the discriminating means (105) or the out-of-synchronization detecting means (1).
04), the number of mixed cells obtained is counted .

Therefore, the structure of the present invention is as follows:
is there. That is, the test PN pattern is divided into several parts.
The test cells carrying each one of
It transmits to the transmission line in the ATM mode and receives the test cell.
In ATM test method is performed by monitoring, the test cell
For detecting test cell from transmission line (100)
(101) and the test cell detecting means (101)
Matches the pattern mounted on the detected cell in bit units
PN pattern for generating a reference PN pattern
Turn generating means (102) and the reference PN pattern generator
PN pattern for reference generated by generating means (102)
And the cell detected by the test cell detecting means (101).
Comparison method that compares the pattern mounted on the
The result of the comparison between the step (103) and the comparing means (103)
And the reference PN pattern is the cell
Is less than a certain value.
When the two patterns are out of synchronization,
First, the reference PN pattern generation means (102)
The reference PN pattern corresponding to the pattern mounted on the cell.
Loss of PN pattern synchronization detection for turn re-creation
Means (104) and a means for detecting the PN pattern loss of synchronization.
The synchronization of the two patterns detected by step (104) is
In the shift state, the reference PN
By monitoring whether a turn is available, the test
To determine that the cell has been lost or that other cells
That determination means (105), determine the discriminating means (105)
Count the number of cells judged to be loss of test cells due to interruption
Loss cell counter (107), said discrimination means (10
By the determination in 5), the number of cells determined to be mixed with other cells is counted.
Number of mixed cell counters (108) and both patterns
In the synchronized state of (1), the comparison means (103)
As a result, errors that occur in the test cell during transmission of inconsistent bits
Error bit counter (106) for counting as an error bit
And an ATM test method characterized by comprising:
The configuration is as follows.

Alternatively, the PN pattern is out of synchronization.
The detecting means (104) includes the test cell detecting means (10
The pattern mounted on the cell detected in 1) and the cell
Reference PN pattern synchronized with the pattern mounted on the
Monitors whether the ratio of the match with the pattern is below a certain value
The cell is a normal test cell, or
Test cell loss or other cell contamination
The structure as an ATM test method characterized in that it can be distinguished.
Have

Alternatively, the determining means (105)
The reference PN pattern and a pattern mounted on the cell
The reference PN in a state where synchronization with the
In the pattern generation means (102),
Again for reference synchronized with the pattern mounted on the cell
By monitoring whether a PN pattern can be obtained,
Loss of test cells in the cell or contamination of other cells
ATM test method characterized by being able to determine what occurred
It has a configuration as an expression.

Alternatively, the test PN pattern is divided into several parts, and test cells carrying each of them are transmitted in that order from the transmitting side to the transmission line (100) in the ATM mode, and the test cells are received. Or, in an ATM test method performed by monitoring, a test cell detecting means (101) for detecting the test cell from the transmission line (100), and a pattern and bit mounted on the cell detected by the test cell detecting means (101). Reference PN pattern generation means (102) for generating a reference PN pattern that matches in units;
The reference PN pattern generated by the reference PN pattern generation means (102) and the test cell detection means (10
The comparison means (103), which compares the pattern mounted on the cell detected by 1) bit by bit, and monitors the result of the comparison by the comparison means (103).
When the ratio of the N patterns that match the pattern mounted on the cell is equal to or less than a certain value, it is determined that the two patterns are out of synchronization, and the N pattern is again transmitted to the reference PN pattern generation means (102). A PN that recreates a reference PN pattern that matches the pattern mounted on the cell
Pattern synchronization loss detecting means (104); and a received test cell number counter (301) for counting the number of cells detected by the test cell detecting means (101).
The test cell uses a test cell to which a test PN pattern is divided into several patterns, a serial number assigned in the order of generation of the test cells, and an error detection and correction code of the serial number. A serial number error detecting and correcting means (30) for checking whether or not an error exists in a serial number of the cell by using an error detecting and correcting code mounted on the cell.
And 2), by comparing the value of the error it is not judged to be the sequence number and the received test cell counter (301) by said sequence number error detection and correction means (302), prior to
Of the received test cell number counter (301).
If the values match, it is determined that the test cells have been normally received in order, and the serial number is the number of received test cells.
If it is larger than the value of the counter (301), it is determined that a test cell loss has occurred, and the serial number is
If not smaller than the value of the test cell counter (301)
It is discrimination means (10 for determining the contamination of other cells occurs
5) and in a state where it is determined to be normal by the determination means (105) or in a synchronized state of the two patterns, as a result of the comparison by the comparison means (103), a bit that does not match is stored in the test cell being transmitted. An error bit counter (106) that counts as an error bit that has occurred, and the number of cells determined to be loss of test cells by the determination of the determination unit (105) is calculated from the value of the serial number to the number of received test cells.
A counter (301) loss cell counter that counts from subtracting the value of (107), the determination of the determining means (105), the number of cells is determined that incorporation of other cells, the receiving
The serial number is obtained from the value of the communication test cell number counter (301).
Mixed cell counter for counting from subtracting the value (1
08), and has a configuration as an ATM test system.

Alternatively, some test PN patterns are used.
And place the test cells on each one in that order.
To the transmission line (100) in the ATM mode from the transmission side
ATM test was performed the test cell receiving or monitor to
In the method, the test cell is detected from a transmission line (100).
A test cell detecting means (101) for outputting the test cell;
The pattern mounted on the cell detected by the output means (101).
PN pattern that matches the pattern and bit unit
Reference PN pattern generation means (102) for generating
Generated by the reference PN pattern generation means (102).
PN pattern for reference and the test cell detecting means (10
The pattern mounted on the cell detected in 1) is compared with the pattern.
Comparing means (103) for comparing each of the units, and the comparing means
The result of the comparison in (103) is monitored, and the reference P
The N pattern matches the pattern mounted on the cell.
When the ratio of the two patterns is below a certain value,
Judgment that the reference PN pattern was generated again
Pattern mounted on the cell for forming means (102)
To recreate a reference PN pattern that matches
A pattern out of synchronization detection means (104), said test cell
The number of cells detected by the cell detecting means (101) is counted.
A receiving test cell number counter (301) for counting
The test cell is divided into several test PN patterns.
Each pattern is assigned in the order of generation of test cells.
A serial number and an error detection and correction code of the serial number.
Using a test cell that has been
An error exists in the serial number of the cell using the detection correction code
Serial number error detection and correction means (30)
2) and the PN pattern out-of-synchronization detecting means (10)
Out-of-synchronization state of both patterns detected by 4)
In a certain period, the reference PN pattern is
By monitoring whether or not it can be obtained,
Judgment has occurred and the PN pattern loss of synchronization is detected.
Synchronization of the two patterns detected by the means (104)
In the state, the serial number error detection and correction means (30
2) the serial number determined to be error-free and the reception
To compare with the value of the test cell counter (301)
Whether the test cells were received normally in order.
Determining means (10) for determining whether a test cell loss has occurred.
5) and the determination by the determination means (105) is normal.
In the disconnected state or in the synchronized state of both patterns
And the comparison means (103) does not match
The error bit in the test cell during transmission.
The number for error bit counter (106), said determining means
According to the determination in (105), the cell determined to be a loss of the test cell.
Loss cell counter for counting the Le number (107), said-size
According to the judgment of the different means (105), it is judged that another cell is mixed.
And a mixed cell counter for counting the number of cells (108), the
ATM test system characterized by having
Having a configuration.

Alternatively, the test PN pattern is divided into several parts, and the test cells carrying each of them are transmitted in that order from the transmitting side to the transmission line (100) in the ATM mode, and the test cells are received. Or, in an ATM test method performed by monitoring, a test cell detecting means (101) for detecting the test cell from the transmission line (100), and a pattern and bit mounted on the cell detected by the test cell detecting means (101). Reference PN pattern generation means (102) for generating a reference PN pattern that matches in units;
The reference PN pattern generated by the reference PN pattern generation means (102) and the test cell detection means (10
The comparison means (103), which compares the pattern mounted on the cell detected by 1) bit by bit, and monitors the result of the comparison by the comparison means (103).
When the ratio of the N patterns that match the pattern mounted on the cell is equal to or less than a certain value, it is determined that the two patterns are out of synchronization, and the N pattern is again transmitted to the reference PN pattern generation means (102). A PN that recreates a reference PN pattern that matches the pattern mounted on the cell
Pattern synchronization loss detecting means (104); and a received test cell number counter (301) for counting the number of cells detected by the test cell detecting means (101).
The test cell uses a test cell to which a test PN pattern is divided into several patterns, a serial number assigned in the order of generation of the test cells, and an error detection and correction code of the serial number. A serial number error detecting and correcting means (30) for checking whether or not an error exists in a serial number of the cell by using an error detecting and correcting code mounted on the cell.
2) and the PN pattern out-of-synchronization detecting means (10)
In the synchronous state of the two patterns detected in 4), the serial number which is determined by the serial number error detecting and correcting means (302) to have no error is compared with the value of the reception test cell number counter (301). by the communication
Serial number and the value of the reception test cell number counter (301) are
If they match, it is determined that the test cells have been normally received in order, and the serial number is counted as the number of received test cells.
If it is larger than the value of the receiving test cell (301), it is determined that a test cell loss has occurred, and the serial number is
It is smaller than the value of Le counter (301) includes a discriminating means for determining that incorporation of another cell has occurred (105),
Said state is determined to be normal by the determining the determining means (105) or in the synchronous state of both patterns, the comparing means (103) the result of the comparison, the error bits occurring in the test cell during the transmission nonmatching bit An error bit counter (106) for counting as
The number of cells determined to be loss of test cells by the determination of 5) is calculated from the value of the serial number by the reception test cell number counter.
The lost cell counter (107) that counts by subtracting the value of (301) and the number of cells determined to be mixed with other cells by the determination of the determination unit (105) are determined by the reception test.
From the value of the test cell number counter (301), the value of the serial number
Counted by subtracting the mixed cell counter (10
8), and has a configuration as an ATM test system.

[0045]

In the ATM test method, the comparison result between the reference PN pattern generated by the reference PN pattern generation means (102) and the pattern mounted on the cell detected by the test cell detection means (101) is used as the PN pattern. By monitoring the out-of-synchronization detecting means (104) and monitoring whether or not the two patterns are out of synchronization, it is possible to specify that the pattern mounted on the cell is a continuous PN pattern.

[0046] That is, when mounting pattern in the cell is a continuous PN pattern, substantially coincides with the reference PN pattern.

Meanwhile, skip PN pattern due to the loss of the test cell or by the incorporation of another cell, when mounted on the pattern in the cell is not a continuous PN pattern, a number of mismatch bits between the both patterns generated And
The two patterns are immediately out of synchronization.

[0048] Referring again within a predetermined period in the reference PN pattern generating means in a state where synchronization is lost between the mounting pattern to the said reference PN pattern cell (102), the discrimination means (105) For P
By monitoring whether or not N patterns can be obtained, the cause of the loss of synchronization can be identified.

That is, when the reference PN pattern synchronized with the pattern mounted on the cell is obtained again, it can be specified that the cell is the test cell having the skipped PN pattern, and therefore, the test cell immediately before the test cell can be specified. Can be specified that the test cell has been lost.

On the other hand, if the reference PN pattern cannot be obtained, it can be specified that the cell is another cell having a completely random pattern, and thus it can be specified that another cell has been mixed.

At this time, the number of cells specified as lost cells or mixed cells is counted by the lost cell counter (10
7) Alternatively, by adding to the mixed cell counter (108) , the number of lost cells and the number of mixed cells generated during the test can be measured.

A serial number (SN) error detecting and correcting means (30)
According to 2) , it is possible to identify whether the received cell is a test cell or another cell by checking whether or not there is an error in the serial number of the received cell.

In other words, if the test cell is normally received, no error occurs in the serial number, but other cells do not have the serial number itself, so an error occurs in the serial number area.

At this time, by adding the number of cells specified as mixed cells of other cells to the mixed cell counter (108) , the number of mixed cells generated during the test can be measured.

The serial number mounted on the test cell determined to be normal by the serial number (SN) error detection and correction means (302) by the determination means (105) and the value of the received test cell number counter (301) . By comparing with the above, it can be specified whether the test cell is normal, has been lost, or has mixed with other cells.

That is, when the two values match, it can be detected that the test cells have been received normally in order. When the serial number is larger than the received test cell number counter value, the immediately preceding test cell is lost. Can be detected.

When the received cell counter value is larger than the serial number, it can be detected that another cell has been mixed immediately before.

The number of cells actually lost or mixed becomes apparent from the difference between the serial number and the received test cell number counter value, and is added to the lost cell counter (107) or mixed cell counter (108). The number of lost cells and the number of mixed cells generated during the test can be accurately measured.

As described above, the pattern mounted on the test cell determined to be a normal test cell and the reference PN pattern synchronized with the pattern are compared, and the mismatch bit detected as a result is compared with the error bit counter (106). ) , The number of error bits generated during the test can be measured.

[0060]

DESCRIPTION OF THE PREFERRED EMBODIMENTS For the sake of simplicity, a pseudo random pattern is abbreviated as a PN pattern, a serial number is abbreviated as SN, an error detection and correction code is abbreviated as SNP, and the number of received test cells is abbreviated as an SNR.

Further, when two patterns having different generating means coincide with each other for every bit during a certain period, it is called that both patterns are synchronized, and the subsequent two patterns are called synchronized.

On the other hand, if the two patterns do not agree with each other by a certain value or more, it is said that the two patterns are out of synchronization.

(Embodiment 1) FIG. 1 shows an ATM test system as a first embodiment of the present invention.
Shows a schematic block diagram of a test cell processing circuit in
You. In FIG. 1, 100 is a transmission line, 101 is a test cell.
A detection circuit; 102, a reference PN pattern generation circuit;
3 is a comparison circuit, 104 is a PN pattern out-of-sync detection time
Path, 105 is a determination circuit, 106 is an error bit counter,
107 is a lost cell counter, 108 is a mixed cell counter
Is shown.

In the ATM test system as the first embodiment ,
The test cell processing circuit can be included in a transmission device and a switch in the transmission network.

First, the ATM test method as the first embodiment
The configuration of the test cell processing circuit in the equation will be described.

The test cell detection circuit 101 is connected to the transmission line 100
Has a function of detecting a test cell transmitted with the PN pattern and extracting a reception PN pattern mounted in the test cell.

The reference PN pattern generation circuit 102 is connected to the test cell detection circuit 101 and has a function of newly generating a reference PN pattern synchronized with the reception PN pattern.

The comparison circuit 103 includes the test cell detection circuit 10
1 and is connected to the reference PN pattern generation circuit 102 and has a function of comparing the coincidence / mismatch between the reception PN pattern and the reference PN pattern for each bit.

PN pattern out-of-synchronization detection circuit 104
Receives the comparison result of the comparison circuit 103 and constantly monitors whether or not the two patterns are out of synchronization. If the two patterns are out of synchronization, the reference PN
Pattern generation circuit 102 and error bit counter 10
6 has a function of issuing a reset command.

The discrimination circuit 105 is connected to the reference PN pattern generation circuit 102, and the reference PN pattern generation circuit 1
In 02, it is monitored whether or not a reference PN pattern synchronized with the received PN pattern has been generated.

The discrimination circuit 105 determines whether the received test cell has been normally received or whether the test cell has been lost.
It is determined whether another cell is mixed.

The error bit counter 106 includes a comparator 1
03, and the PN pattern out-of-synchronization detection circuit 104
, The number of error bits generated in the reception PN pattern mounted on the test cell determined to be normal by the determination circuit 105 is counted.

The lost cell counter 107 is provided in the discriminating circuit 10
When it is determined that the test cell has been lost in step 5, the value is increased.

The mixed cell counter 108 is provided in the determination circuit 10
When it is determined in step 5 that another cell has been mixed, the value is increased.

[0075] Figure 2, A as a first embodiment of the present invention
The operation of the test cell processing circuit in the TM test method will be described.
FIG. 9 is a flowchart illustrating a measurement process flow of an error bit, a lost cell, and a mixed cell. In FIG.
201: test cell detection processing, 202: PN pattern synchronization
Establishment processing, 203: PN pattern out-of-synchronization determination processing,
204 is a PN pattern resynchronization establishment process, and 205 is a normal process.
206, loss processing, and 207, mixing processing.

The following is a first embodiment based on the above contents.
The operation of the test cell processing circuit in the ATM test method will be described with reference to FIG.

1) Test cell detection processing 201

The test cell detection circuit 101 detects a test cell and extracts a reception PN pattern mounted in the test cell.

2) PN pattern synchronization establishment processing 202

This processing is necessary when the test is started or when the received PN pattern and the reference PN pattern are out of synchronization in the immediately preceding test cell. The process proceeds to the PN pattern out-of-synchronization determination process 203.

This processing is performed in the reference PN pattern generation circuit 1
02 and the determination circuit 105.

If the synchronization is lost before the measurement process,
The reference PN pattern generation circuit 102 generates a reference PN pattern synchronized with the received PN pattern mounted on the received test cell.

The reference PN pattern generation circuit 102
It holds a preset synchronization condition (for example, if the two patterns match over 30 consecutive bits, it is regarded as synchronization), and changes the reference PN pattern until a reference PN pattern that satisfies the synchronization condition is obtained. Continue generating.

At this time, the discriminating circuit 105 determines a predetermined discriminating condition (for example, if a reference PN pattern that satisfies the synchronizing condition within one cell processing time after receiving a test cell is obtained, synchronization is established). It is determined whether a reference PN pattern synchronized with the reception PN pattern has been obtained based on the determination conditions.

If the reference PN pattern is obtained, it is determined that a test cell having a normal PN pattern has been received, and the subsequent PN pattern is used by using the reference PN pattern.
The process proceeds to the out-of-synchronization determination process 203.

On the other hand, if the reference PN pattern is not obtained, it is determined that the received cell is a mixed cell having a random pattern, and the flow proceeds to the mixing process 207.

3) PN pattern out-of-synchronization determination processing 203

When a reference PN pattern synchronized with the reception PN pattern has been obtained in advance, it is determined whether or not the synchronization of both patterns is continued.

PN pattern out-of-synchronization detection circuit 104
Holds out-of-sync conditions set in advance (for example, if there is a mismatch of 15 bits or more in all bits of the PN pattern mounted on one test cell, both patterns are regarded as out-of-sync). By referring to the comparison result of each bit of the two patterns by the circuit 103, it is always monitored whether or not the out-of-synchronization condition is satisfied.

If a comparison result that satisfies the out-of-synchronization condition is obtained, it is determined that the two patterns are out of synchronization, and the process shifts to the PN pattern resynchronization establishment process 204.

[0091] In addition, at the same time to reset the error bit counter 106, to cancel your Keru mismatch bit counter to the out-of-sync state.

On the other hand, if no out-of-synchronization is detected, it is determined that the received PN pattern is normal, and normal processing 2
Move to 05.

4) PN pattern resynchronization establishment processing 204

If the received PN pattern is determined to be out of synchronization with the reference PN pattern by the PN pattern out-of-synchronization determination processing 203, a new reference P
Recreate the N pattern.

When the PN pattern out-of-synchronization detection circuit 104 determines that the synchronization is out of synchronization, the reference PN pattern generation circuit 102 is reset.

The reference PN pattern generation circuit 102 generates a new reference PN pattern. At this time, the reference PN pattern is repeatedly generated until a reference PN pattern satisfying the synchronization condition is obtained. .

The discriminating circuit 105 for monitoring the result can set the discriminating condition set in advance (however, the discriminating condition can be set independently of the discriminating condition.
If a reference PN pattern that satisfies the synchronization condition is obtained within the same time, it is considered that synchronization has been established), and loss or mixing of cells is determined based on the determination condition.

That is, when the test cell is lost, the receiving unit of the test cell skips the reception PN pattern, which should be continuous, by skipping the middle.

Therefore, immediately after skipping, the reference PN
Although the reference PN is out of synchronization with the pattern, the reference PN is synchronized again with the skipped reception PN pattern within the determination conditions.
A pattern is obtained.

On the other hand, when another cell is mixed,
A completely random pattern is mixed in the N pattern.

Therefore, the synchronization with the reference PN pattern is lost immediately after the random pattern is mixed, and there is no reference PN pattern synchronized with the random pattern. The obtained reference PN pattern is not obtained.

The discrimination circuit 105 pays attention to this point, and when the reception pattern and the reference PN pattern are synchronized again within the discrimination condition, the cell is a test cell, and immediately before the test cell, the test cell Judge that there was a loss, loss processing 2
Shift to 06.

If the reception pattern and the reference PN pattern are not synchronized even after the determination condition, the cell is determined to be another cell, and the process proceeds to the mixing process 207.

5) Normal processing 205

For the test cell determined to be normal by the determination circuit 105, the PN pattern out-of-synchronization detection circuit 10
4, only when the out-of-synchronization condition is not satisfied, a bit that does not match as a result of the comparison between the received PN pattern by the comparator 103 and the reference PN pattern synchronized with the received PN pattern is regarded as an error bit generated in the received PN pattern. The count is performed by the counter 106.

If the PN pattern loss of synchronization detection circuit 1
If it is determined at 04 that the synchronization has been lost, the count value of the error bit counter 106 is reset.

6) Loss processing 206

When the determination circuit 105 determines that the test cell has been lost, the lost cell counter 107 is incremented by one.

Further, since the reception pattern and the reference PN pattern are synchronized, the bit which has become inconsistent as a result of comparison by the comparison circuit 103 is counted by the error bit counter 106 as an error bit generated in the reception PN pattern. .

At this time, it is needless to say that the synchronization state of the two patterns is monitored by the PN pattern out-of-synchronization detecting circuit 104.

7) Mixing process 207

When the determination circuit 105 determines that another cell has been mixed, the mixed cell counter 108 is incremented by one.

(Embodiment 2) FIG. 3 shows an ATM test system as a second embodiment of the present invention.
Shows a schematic block diagram of a test cell processing circuit in
You . In FIG. 3, 100 is a transmission line, 101 is a test cell.
A detection circuit; 102, a reference PN pattern generation circuit;
3 is a comparison circuit, 104 is a PN pattern out-of-sync detection time
Path, 105 is a determination circuit, 106 is an error bit counter,
107 is a lost cell counter, 108 is a mixed cell counter
301, a reception test cell number (SNR) counter, 30
Reference numeral 2 denotes a serial number (SN) error detection and correction circuit.

The ATM test method as the second embodiment is
The test cell processing circuit can be included in a transmission device and a switch in the transmission network.

First, the ATM test method as the second embodiment
The configuration of the test cell processing circuit in the equation will be described.

The test cell detection circuit 101 is connected to the transmission line 100
Has a function of detecting a test cell transmitted with the PN pattern and extracting a reception PN pattern, a serial number (hereinafter, SN) and an error detection and correction code (hereinafter, SNP) mounted in the test cell.

The received test cell number (SNR) counter 301 counts the number of received test cells.

The SN error detection and correction circuit 302 has a function of detecting and correcting an error occurring in the SN using the SNP.

The reference PN pattern generation circuit 102 is connected to the test cell detection circuit 101 and has a function of newly generating a reference PN pattern synchronized with the reception PN pattern.

The comparison circuit 103 includes the test cell detection circuit 10
1 and is connected to the reference PN pattern generation circuit 102 and has a function of comparing the coincidence / mismatch between the reception PN pattern and the reference PN pattern for each bit.

PN pattern out-of-synchronization detection circuit 104
Receives the comparison result of the comparison circuit 103 and constantly monitors whether or not the two patterns are out of synchronization. If the two patterns are out of synchronization, the reference PN
Pattern generation circuit 102 and error bit counter 10
6 has a function of issuing a reset command.

The discriminating circuit 105 includes an SNR counter 301
In addition, it is connected to the SN error detection and correction circuit 302 to monitor the difference between the SN value and the SNR value of the received cell.

The discriminating circuit 105 determines whether the received test cell has been received normally, whether the test cell has been lost, or not.
It is determined whether another cell is mixed.

The error bit counter 106 is provided by the comparator 1
03, and the PN pattern out-of-synchronization detection circuit 104
, The number of error bits generated in the reception PN pattern mounted on the test cell determined to be normal by the determination circuit 105 is counted.

The lost cell counter 107 is provided in the determination circuit 10
When it is determined that the test cell has been lost in step 5, the value is increased.

The mixed cell counter 108 is
When it is determined in step 5 that another cell has been mixed, the value is increased.

FIG. 4 shows an ATM test as a second embodiment.
For explaining the operation of the test cell processing circuit in the system
It is a chart figure and shows the measurement processing flow of an error bit, a lost cell, and a mixing cell. In FIG. 4, 205 is
Normal processing, 401: test cell detection and counting processing, 40
2 is a serial number (SN) error check process, 403 is an SN or SN
And SNR comparison processing, 404 is loss processing, and 405 is mixed
Input processing, 406 performs synchronization establishment and error bit measurement processing.
Show.

Hereinafter , the second embodiment of the present invention based on the above contents will be described.
The operation of the test cell processing circuit in the ATM test system as an embodiment of the present invention will be described with reference to FIG.

1) Test cell detection and counting processing 401

The test cell detection circuit 101 detects a test cell and extracts a reception PN pattern, SN and SNP mounted in the test cell.

When a test cell is received, the SNR counter is increased by one.

2) SN error check processing 402

The SN error detection and correction circuit 302 checks whether or not the received SN error exists using the SNP.

Since an error may occur in the SN itself during transmission, the presence or absence of an error in the SN is checked by the SNP, and if an error is detected, the SN is corrected to a correct SN.

An SN error is a case where an SN having an error that cannot be corrected by the SNP is detected.

Normally, the probability that there is a test cell in which an SN error occurs is quite low. An SN error occurs when another cell having a completely random value is mixed in the SN mounting area in the test cell. Can be determined.

The present process pays attention to this point, and determines whether or not the cell is a test cell based on the presence or absence of an SN error.

That is, a cell in which an SN error does not occur is a test cell, and the following SN and SNR comparison processing 403 is performed.
However, since the cell in which the SN error has occurred is another cell, test processing is not performed and the reception of the next test cell is waited for.

3) SN and SNR comparison processing 403

In the discriminating circuit 105, SN and SNR are compared.

Since the test cell has an SN value that is increased by one in the order in which the test cells are generated, the SN and the SN are usually used.
The values of R match.

At this time, if a loss of the test cell occurs, the SN value which should be continuous will be skipped and a number jump will occur (for example, when the SN should be 1-2-3-4-5 ). , SN = 3, the resulting S
N becomes 1-2-4-5 ).

As a result, the SN and the SNR do not match from the test cell received immediately after the lost test cell, and the SN value becomes larger than the SNR value by the number of the lost test cells.

On the other hand, when another cell is mixed,
A random number is mixed in the N number sequence (for example, S
When N should be 1-2-3-4-5 , SN = 3
In the case where another cell having ♯ mixed in the SN mounting area next to the test cell described above, the obtained SN is 1-2-3-♯-4-5 ).

As a result, a mismatch between SN and SNR occurs, and S
The N value is smaller than the SNR value by the number of mixed other cells.

The discriminating circuit 105 pays attention to this point, and
If the value matches the SN value, it is determined that the test cell has been normally received, and the process proceeds to normal processing 205.

When the SN value is larger than the SNR value, it is determined that the test cell has been lost, and the loss processing 4
Move to 04.

If the SN value is smaller than the SNR value, it is determined that another cell has been mixed, and the flow shifts to mixing processing 405.

4) Normal processing 205

For the test cell determined to be normal by the determination circuit 105, the PN pattern out-of-synchronization detection circuit 10
4, when the out-of-synchronization condition is not satisfied, a bit that is inconsistent as a result of comparison between the received PN pattern by the comparison circuit 103 and the reference PN pattern synchronized therewith is regarded as an error bit generated in the received PN pattern by an error bit counter. The counting is performed at 106.

If the PN pattern loss of synchronization detection circuit 1
If it is determined at 04 that the synchronization has been lost, the count value of the error bit counter 106 is reset.

5) Loss processing 404

When the determination circuit 105 determines that the test cell has been lost, the lost cell counter 107 is set to (S
N-SNR).

In order to make the SNR value equal to the SN value, the value of the SNR counter is decreased by (SN-SNR).

6) Mixing process 405

When the determination circuit 105 determines that another cell has been mixed, the mixed cell counter 108 is set to (SN).
R-SN).

In order to make the SNR value equal to the SN value, the value of the SNR counter is decreased by (SNR-SN).

7) Synchronization establishment and error bit measurement processing 40
6

Since the reception PN pattern mounted on the test cell in which the loss and the mixing are detected is not always synchronized with the reference PN pattern, the two patterns are resynchronized.

This processing is performed in the reference PN pattern generation circuit 1
02 and the determination circuit 105.

The reference PN pattern is continuously generated by the reference PN pattern generation circuit 102 until a reference PN pattern synchronized with the reception PN pattern is obtained.

This reference PN pattern generation circuit 102
Holds a preset synchronization condition (for example, when the two patterns match over 30 consecutive bits, it is regarded as synchronization), and the reference P satisfying the synchronization condition is held.
Generate N patterns.

At this time, the discriminating circuit 105 determines a predetermined criterion condition (for example, if a reference PN pattern that satisfies the synchronization condition within the processing time of one cell after receiving a test cell is obtained, synchronization is established). It is determined whether a reference PN pattern synchronized with the reception PN pattern has been obtained based on the determination conditions.

Since the received PN pattern mounted on the test cell is used, it can be expected that resynchronization of both patterns is established within the discrimination conditions in most cases.

When the reference PN pattern is obtained, it is assumed that both patterns are synchronized, and the error bits detected by the comparison circuit 103 thereafter are counted by the error bit counter 106.

If the reference PN pattern cannot be obtained, the received PN pattern is regarded as abnormal and excluded from the error bit measurement target.

(Embodiment 3) FIG. 5 shows an ATM test system according to a third embodiment of the present invention.
Shows a schematic block diagram of a test cell processing circuit in
You . In FIG. 5, 100 is a transmission line, 101 is a test cell.
A detection circuit; 102, a reference PN pattern generation circuit;
3 is a comparison circuit, 104 is a PN pattern out-of-sync detection time
Path, 105 is a determination circuit, 106 is an error bit counter,
107 is a lost cell counter, 108 is a mixed cell counter
301, a reception test cell number (SNR) counter, 30
Reference numeral 2 denotes a serial number (SN) error detection and correction circuit.

The ATM test method as the third embodiment is
The test cell processing circuit can be included in a transmission device and a switch in the transmission network.

First, the ATM test method as the third embodiment
The configuration of the test cell processing circuit in the equation will be described.

The test cell detection circuit 101 is connected to the transmission line 100
Has a function of detecting a test cell transmitted with the PN pattern and extracting a reception PN pattern, SN, and SNP mounted in the test cell.

The SNR counter 301 counts the number of test cells received.

The SN error detection and correction circuit 302 has a function of detecting and correcting an error occurring in the SN using the SNP.

The reference PN pattern generation circuit 102 is connected to the test cell detection circuit 101 and has a function of newly generating a reference PN pattern synchronized with the reception PN pattern.

The comparison circuit 103 includes the test cell detection circuit 10
1 and is connected to the reference PN pattern generation circuit 102 and has a function of comparing the coincidence / mismatch between the reception PN pattern and the reference PN pattern for each bit.

PN pattern out-of-synchronization detection circuit 104
Receives the comparison result of the comparison circuit 103 and constantly monitors whether or not the two patterns are out of synchronization. If the two patterns are out of synchronization, the reference PN
Pattern generation circuit 102 and error bit counter 10
6 has a function of issuing a reset command.

The discriminating circuit 105 is connected to the reference PN pattern generation circuit 102, the SNR counter 301, and the SN error detection and correction circuit 302, and the reference PN pattern generation circuit 102 synchronizes the reference PN pattern with the reception PN pattern.
It monitors whether an N pattern has been generated and monitors the difference between the SN value and the SNR value of the receiving cell.

The discrimination circuit 105 determines whether the received test cell has been normally received or whether the test cell has been lost.
It is determined whether another cell is mixed.

The error bit counter 106 is provided by the comparator 1
03, and the PN pattern out-of-synchronization detection circuit 104
, The number of error bits generated in the reception PN pattern mounted on the test cell determined to be normal by the determination circuit 105 is counted.

The lost cell counter 107 is provided in the discriminating circuit 10
When it is determined that the test cell has been lost in step 5, the value is increased.

The mixed cell counter 108 is
When it is determined in step 5 that another cell has been mixed, the value is increased.

[0181] Figure 6, A as a third embodiment of the present invention
Explaining the operation of the test cell processing circuits in TM test method
FIG. 9 is a flowchart illustrating a measurement process flow of an error bit, a lost cell, and a mixed cell. In FIG.
202 is a PN pattern synchronization establishment process, 203 is a PN pattern
Loss synchronization judgment processing, PN pattern resynchronization 204
Establish processing, 205 is normal processing, 401 is test cell detection and
And a counting process 402 is a serial number (SN) error checking process.
403, SN and SNR comparison processing, 601 loss
Lost processing, 602 indicates mixing processing.

Hereinafter , the third aspect of the present invention based on the above contents will be described.
The operation of the test cell processing circuit in the ATM test system as an embodiment of the present invention will be described with reference to FIG.

1) Test cell detection and counting processing 401

The test cell detection circuit 101 detects a test cell and extracts a reception PN pattern, SN and SNP mounted in the test cell.

When a test cell is received, the SNR counter is increased by one.

2) PN pattern synchronization establishment processing 202

This processing is necessary when starting the test or when the received PN pattern is out of synchronization with the reference PN pattern in the test cell immediately before. The process proceeds to the PN pattern out-of-synchronization determination process 203.

This processing is performed in the reference PN pattern generation circuit 1
02 and the determination circuit 105. If the synchronization is lost before the measurement processing, a reference PN pattern synchronized with the received PN pattern mounted on the received test cell is generated.

The reference PN pattern generation circuit 102 continues to generate a reference PN pattern until a reference PN pattern synchronized with the reception PN pattern is obtained.

This reference PN pattern generation circuit 102
Holds a preset synchronization condition (for example, when the two patterns match over 30 consecutive bits, it is regarded as synchronization), and the reference P satisfying the synchronization condition is held.
Generate N patterns.

At this time, the discriminating circuit 105 performs the synchronizing operation when a reference PN pattern that satisfies the synchronizing condition is obtained within one cell processing time after receiving the test cell. Is determined to have been established), and it is determined whether or not a reference PN pattern synchronized with the received PN pattern has been obtained based on the determination conditions.

If the reference PN pattern is obtained, it is determined that the test cell has been received normally and the subsequent processing 20
Move to 3.

On the other hand, if the reference PN pattern cannot be obtained, it is determined that the received cell is a mixed cell having a random pattern, and the flow proceeds to the mixing process 602.

3) PN pattern out-of-synchronization determination processing 203

When a reference PN pattern synchronized with the reception PN pattern has been obtained in advance, it is determined whether or not the synchronization of the two patterns is continued.

PN pattern out-of-synchronization detection circuit 104
Holds out-of-sync conditions set in advance (for example, if there is a mismatch of 15 bits or more in all bits of the PN pattern mounted on one test cell, both patterns are regarded as out-of-sync). By referring to the comparison result of each bit of the two patterns by the circuit 103, it is always monitored whether or not the out-of-synchronization condition is satisfied.

If a comparison result that satisfies the out-of-synchronization condition is obtained, it is determined that the two patterns are out of synchronization, and the process shifts to the PN pattern resynchronization establishment processing 204.

At the same time, the error bit counter 106 is reset to cancel the counting of mismatch bits in the out-of-synchronization state.

On the other hand, if no out-of-synchronization is detected, it is determined that the received PN pattern is normal, and the subsequent SN
The process proceeds to the error checking process 402.

4) PN pattern resynchronization establishment processing 204

When the received PN pattern is determined to be out of synchronization with the reference PN pattern by the PN pattern out-of-synchronization determination processing 203, a new reference P
Recreate the N pattern.

When the PN pattern out-of-synchronization detection circuit 104 determines that the synchronization is out of synchronization, the reference PN pattern generation circuit 102 is reset.

The reference PN pattern generation circuit 102 generates a new reference PN pattern. At this time, the reference PN pattern is repeatedly generated until a reference PN pattern satisfying the synchronization condition is obtained. .

The discrimination circuit 105 for monitoring the result can set the discrimination condition set in advance (however, it can be set independently of the discrimination condition).

For example, if a reference PN pattern that satisfies the synchronization condition is obtained within two times after receiving the test cell, it is considered that synchronization has been established.) Loss or contamination is determined.

That is, when the test cell is lost, the receiving section of the test cell skips the reception PN pattern, which should be continuous, by skipping the middle.

For this reason, immediately after skipping, the reference PN
Although the reference PN is out of synchronization with the pattern, the reference PN is synchronized again with the skipped reception PN pattern within the determination conditions.
A pattern is obtained.

On the other hand, when another cell is mixed,
A completely random pattern is mixed in the N pattern.

[0209] Therefore, the reference PN pattern is out of synchronization immediately after the random pattern is mixed, and there is no reference PN pattern synchronized with the random pattern. The obtained reference PN pattern is not obtained.

The discrimination circuit 105 pays attention to this point, and if the reception pattern and the reference PN pattern are synchronized again within the above-described discrimination condition, it is determined that the test cell has been lost.
The process proceeds to the subsequent SN error checking process 402.

If the reception pattern and the reference PN pattern are not synchronized even after the determination condition, it is determined that another cell has been mixed, and the process proceeds to the mixing process 602.

3) SN error check processing 402

The SN error detection and correction circuit 302 checks whether or not the received SN has an error by using the SNP.

Since an error may occur in the SN itself during transmission, the presence or absence of an error in the SN is checked by the SNP, and if an error is detected, the SN is corrected to a correct SN.

When no SN error is detected, the S
N is determined to be normal, and the process proceeds to the subsequent processing 403.

Although the probability of an error occurring in the SN while being synchronized is considerably low, if an SN error occurs,
Since accurate determination cannot be made, the test cell is not subjected to the test processing and waits for reception of the next test cell.

4) SN and SNR comparison processing 403

In the decision circuit 105, SN and SNR are compared.

The discriminating circuit 105 discriminates whether the received cell is a normal test cell, a test cell immediately after loss, or another cell mixed from another.
Among them, the mixing of other cells has already been determined in the PN pattern re-synchronization establishment processing 204, so in this processing, the presence or absence of the loss of the test cell is determined for the test cell on which the synchronized reception PN pattern is mounted. .

[0220] Since the test cell has an SN value that is increased by one in the order in which the test cells are generated, if the test cell is received normally, the SN and SNR values match.

At this time, if a loss of the test cell occurs, the SN value which should be continuous is skipped and a number jump occurs (for example, when the SN should be 1-2-3-4-5 ). , SN = 3, the resulting S
N becomes 1-2-4-5 ).

For this reason, the SN and the SNR do not match from the test cell received immediately after the lost test cell, and the SN value becomes larger than the SNR value by the number of the lost test cells.

The discrimination circuit 105 pays attention to this point, and
If the value matches the SN value, it is determined that the test cell has been normally received, and the process proceeds to normal processing 205.

If the SNR value and the SN value do not match,
It is determined that the test cell has been lost, and the process proceeds to the loss processing 601.

4) Normal processing 205

For the test cell judged to be normal by the judgment circuit 105, the PN pattern out-of-synchronization detection circuit 10
4, when the out-of-synchronization condition is not satisfied, a bit that is inconsistent as a result of comparison between the received PN pattern by the comparison circuit 103 and the reference PN pattern synchronized therewith is regarded as an error bit generated in the received PN pattern by an error bit counter. The counting is performed at 106.

If the PN pattern loss of synchronization detection circuit 1
If it is determined at 04 that the synchronization has been lost, the count value of the error bit counter 106 is reset.

5) Loss processing 601

When the determination circuit 105 determines that the test cell has been lost, the lost cell counter 107 is set to (S
N-SNR).

In order to make the SNR value equal to the SN value, the value of the SNR counter is decreased by (SN-SNR).

Since the reception PN pattern and the reference PN pattern are synchronized, the error bits detected by the comparison circuit 103 are counted by the error bit counter 106.

At this time, it is needless to say that the synchronization state of the two patterns is monitored by the PN pattern out-of-synchronization detecting circuit 104.

6) Mixing process 602

When the discrimination circuit 105 determines that another cell has been mixed, the mixed cell counter 108 is incremented by one.

Further, the value of the SNR counter is decreased by one in order to make the SNR value equal to the SN value.

(Embodiment 4) FIG. 7 shows an ATM test system according to a fourth embodiment of the present invention.
Shows a schematic block diagram of a test cell processing circuit in
You . In FIG. 7, 100 is a transmission line, 101 is a test cell.
A detection circuit; 102, a reference PN pattern generation circuit;
3 is a comparison circuit, 104 is a PN pattern out-of-sync detection time
Path, 105 is a determination circuit, 106 is an error bit counter,
107 is a lost cell counter, 108 is a mixed cell counter
301, a reception test cell number (SNR) counter, 30
Reference numeral 2 denotes a serial number (SN) error detection and correction circuit.

In the ATM test system as the fourth embodiment ,
The test cell processing circuit can be included in a transmission device and a switch in the transmission network.

First, the ATM test method as the fourth embodiment
The configuration of the test cell processing circuit in the equation will be described.

The test cell detection circuit 101 is connected to the transmission line 100
Has a function of detecting a test cell transmitted with the PN pattern and extracting a reception PN pattern, SN, and SNP mounted in the test cell.

The SNR counter 301 counts the number of test cells received.

[0241] The SN error detection and correction circuit 302 has a function of detecting and correcting an error occurring in the SN using the SNP.

The reference PN pattern generation circuit 102 is connected to the test cell detection circuit 101 and has a function of newly generating a reference PN pattern synchronized with the reception PN pattern.

The comparison circuit 103 includes the test cell detection circuit 10
1 and is connected to the reference PN pattern generation circuit 102 and has a function of comparing the coincidence / mismatch between the reception PN pattern and the reference PN pattern for each bit.

PN pattern out-of-synchronization detection circuit 104
Receives the comparison result of the comparison circuit 103 and constantly monitors whether or not the two patterns are out of synchronization. If the two patterns are out of synchronization, the reference PN
Pattern generation circuit 102 and error bit counter 10
6 has a function of issuing a reset command.

The discriminating circuit 105 is connected to the reference PN pattern generation circuit 102, the SNR counter 301, and the SN error detection and correction circuit 302, and the reference PN pattern generation circuit 102 synchronizes the reference PN pattern with the reception PN pattern.
It monitors whether an N pattern has been generated and monitors the difference between the SN value and the SNR value of the receiving cell.

The discriminating circuit 105 determines whether the received test cell has been normally received or whether the test cell has been lost.
It is determined whether another cell is mixed.

The error bit counter 106 is provided by the comparison circuit 1
03, and the PN pattern out-of-synchronization detection circuit 104
, The number of error bits generated in the reception PN pattern mounted on the test cell determined to be normal by the determination circuit 105 is counted.

The lost cell counter 107 is provided in the discriminating circuit 10
When it is determined that the test cell has been lost in step 5, the value is increased.

The mixed cell counter 108 has a function of
When it is determined in step 5 that another cell has been mixed, the value is increased.

[0250] Figure 8, A as a fourth embodiment of the present invention
The operation of the test cell processing circuit in the TM test method will be described.
FIG. 9 is a flowchart illustrating a measurement process flow of an error bit, a lost cell, and a mixed cell. In FIG.
202 is a PN pattern synchronization establishment process, 203 is a PN pattern
Out-of-synchronization determination processing, 205 is normal processing, 401 is
Test cell detection and counting processing, 402 is a serial number (S
N) Error check processing, 403 compares SN and SNR
Processing, 601 indicates loss processing, and 801 indicates mixing processing.

The following is a description of the fourth embodiment of the present invention based on the above contents .
The operation of the test cell processing circuit in the ATM test system as an embodiment of the present invention will be described with reference to FIG.

1) Test cell detection and counting processing 401

The test cell detection circuit 101 detects a test cell and extracts a reception PN pattern, SN and SNP mounted in the test cell.

When a test cell is received, the SNR counter is increased by one.

2) PN pattern synchronization establishment processing 202

This processing is necessary at the start of the test or when the reception PN pattern and the reference PN pattern are out of synchronization in the test cell immediately before. If the synchronization has been established before, the following PN pattern is used. The process proceeds to the out-of-synchronization determination process 203.

This processing is performed in the reference PN pattern generation circuit 1
02 and the determination circuit 105.

If the synchronization is lost before the measurement processing,
A reference PN pattern synchronized with the received PN pattern mounted on the received test cell is generated.

The reference PN pattern generation circuit 102 continues to generate a reference PN pattern until a reference PN pattern synchronized with the reception PN pattern is obtained.

This reference PN pattern generation circuit 102
Holds a preset synchronization condition (for example, when the two patterns match over 30 consecutive bits, it is regarded as synchronization), and the reference P satisfying the synchronization condition is held.
Generate N patterns.

At this time, the discriminating circuit 105 performs the synchronizing operation when a reference PN pattern that satisfies the synchronizing condition is obtained within the processing time of one cell after receiving the test cell. Is determined to have been established), and it is determined whether or not a reference PN pattern synchronized with the received PN pattern has been obtained based on the determination conditions.

If the reference PN pattern is obtained, it is determined that the test cell has been normally received, and the processing shifts to the subsequent PN pattern out-of-synchronization determination processing 203.

On the other hand, if the reference PN pattern cannot be obtained, it is determined that the receiving cell is a mixed cell having a random pattern, and the test processing is not performed and the reception of the next test cell is waited.

3) PN pattern out-of-synchronization determination processing 203

When the reference PN pattern synchronized with the reception PN pattern has been obtained in advance, it is determined whether or not the synchronization of the two patterns is continued.

PN pattern out-of-synchronization detection circuit 104
Holds out-of-sync conditions set in advance (for example, if there is a mismatch of 15 bits or more in all bits of the PN pattern mounted on one test cell, both patterns are regarded as out-of-sync). By referring to the comparison result of each bit of the two patterns by the circuit 103, it is always monitored whether or not the out-of-synchronization condition is satisfied.

If a comparison result that satisfies the out-of-synchronization condition is obtained, it is determined that the two patterns are out of synchronization, and the test process is not performed on the test cell, and the reception of the next test cell is awaited.

At the same time, the error bit counter 106 is reset, and the counting of mismatch bits in the out-of-synchronization state is cancelled.

On the other hand, if no out-of-synchronization is detected, it is determined that the received PN pattern is normal, and the subsequent SN
The process proceeds to the error checking process 402.

4) SN error check processing 402

The SN error detection / correction circuit 302 checks whether or not the received SN has an error by using the SNP.

Since an error may occur in the SN itself during transmission, the presence or absence of an error in the SN is checked by the SNP, and if an error is detected, the SN is corrected to a correct SN.

If the SN error is not detected, the S
N is normal, and the process proceeds to the subsequent SN and SNR comparison processing 403.

Although the probability of an error occurring in the SN while being synchronized is considerably low, if an SN error occurs,
The test processing is not performed on the test cell, and the reception of the next test cell is waited.

3) SN and SNR comparison processing 403

The discriminating circuit 105 compares SN with SNR.

Since the test cell has an SN that is increased by one in the order in which the test cells are generated, the SN and the SNR are usually
Are the same.

At this time, if a loss of the test cell occurs, the SN value, which should be continuous, is skipped and a number jump occurs (for example, when the SN should be 1-2-3-4-5 ). , SN = 3, the resulting S
N becomes 1-2-4-5 ).

For this reason, SN and SNR mismatches occur from the test cell received immediately after the lost test cell, and the SN value becomes larger than the SNR value by the number of lost test cells.

On the other hand, when another cell is mixed,
A random number is mixed in the N number sequence (for example, S
When N should be 1-2-3-4-5 , SN = 3
If another cell having ♯ in the SN mounting area is mixed next to the test cell of ( 1 ), the obtained SN is 1-2-3-♯-4-5 ).

As a result, a mismatch between SN and SNR occurs, and S
The N value is smaller than the SNR value by the number of mixed other cells.

The discrimination circuit 105 pays attention to this point, and
If the value matches the SN value, it is determined that a normal test cell has been received, and the process proceeds to normal processing 205.

When the SN value becomes larger than the SNR value, it is determined that the test cell has been lost, and the loss processing 6
Move to 01.

When the SN value is smaller than the SNR value, it is determined that another cell has been mixed, and the flow shifts to mixing processing 801.

4) Normal processing 205

With respect to the test cell determined to be normal by the determination circuit 105, the PN pattern out-of-synchronization detection circuit 10
4, when the out-of-synchronization condition is not satisfied, a bit that is inconsistent as a result of the comparison between the received PN pattern by the comparison circuit 103 and the reference PN pattern synchronized with it is generated in the received PN pattern, and an error bit counter is generated as an error bit. The counting is performed at 106.

If the PN pattern loss of synchronization detection circuit 1
If it is determined at 04 that the synchronization has been lost, the count value of the error bit counter 106 is reset.

5) Loss processing 601

When the determination circuit 105 determines that the test cell has been lost, the lost cell counter 107 is set to (S
N-SNR).

In order to make the SNR value equal to the SN value, the value of the SNR counter is decreased by (SN-SNR).

Since the received PN pattern and the reference PN pattern of the test cell itself in which the loss is detected are synchronized, error bits detected by the comparison circuit 103 are counted by the error bit counter 106.

At this time, it is needless to say that the synchronization state of the two patterns is monitored by the PN pattern out-of-synchronization detecting circuit 104.

6) Mixing process 801

When the determination circuit 105 determines that another cell has been mixed, the mixed cell counter 108 is set to (SN).
R-SN).

Also, the value of the SNR counter is decreased by (SNR-SN) in order to make the SNR value equal to the SN value.

Since the received PN pattern of the test cell itself and the reference PN pattern for which the contamination has been detected are synchronized, error bits detected by the comparison circuit 103 are counted by the error bit counter 106.

At this time, it is needless to say that the PN pattern out-of-synchronization detection circuit 104 monitors the state of synchronization between the two patterns.

FIG. 9 shows an ATM test method according to the first embodiment of the present invention.
Shows a schematic block diagram of a test cell generator in
You . In FIG. 9, 100 is a transmission line, and 901 is a PN pattern.
Over down production formation circuit, the test cell assembling circuit 902, 903 trial
3 shows a test cell insertion circuit.

The test cell generation circuit in the ATM test system according to the first embodiment can be provided in a transmission device and an exchange in a transmission network.

First, the configuration of the test cell generation circuit in the ATM test system according to the first embodiment will be described.

[0301] The PN pattern generation circuit 901 has a function of generating a continuous PN pattern.

The test cell assembling circuit 902 divides the PN pattern generated by the PN pattern generating circuit 901 into predetermined blocks, and generates test cells each of which is mounted.

[0303] The test cell insertion circuit 903 inserts the generated test cell into the transmission path.

FIG. 10 shows the AT according to the first embodiment of the present invention .
Shows a block diagram of a test cell generated in M test method
You . In FIG. 10, reference numeral 1001 denotes a header, and 1002 denotes a page.
Elode, 1003 is OAM type, 1004 is PN pattern
This shows the application block.

In the ATM test method according to the first embodiment of the present invention,
It will be described with reference to FIGS. 9 and 10 the operation of the test cell generating circuit that.

A continuous PN pattern generated by the PN pattern generation circuit 901 is used for mounting on a cell.
Each PN pattern block 1004 is divided.

The test cell assembling circuit 902 has a PN pattern block 1004 and an OAM type 1003 indicating that it is a test OAM cell in the payload 1002.
A test cell including the header 1001 to be tested is assembled.

The test cell generated by the test cell assembly circuit 902 is inserted into the transmission line by the test cell insertion circuit 903.

FIG. 11 shows the ATs of Examples 2, 3, and 4 of the present invention.
FIG. 3 is a schematic block diagram of a test cell generation circuit in an M test system . 11, 100 is a transmission line, 90
1 is a PN pattern generation circuit, 902 is a test cell assembly time
Path, 903 is a test cell insertion circuit, 1101 is a serial number
(SN) generation circuit 1102 is an error detection and correction code (SN)
P) shows a generation circuit.

In the ATM test method of Examples 2, 3, and 4
The test cell generation circuit can be included in a transmission device and a switch in the transmission network.

First, the configuration of the test cell generation circuit in the ATM test system of the second, third, and fourth embodiments will be described.

[0312] The PN pattern generation circuit 901 has a function of generating a continuous PN pattern.

The serial number (SN) generation circuit 1101 generates numbers consecutive in the order in which test cells are generated.

An error detection and correction code generation circuit 1102 generates an error detection and correction code for the serial number generated by the serial number (SN) generation circuit 1101.

The test cell assembling circuit 902 includes the PN pattern generating circuit 901 and the serial number (SN) generating circuit 1
101, and a PN connected to the error detection and correction code (SNP) generation circuit 1102 and divided into certain blocks.
Pattern, serial number (SN) and error detection and correction code
A test cell on which the (SNP) is mounted is generated.

[0316] The test cell insertion circuit 903 inserts the generated test cell into the transmission path.

FIG. 12 shows Embodiments 2 and 3 of the present invention .
Shows a block diagram of a test cell produced in the fourth ATM testing system. In FIG. 12, reference numeral 1001 denotes a header;
2 is payload, 1003 is OAM type, 1201 is P
N pattern blocks, 1202 are serial numbers (SN), 1
203 denotes an error detection and correction code (SNP).

In the ATM test method of Examples 2, 3, and 4
It will be described with reference to FIGS. 11 and 12 the operation of the test cell generating circuit that.

[0319] The continuous PN pattern generated by the PN pattern generation circuit 901 is used for mounting on a cell.
Each PN pattern block 1201 is divided.

In the test cell assembly circuit 902, the PN pattern block 1201, the serial number (SN) generation circuit 1
The serial number (SN) 1202 generated by 101, the error detection and correction code (SNP) 1203 generated by the error detection and correction code (SNP) generation circuit 1102, and the OAM type 100 indicating that it is a test OAM cell
3 in the payload 1002 and the header 10 to be tested.
Assemble the test cell with 01.

The test cell generated by the test cell assembly circuit 902 is inserted into the transmission line by the test cell insertion circuit 903.

[0322]

According to the ATM test system of the present invention, an ATM test system having an efficient test processing algorithm for measuring the number of error bits, the number of lost cells, and the number of mixed cells to be measured in a test is provided. The present invention can provide a test circuit for realizing the same, and can accurately and efficiently realize a continuity test, a characteristic test, and a fault isolation test for virtual paths and virtual channels.

[Brief description of the drawings]

FIG. 1 is an ATM test method according to a first embodiment of the present invention.
Block diagram of the test cell processing circuit in the system

FIG. 2 is an ATM test method according to a first embodiment of the present invention;
To explain the operation of the test cell processing circuit in the system
Chart

FIG. 3 shows an ATM test system according to a second embodiment of the present invention.
Block diagram of the test cell processing circuit in the system

FIG. 4 shows an ATM test system according to a second embodiment of the present invention .
To explain the operation of the test cell processing circuit in the system
Chart

FIG. 5 shows an ATM test system according to a third embodiment of the present invention .
Block diagram of the test cell processing circuit in the system

FIG. 6 shows an ATM test system according to a third embodiment of the present invention.
Furocha explaining the operation of the test cell processing circuit in
Chart

FIG. 7 shows an ATM test system according to a fourth embodiment of the present invention.
Block diagram of the test cell processing circuit in the system

FIG. 8 shows an ATM test system according to a fourth embodiment of the present invention .
To explain the operation of the test cell processing circuit in the system
Chart

FIG. 9 is a schematic block configuration diagram of a test cell generation circuit in the ATM test system according to the first embodiment of the present invention .

FIG. 10 illustrates an ATM test method according to the first embodiment of the present invention .
Configuration diagram of generated test cell

FIG. 11 is an ATM test method according to Examples 2, 3, and 4 of the present invention.
Block diagram of the test cell generation circuit in the ITER

FIG. 12 is an ATM test method according to the second, third, and fourth embodiments of the present invention .
Diagram of test cell generated in

[Figure 13] schematic theory <br/> Akirazu of ATM test scheme according to the prior art

[Description of Signs] 10: Test cell insertion point 11: Test cell detection / measurement point 12: Inter-device test 13: Test between multiple devices 100 : Transmission line 101 : Test cell detection circuit 102 : Reference PN pattern generation circuit 103 : Comparison circuit 104 : PN pattern loss detection circuit 105 : Determination circuit 106 : Error bit counter 107 : Lost cell counter 108 : Mixed cell counter 201 : Test cell detection processing 202 : PN pattern synchronization establishment processing 203 : PN pattern loss synchronization determination processing 204 : PN pattern resynchronization establishment processing 205 : normal processing 206 , 404, 601: loss processing 207 , 405, 602, 801: mixing processing 301 : reception test cell number (SNR) counter 302 : serial number (SN) error detection and correction circuit 401 ... test cell detection and counting processing 402 ... sequence number (SN) error checking process 403 ... SN and comparison of SNR 406 ... synchronization establishment and error bit measurement processing 901 ... PN pattern generation circuit 902 ... test cell assembling circuit 903 ... test cell insertion circuit 1001 ... header 1002 ... payload 1003 ... OAM type 1004, 1201 ... PN pattern blocks 1101 ... sequence number (SN) generating circuit 1102 ... ECC code (SNP) generating circuit 1202 ... sequence number (SN) 1203 ... ECC code (SNP)

Continuation of front page (72) Inventor Hiromi Ueda 1-6-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-3-250834 (JP, A) JP-A-2-295323 (JP, A) JP-A-63-50227 (JP, A) JP-A-5-244196 (JP, A) 1992 IEICE Spring Conference B-726 1992 IEICE Autumn Conference B-543 IEICE technical report CS91-92 IEICE technical report CS92-30 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12/26 H04L 12/56

Claims (6)

(57) [Claims] 1. A test PN pattern is divided into several parts,
In an ATM test system in which the test cells carrying each of them are sequentially transmitted from the transmitting side to the transmission line in the ATM mode in order and the test cells are received or monitored, the test cells are detected from the transmission line. Test cell detection means, reference PN pattern generation means for generating a reference PN pattern that matches in bit units a pattern mounted on a cell detected by the test cell detection means, and reference PN pattern generation means A comparison unit that compares, on a bit-by-bit basis, a reference PN pattern generated by the method and a pattern mounted on the cell detected by the test cell detection unit; and monitoring a result of the comparison by the comparison unit. for
PN pattern, when the rate that matches the mounting pattern in the cell is less than a predetermined value, it is determined that synchronization the both patterns is out, mounted on the cell relative anew the reference PN pattern generating means a PN pattern <br/> synchronization deviation detecting unit that makes rework of the reference PN pattern matching the pattern, the in-sync state of both patterns detected by the PN pattern out detecting means, among the predetermined period again by reference PN pattern monitors whether obtained, the loss of the test cell, or a determination means for determining that the contamination of other cells occurs, at the discretion of the discriminating means, the loss of the test cell mixed for counting the loss cell counter for counting the number of cells was determined by determination of the determination means, the number of cells is determined that incorporation of other cells and And an error bit counter that counts bits that do not match as a result of the comparison by the comparing means as error bits generated in the test cell being transmitted in a synchronized state of the two patterns. ATM test system. 2. The PN pattern out-of-synchronization detecting means detects a ratio at which a pattern mounted on a cell detected by the test cell detecting means coincides with the reference PN pattern synchronized with the pattern mounted on the cell. 2. The method according to claim 1, wherein by monitoring whether or not the value is equal to or less than a predetermined value, it is possible to determine whether the cell is a normal test cell, a loss of the test cell, or mixing of another cell. ATM test system. Wherein said discriminating means, in the reference PN pattern generating means in a state where synchronization is lost between the mounting pattern to the said reference PN pattern cell, the cell again within a certain period 2. The method according to claim 1, wherein monitoring whether or not a reference PN pattern synchronized with the mounted pattern is obtained can determine whether a test cell has been lost or another cell has been mixed in the cell. ATM test system as described. 4. The test PN pattern is divided into several parts.
In an ATM test system in which the test cells carrying each of them are sequentially transmitted from the transmitting side to the transmission line in the ATM mode in order and the test cells are received or monitored, the test cells are detected from the transmission line. Test cell detection means, reference PN pattern generation means for generating a reference PN pattern that matches in bit units a pattern mounted on a cell detected by the test cell detection means, and reference PN pattern generation means A comparison unit that compares, on a bit-by-bit basis, a reference PN pattern generated by the method and a pattern mounted on the cell detected by the test cell detection unit; and monitoring a result of the comparison by the comparison unit. The PN pattern for use is determined that the two patterns are out of synchronization when the ratio of coincidence with the pattern mounted on the cell is below a certain value. PN pattern out-of-synchronization detecting means for causing the reference PN pattern generating means to re-create a reference PN pattern that matches the pattern mounted on the cell, and determining the number of cells detected by the test cell detecting means. A counter for counting the number of received test cells, wherein each test cell is divided into several test PN patterns, a serial number assigned in the order of generation of test cells, and error detection and correction of the serial number. Using a test cell to which a code is added, using an error detection and correction code mounted on the test cell, a serial number error detection and correction means for checking whether or not an error exists in the serial number of the cell; wherein by comparing the value of has been continuous number and the received test cell counter determines that there are no errors by the continuous number the error detection and correction means, before Sequence number and the received test cell
If the values of the number counters match, it is determined that the test cells have been normally received in order, and the serial number is
If it is larger than the value of the test cell number counter, it is determined that test cell loss has occurred, and the serial number is
Is smaller than the value of the test cell counter includes a determination means for determining the contamination of other cells occurs, the state is determined to be normal by the decision of the determining means or,
In the synchronized state of the two patterns, as a result of the comparison by the comparing means, an error bit counter that counts inconsistent bits as error bits generated in the test cell during transmission; From the value of the serial number,
A lost cell counter that counts by subtracting the value of the counter from the received test cell number counter,
An ATM test system comprising: a mixed cell counter that counts by subtracting a value of a number . 5. A test PN pattern is divided into several parts,
The test cells on which each of them is placed should be
To the transmission line in ATM mode and receive the test cell
Or a test cell detecting means for detecting said test cell from a transmission line in an ATM test system which performs monitoring.
And mounted on the cell detected by the test cell detecting means.
Reference PN pattern that matches the pattern in bit units
PN pattern generating means for generating a pattern
Reference PN pattern generated by the reference PN pattern generation means.
Turn and the cell detected by the test cell detection means.
Comparison means for comparing the mounted pattern with each bit
When, and monitors the results of comparison of the comparison means, for the reference
The PN pattern matches the pattern mounted on the cell
When the ratio of the two patterns is below a certain value,
And the reference PN pattern is referred to again.
Match the pattern mounted on the cell to the generating means
PN pattern that recreates the reference PN pattern
The number of cells detected by the out-of-synchronization detecting means and the test cell detecting means is counted.
; And a number of received test cells counter for the number, the test cell, separated PN pattern test to some
Each pattern is assigned in the order of generation of test cells.
A serial number and an error detection and correction code of the serial number.
The test cell used was, using said error detection correction code installed in the test cell, a sequence number error detection and correction means for checking whether or not an error in the sequence number of the cell is present, the PN pattern Loss detected by the means for detecting
When the two patterns are out of synchronization,
Monitor whether a reference PN pattern can be obtained again
To determine that other cells have been mixed,
The PN pattern loss of synchronization has been detected by the detecting means.
In the synchronous state of the two patterns, the serial number error
The serial number determined to be error-free by the detection and correction means
By comparing with the value of the reception test cell number counter,
The test cell is received normally in order.
Determining means for determining whether a cell loss has occurred, and a state determined to be normal by the determination of the determining means, or
In the synchronous state of the two patterns, the ratio of the comparing means
Bit that does not match in the test cell being transmitted.
An error bit counter that counts as an error bit, and the determination by the determination unit determines that the test cell is lost.
A lost cell counter that counts the number of cells and a cell determined to be mixed with other cells are determined by the determination unit.
ATM test method, characterized by comprising comprises a mixed cell counter for counting the Le number, the. 6. A test PN pattern is divided into several parts.
In an ATM test system in which the test cells carrying each of them are sequentially transmitted from the transmitting side to the transmission line in the ATM mode in order and the test cells are received or monitored, the test cells are detected from the transmission line. Test cell detection means, reference PN pattern generation means for generating a reference PN pattern that matches in bit units a pattern mounted on a cell detected by the test cell detection means, and reference PN pattern generation means A comparison unit that compares, on a bit-by-bit basis, a reference PN pattern generated by the method and a pattern mounted on the cell detected by the test cell detection unit; and monitoring a result of the comparison by the comparison unit. The PN pattern for use is determined that the two patterns are out of synchronization when the ratio of coincidence with the pattern mounted on the cell is below a certain value. PN pattern out-of-synchronization detecting means for causing the reference PN pattern generating means to re-create a reference PN pattern that matches the pattern mounted on the cell, and determining the number of cells detected by the test cell detecting means. A counter for counting the number of received test cells, wherein each test cell is divided into several test PN patterns, a serial number assigned in the order of generation of test cells, and error detection and correction of the serial number. Using a test cell to which a code is added, using an error detection and correction code mounted on the test cell, a serial number error detection and correction means for checking whether or not an error exists in the serial number of the cell; In the synchronized state of the two patterns detected by the PN pattern out-of-synchronization detecting means, an error is detected by the serial number error detecting and correcting means. By comparing been continuous number and determines that there is no and the value of the received test cell counter, the value of the sequence number and the received test cell number counter
If they match, it is determined that the test cells have been normally received in order, and the serial number is counted as the number of received test cells.
If it is larger than the value of the test cell, it is determined that test cell loss has occurred, and the serial number is counted by the reception test cell count.
If the value is smaller than the value of the pattern, the discriminating means for judging that the mixing of other cells has occurred; and comparison of the results of the comparison means, and the error bit counter for counting the no match bits as error bits occurring in the test cell during the transmission, the determination of the determination means, the number of cell it is determined that the loss of the test cell, the continuous From the value of the number,
A lost cell counter that counts by subtracting the value of the counter from the received test cell number counter.
An ATM test system comprising: a mixed cell counter that counts by subtracting a value of a number .