JP2770766B2 - ATM continuity test apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for testing ATM continuity characteristics, and more particularly, to a continuity characteristic of a virtual path or virtual channel virtually set by using an OAM cell for continuity test containing a pseudo-random pattern. The present invention relates to an apparatus and a method for testing an ATM continuity characteristic for testing an ATC.

[0002]

2. Description of the Related Art Generally, an ATM mode (Asynchronous T
In an ATM communication system that performs communication using fixed-length packets called ATM cells (hereinafter, referred to as cells) based on ransfer mode (asynchronous transfer mode), a virtual path (hereinafter, referred to as VP: Virtual Path) set between two points. ) And channel (hereinafter referred to as VC: Virtual Channel)
Data communication is performed via the. Conventionally, when testing the conduction characteristics of such VP and VC, a test OAM (Operation Administration Monitoring) is used.
Receiving the cell via the VP and VC under test,
The conduction characteristics are tested based on the normality (for example, Japanese Patent Application Laid-Open No. 5-244196).

FIG. 6 is a block diagram showing a conventional ATM continuity test apparatus. In FIG. 6, reference numeral 600 denotes a sequence number checker for checking a sequence number stored in a test OAM cell and indicating a transmission order. An abnormal cell counter 610 that counts abnormal cells detected by the sequence number check unit 600. A pseudo random pattern (Pseudo random pattern) 610 stored in the test OAM cell.
This is a pseudo-random pattern inspection unit for inspecting.

[0004] The received cell is input to an inspection target OAM cell extraction circuit 601 of the sequence number inspection unit 600, and only the test OAM cell to be inspected is extracted based on the header information of the cell. The OAM cell to be inspected extracted here is input to the sequence number extracting circuit 602 to extract the sequence number, and is input to the sequence number matching circuit 604. Sequence number counter 6
Numeral 03 indicates the sequence number to be received next by sequentially counting the sequence numbers. The sequence number matching circuit 604 outputs the sequence number extracted from the received OAM cell to be inspected and the sequence number to be received next. Is compared with

[0005] If the two sequence numbers do not match, it is determined that an error has occurred in the received OAM cell, and the received OAM cell is counted by the abnormal cell counter 605. On the other hand, the received cell is also input to the pseudo random pattern detection circuit 611 and the comparison circuit 612 of the pseudo random pattern inspection unit 610. The pseudo-random pattern detection circuit 611 detects a pseudo-random pattern from a received cell when the sequence number checker 600 determines that the cell reception order is normal.

In the pseudo-random-pattern synchronization protection circuit 613, when the pseudo-random pattern is out of synchronization, the pseudo-random pattern detected and received is fetched in advance and the coincidence of the pattern generated from the pseudo-random pattern is confirmed over a predetermined number of bits. By doing so, the synchronization of the pseudo random pattern is confirmed, and the synchronization state is output. Also,
In the synchronized state of the pseudo random pattern, a pseudo random pattern to be received next is generated from the pseudo random pattern detected immediately before based on the cyclic characteristic.

[0007] The comparison circuit 612 compares the pseudo-random pattern detected from the received cell in the synchronized state with the pseudo-random pattern to be received next. As a result of the comparison, if each bit of the two pseudo random patterns is different, the bit is regarded as an error bit and the error bit counter 61
4 and output as the number of error bits, and the number of abnormal cells and the number of error bits are output as a result of the conduction characteristic test.

[0008]

Therefore, in such a conventional ATM conduction characteristic testing apparatus and method, a pseudo random pattern having a relatively large number of bits is sequentially inspected for a received cell. Therefore, inspection must be completed before the next cell is input. In high-speed ATM communication, a large-capacity memory is provided as a reception cell buffer by predicting the burstiness of cells, and processing delay is reduced. We needed to make up for it. Further, when the reception cells arrive continuously, there is a possibility that the processing speed of the apparatus cannot keep up.
In such a case, the processing result is not output within one cell,
There is a problem in that the selection of the process for the next received cell, that is, the selection of the synchronization pull-in process or the pseudo-random pattern inspection process after synchronization is delayed, and the normal operation is not performed.

Furthermore, since the subsequent pseudo-random pattern continuously arrives at the time of synchronization pull-in, a pseudo-random pattern detection process from a received cell, a synchronization confirmation process by comparing a predetermined bit of the pseudo-random pattern, and a re-execution within one cell. There is a possibility that the pull-in process cannot be completed in time, and there is a problem that it is not possible to cope with the high speed, the cell fluctuation based on the asynchronous communication, the burst characteristic, etc. which are the characteristics of the ATM communication. An object of the present invention is to solve such a problem, and an ATM continuity test apparatus and method capable of accurately testing continuity of VP and VC even when cells arrive at high speed and continuously. It is intended to provide.

[0010]

In order to achieve the above object, an apparatus and a method for testing ATM continuity characteristics according to the present invention are provided in parallel with a received cell input, and a test object to be tested is provided. A continuity test cell inspection unit that performs synchronization pull-in processing and error detection processing of a pseudo random pattern stored in a cell, and outputs a synchronization state and the number of error bits as a result of the processing, and output from each continuity test cell inspection unit. Selection means for selecting and outputting any of the processing results as the inspection result for the inspection target cell, and instructing any one of the continuity test cell inspection means to perform synchronization pull-in processing as an out-of-synchronization processing. At the same time, an error detection process is instructed to the other as a process at the time of synchronization, and the inspection performed immediately before the cell to be inspected currently being processed is performed. When the synchronization state of the target cell is out of synchronization, an instruction is issued to switch the processing of each continuity test cell inspection means for the next inspection cell after the inspection cell currently being processed, and the switching of the inspection cell currently being processed is performed. And control means for instructing to switch the selection state of the first selection means with respect to the inspection result.

The continuity test cell inspection means may include a receiving cell
Are provided in parallel with each other and stored in the cell to be inspected.
Pull-in processing and error
-Perform detection processing in different phases, and
Output the synchronization status and the number of error bits as multiple
Pseudo-random pattern processing means and each pseudo-random pattern
Select one of the processing means and
Select and output as the processing result for the cell to be inspected
2 selecting means.

Further, the second selection means monitors the synchronization state output from each pseudo-random pattern processing means, and selects the synchronization state which is the earliest in the synchronization pull-in state. In addition, the continuity test cell inspection means may include a second
The number of error bits from the pseudo-random pattern processing means selected by the selection means is totalized and output for each cell to be inspected.

[0013]

Therefore, one of the continuity test cell inspection means is instructed to perform a synchronization pull-in process as an out-of-synchronization process, and the other is instructed to perform an error detection process as a synchronization process. If the synchronization state of the cell to be inspected is out of synchronization, switching of the processing of each continuity test cell inspection means for the next cell to be inspected is instructed, and the first selection means for the cell to be processed currently being processed is instructed. The selection state is switched.

Further, one of a plurality of pseudo-random pattern processing means provided in parallel with the reception cell is selected, and the processing result is selectively output as a processing result for the input inspection target cell. Further, the synchronization state output from each pseudo-random pattern processing means is monitored, and the synchronization state that is the earliest in the synchronization pull-in state is selected. Furthermore, the number of error bits from the pseudo-random pattern processing means selected by the second selection means is totaled and output for each reception cell.

[0015]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an ATM continuity test apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a test OAM cell to be inspected based on header information of a received cell 120. A test target OAM cell extraction circuit, 100 is a sequence number checker for checking a sequence number stored in the test OAM cell and indicating a transmission order;
Reference numeral 105 denotes an abnormal cell counter that counts abnormal cells detected by the sequence number inspection unit 100, and 106 generates various timing signals such as a timing clock 122 in synchronization with the reception timing of the extracted test OAM to be inspected. It is a timing generation circuit.

In sequence number checking section 100, 1
02 is a sequence number extracting circuit for extracting a sequence number from the test OAM cell, 103 is a sequence number counter for generating a sequence number to be received next based on the sequence number extracted immediately before, 104 is a test OAM cell And a sequence number matching circuit for comparing and matching the sequence number extracted from the sequence number with the sequence number to be received next.

Reference numeral 110 denotes a pseudo-random pattern inspection unit for inspecting a pseudo-random pattern stored in the test OAM cell. Reference numerals 200A and 200B are provided in parallel with the reception cells, and the inspection target OAM cell extraction circuit 101 OAM for testing the target cell signal 121 from the
If it indicates that the received cell 120
The pseudo random pattern stored in the pseudo random pattern is extracted. When the pseudo random pattern is out of synchronization, the synchronization is performed. In addition, an error bit of the pseudo random pattern following the pull in is checked. It is a continuity test cell inspection unit that detects bits.

Reference numeral 112 denotes an output 1 of one of the continuity test cell inspection units 200A and 200B based on the surface control signal 126.
A selection circuit (first selection means) for selecting the cells 23A and 123B and outputting the number of error bits 124 and the synchronization state signal 125 of the pseudo random pattern, and a continuity test cell inspection circuit 111 according to the synchronization state of the immediately preceding inspection target cell Part 200A,
A surface control circuit (control means) for outputting a surface control signal 126 for selecting any one of the surface control signals
6 is an operation control circuit (control means) that outputs operation control signals 127A and 127B for instructing the operation of the continuity test cell inspection units 200A and 200B based on the operation control signals C.

FIG. 2 shows a continuity test cell inspection section 200A, 20
0B.
20N is a pseudo-random pattern processing unit which is provided in parallel as 1 to N planes with respect to the reception cell 120 and performs synchronization pull-in of pseudo-random patterns stored in the reception cell 120 and error bit detection at different phases.
A pull-in detection circuit 11 monitors the pull-in detection signals 231 to 23N from the respective surfaces when the pseudo-random pattern is out of synchronization, selects the one that has completed the pull-in first, and outputs it as a pull-in detection signal 241 (second Selection means), 212 is a 1 / N selection circuit (second selection means) for selecting the number of pseudo-random pattern error bits counted on each surface, from which the completion of synchronization has been detected.
It is.

Reference numeral 213 denotes an error bit number counting circuit for counting the number of error bits selected and output from the 1 / N selection circuit 212 for one cell. Reference numeral 214 denotes a synchronization pull-in detection signal 241 from the pull-in detection circuit 211 and the totaled error bits. An out-of-synchronization detection circuit 215 for detecting out-of-synchronization based on the number is a latch circuit for holding and outputting the total number of error bits and the out-of-synchronization detection output. In the pseudo-random pattern processing units 201 to 20N, reference numeral 221 denotes an input selection circuit for selecting and outputting either a pseudo-random pattern stored in a received cell or a pseudo-random pattern generated inside, and 222 denotes a selected cell. This is a pseudo-random pattern generation circuit that generates a pseudo-random pattern to be received next based on the pseudo-random pattern.

A comparison circuit 223 compares the pseudo-random pattern of the received cell with the generated pseudo-random pattern.
Reference numeral 224 denotes a pull-in protection circuit that detects a pull-in state based on a comparison result and a predetermined pull-in condition when a pseudo-random pattern is out of synchronization, and 225 controls the input selection circuit 221 based on the pull-in state and the operation control signal 127. The input control circuit 226 performs addition when the synchronization pull-in is confirmed, and when the synchronization state is confirmed, the addition control circuit 227 that adds only the bit to be inspected in the comparison result based on the addition instruction. An error bit number adding circuit for adding an error for a predetermined bit in the comparison result.

FIG. 3 is an explanatory diagram showing the configuration of a general test OAM cell. Reference numerals 301 and 302 denote VP identifiers (hereinafter, referred to as VPI) and VC identifiers (hereinafter, referred to as VCI) for identifying VPs and VCs. ) And 303 are VPI
Header error information (hereinafter, referred to as HEC) for checking an error in header information including the H.301 and VCI 302;
304, an OAM type indicating the type of the test OAM cell;
05 is a sequence number indicating the transmission order of the continuity test cells;
Reference numeral 306 denotes sequence number protection information for checking an error of the sequence number 305, and reference numeral 307 denotes a pseudo random pattern generated based on a predetermined generator polynomial.

Here, a general cell inspection method using a pseudo random pattern will be described. The pseudo-random pattern is a bit string (cyclic code) generated based on a predetermined generator polynomial and having a relatively long cycle. Has the property of being able to generate Therefore, by dividing these pseudo-random patterns, storing them in each cell in order, transmitting the divided cells, and confirming the continuity of the pseudo-random patterns, the conduction characteristics of VP and VC can be tested. .

For example, as shown in FIG. 3, several bits required to generate a pseudo-random pattern from a predetermined position in the pseudo-random pattern 307, here 15 bits, are taken in as generated bits 311 and are based on the same generator polynomial as the transmitting side. Then, the next consecutive pseudo-random pattern is predicted from the generated bits 311 and compared with the actually received pseudo-random pattern. Thus, a predetermined number of bits, 33 bits in this case, immediately after the generation bit 311 are pulled in and the detection bits 31
2, and if all bits match, it is determined that the pseudo-random pattern generated on the transmission side and the pseudo-random pattern generated on the reception side are synchronized, that is, a synchronization pull-in state has been reached. As a result of the comparison with the pseudo random pattern, if they do not match, they are counted and output as error bits.

If at least one of the pull-in detection bits 312 detects a mismatch, it is determined that synchronization pull-in has failed, and if an error bit is detected at a predetermined rate or more in the synchronization pull-in state, it is determined that synchronization is lost. In either case, the state becomes out of synchronization. In such a case, the above-described synchronization pull-in processing is repeatedly performed. Note that the position and the number of bits of the above-described pull-in detection bit 312 are called a synchronization pull-in condition, and the error bit detection rate is called an out-of-sync condition or a backward synchronization protection condition.

Next, with reference to FIG. 4, the operation of the pseudo random pattern inspection unit 110 will be described as an operation of the present invention. The configuration and operation of sequence number checking section 100 are the same as those of sequence number checking section 600 (FIG. 6).
), And the description is omitted here. FIG. 4 is a timing chart showing the operation of the continuity test cell inspection units 200A and 200B.

In the following description, the continuity test cell inspection section 200A is referred to as the A side, and the continuity test cell inspection section 200B is referred to as the B side.
We call it plane. Further, in the out-of-synchronization process, a synchronization pull-in condition is satisfied for a pseudo random pattern of a predetermined cell to be inspected, and the inspection until all subsequent pseudo random patterns of the cell are completed is called a synchronization pull-in state. The case where the synchronization has been completed at the time when the inspection has been completed for all the subsequent pseudo-random patterns, that is, the case where the synchronization has been determined, is referred to as a synchronization state.

In the figure, reference numeral 120 denotes a reception cell, 121
Is a target cell signal indicating that the receiving cell 120 is a cell to be inspected, 128 is generated from the target cell signal 121,
The immediately preceding target cell signal indicating that the cell processed immediately before is the cell to be inspected, 200A and 200B indicate the operating states of the A and B planes, and 123A and 123B indicate the synchronization states and the number of error bits on the A and B planes. Reference numeral 122 denotes a timing clock, 125 denotes a synchronization state signal from the selection circuit 112, and 126 denotes a plane control signal from the plane control circuit 111.

Out of synchronization is set as an initial state. In this case, since the synchronization state signal 125 indicates an out-of-synchronization state, the operation control signals 127A and 127B cause A / A
Out-of-synchronization processing is assigned to one of the B surfaces, for example, the A surface. Here, when the reception cell # 1 is input, the synchronization pull-in process of the pseudo random pattern is started as the process at the time of the out-of-sync by the A side. In this case, the result of the synchronization pull-in processing by the side A, that is, the determination of the synchronization pull-in condition and the out-of-synchronization condition is not output at the same time when the reception of the reception cell # 1 is completed, but is delayed due to the processing speed.

Receiving cell # 2 is received following receiving cell # 1, and error detection processing is started on the A side as synchronization processing in preparation for establishing synchronization in receiving cell # 1. Accordingly
As shown in FIG. 4, in the A-side operation 200A, the cell #
Reference simulation performed in real time according to the input of 1.
Even after the comparison process with the random pattern is completed,
In a separate tabulation processing circuit section located after the processing circuit section
By aggregation processing to determine the result of synchronization establishment
Since the processing at the time of loss of synchronization with cell # 1 is delayed, cell # 2
Reference pseudo-randomly implemented in real time in response to input
Some overlap with comparison processing with random patterns.
On the B side, the synchronization pull-in process is started as a process at the time of loss of synchronization in preparation for the failure of synchronization pull-in of the reception cell # 1, and is performed in parallel with the reception cell # 2. Subsequently, during the reception of the reception cell # 2, the out- of- synchronization processing for the reception cell # 1 by the A-side is completed, and the processing result is output to the selection circuit 112.

The output 123A is latched by the selection circuit 112 based on the timing at which it is determined, that is, the timing clock 122, and is output as the number of error bits 124 and the synchronization state signal 125. If the synchronization state signal 125 indicates a synchronization state, the plane control circuit 111 outputs a plane control signal 126 for selecting the plane for which synchronization has been completed, that is, the plane A, and the selection circuit 112
Selects the output 123A from the A side among the processes performed in parallel on the reception cell # 2.

Subsequently, for the reception cell # 3, the operation control signals 127A and 127B from the operation control circuit 113 based on the plane control signal 126 are used in the same manner as described above, so that synchronization processing is performed on the plane A and synchronization is performed on the plane B. The disconnection process is started. Further, the processing for the reception cell # 2 ends while the processing for the reception cell # 3 is completed, and the output 123A from the A side selected by the selection circuit 112 is output via the selection circuit 112. Note that the output 123B from the B side is the received cell # 2
, But is ignored here.

Subsequently, the operation control is performed for the reception cell # 4 in the same manner as described above. Here, when an error occurs in the pseudo random pattern of the reception cell # 3 and the out-of-synchronization condition is satisfied, the output is the output 12 of the A side.
3A is output during the processing of the reception cell # 4. The output 123A is latched and output by the selection circuit 112 based on the timing clock 122. In this case, the synchronization state signal 125 indicates that the synchronization has been lost.

The surface control circuit 111 outputs the synchronization state signal 1
Since 25 indicates out-of-synchronization, it recognizes that out-of-synchronization has occurred on the currently selected A-side, and outputs a plane control signal 126 for selecting the B-side. As a result, the operation control circuit 113 performs processing for the reception cell # 5 as
The operation control signal 127A instructs the side A to perform the out-of-synchronization processing, and the operation control signal 127B
Instructs the surface to perform synchronization processing. Also, the selection circuit 112
Selects the output 123B of the B side as an input.

Therefore, out of synchronization with reception cell # 4
The output 123B from the surface B that has been subjected to the
12 is selected. In this case, a synchronization state signal 125 indicating the completion of the synchronization pull-in is output, and as the subsequent processing, the processing at the time of synchronization is performed on the side B, and the processing at the time of de- synchronization is performed on the side A in parallel. Will be done. If a non-target cell that is not to be inspected is input following the reception cell # 5, the operation control circuit 113 outputs the target cell signal 1
21, and recognizes the operation control signal 127A,
An operation stop instruction is output to each of the A and B surfaces by 127B. As a result, the operations on the surfaces A and B are stopped while maintaining the state immediately before the input of the non-target cell.

Further, when the receiving cell # 6 to be inspected is input following the non-target cell, the operation control circuit 113
Instructs the out- of- synchronization processing to the A-side and the in- synchronization processing to the B-side in the same manner as the previous instruction by the operation control signals 127A and 127B. , The operation is restarted based on the held processing content.

As described above, the continuity test cell inspection unit for performing the synchronization pull-in process of the pseudo-random pattern stored in the reception cell and the error detection process after the synchronization pull-in is provided in parallel with the reception cell. In the meantime, the process at the time of synchronization is performed, and the process at the time of out- of- synchronization is performed. This is to make a selection for the result. Therefore, the processing is performed on a reception cell from which a pseudo random pattern can be accurately read after a processing result for one reception cell is output by one continuity test cell inspection unit as in the related art. In comparison with the case, it is possible to perform synchronization pull-in for the pseudo random pattern in a shorter time, and it is possible to perform more accurate error detection processing, even when cells arrive quickly and continuously. , VP and VC can be accurately tested. In particular, pseudo-la
As mentioned above, the continuity of
It is necessary to ensure that the same continuity test cell inspection section
Process from out-of-synchronization processing to synchronization processing.
By changing the pseudo-line
For subsequent processing during synchronization based on random patterns.
Is it easy to generate a pseudo-random pattern?
Continuity of the pseudo-random pattern
Synchronous processing can be performed frequently.

Next, the operation of the continuity test cell inspection units 200A and 200B will be described with reference to FIG. FIG.
Is a timing chart showing the operation of the continuity test cell inspection units 200A and 200B, where 250 is a pseudo-random pattern stored in the reception cell, 251 to 25N are pseudo-random pattern processing units 201 to 20N, that is, 1 to N planes. An area of a pseudo-random pattern for performing synchronization pull-in processing,
Reference numerals 231 and 232 denote pull-in detection signals output from the first and second surfaces, reference numeral 241 denotes a synchronization pull-in detection signal indicating the synchronization pull-in state of the surface where synchronization pull-in is first detected by the pull-in detection circuit 211, 501 denotes a generated bit, and 502 denotes a generated bit. This is a pull-in detection bit.

Operation control signal 127 indicating processing at the time of loss of synchronization
In response to A and 127B, the pull-in detection circuit 211 initializes the selected state to a state where none of the surfaces is selected. Thus, the same applies to the 1 / N selection circuit 212. Also, the input control circuit 225 and the pull-in protection circuit 2 of each surface
Numeral 24 reads a pseudo-random pattern from a predetermined phase, that is, a bit position assigned to itself, to start the synchronization pull-in process, and the error bit number adding circuit 227 and the error bit number counting circuit 213 clear the count number.

As shown in FIG. 3, each of the 1st to Nth planes reads the generated bit 501 and the pull-in detection bit 502 from the pseudo random pattern 250 to check whether a predetermined synchronization pull-in condition is satisfied. In this case, each one
The operation phases are different between the Nth plane and the Nth plane, and bits at positions corresponding to the respective phases are taken in from the pseudo random pattern 250. Here, the generated bits 501 are generated from the first bit of the pseudo random pattern 250 from one side.
And when the pull-in detection bit 502 is read, 2
The plane reads the generated bit and the pull-in detection bit from the bit position immediately after the plane, and reads the N-plane at a continuous phase.

Therefore, for example, on one side, the input selection circuit 221 is controlled to the cell input side so that the pseudo random pattern 2
The generated bits 501 are read from the first bit of the 50. After the reading is completed, the input selection circuit 221 is controlled to the pseudo random pattern generation circuit 222 side, and the pseudo random pattern to be received next by the pseudo random pattern generation circuit 222, that is, the reference pull-in detection bit, is Generate sequentially. The comparison circuit 223 compares the pull-in detection bit 502 input from the cell input side with the pull-in detection bit for reference.

The pull-in protection circuit 224 determines whether or not the synchronization pull-in condition is satisfied based on the result of this comparison, and outputs a pull-in detection signal 231 if the condition is satisfied. After completion of the reading of the pull-in detection bit, assuming the completion of the synchronization pull-in, the subsequent bits are read, and the respective bits are compared in the same manner as described above to continue the error checking process. The error bit number adding circuit 227 counts and outputs the number of bits whose comparison has become inconsistent every predetermined number of bits (one word) from the bit immediately after the pull-in detection bit 502 under the control of the addition control circuit 226.

On the other hand, if the synchronization pull-in condition is not satisfied, the input selection circuit 221 is switched to the cell input side, and the generation bit 501 is read from a predetermined bit position of the pseudo random pattern 250 as described above. The synchronization pull-in process is started again, and the addition control circuit 2
By the control of 26, the count number of the error bit number adding circuit 227 is cleared. In this manner, the pull-in detection signals 231 to 23N from the respective surfaces having different operation phases are input to the pull-in detection circuit 211, and the pull-in detection signals 232 of the two surfaces (202) whose synchronization has been completed first, for example, are selected. Then, it is output as a synchronization pull-in detection signal 241.

Further, under the control of the pull-in detection circuit 211, the 1 / N selection circuit 212 selects and outputs the output of the error bit number adding circuit 227 of the surface on which synchronization pull-in has been completed first as the number of error bits for the current reception cell. The error bit number is input to the error bit number counting circuit 213 for each predetermined bit number (1 word), and is counted and output for each received cell. Loss of synchronization detection circuit 214
Is the synchronization pull-in signal 2 from the pull-in detection circuit 211.
If 41 indicates a failure in synchronization pull-in in the same cell, or if the total number of error bits exceeds a predetermined value, that is, if an out-of-sync condition is satisfied, it is determined that out-of-sync has occurred.

The output of the out-of-synchronization detection circuit 214 and the output of the error bit number counting circuit 213 are latched by the latch circuit 215 at the timing when the test determination processing for the pseudo-random pattern of the received cell is determined, and the continuity test cell test section 200A and 200B, that is, the outputs 123A and 123B of the A and B planes. The pseudo-random patterns divided and stored in successive test OAM cells have bit continuity, and are stored in the next cell when the bit comparison operation for one cell is completed. In order to perform the bit comparison operation of the pseudo-random pattern generated, the output of the pseudo-random pattern generation circuit 222 is held.

As described above, a plurality of pseudo-random pattern processing units 201 to 20N (1 to N planes) for performing synchronization pull-in of a pseudo-random pattern and detecting an error are provided in parallel with respect to a reception cell and operated at different phases. At the same time, one of the pseudo-random pattern processing units is selected and its output is output as a synchronization state with respect to a received cell and an error detection result. Compared to the case where the synchronization pull-in has failed, the determination of the synchronization pull-in condition is performed in parallel based on the phase slightly shifted, without further waiting for the time required for determining the synchronization pull-in condition when the synchronization pull-in fails, When synchronization pull-in fails, re-pull processing in the same cell will be performed,
Synchronization can be completed in a relatively short time.

The pull-in selection circuit 211 selects the one of the plurality of pseudo-random pattern processing units that has completed the pull-in operation at the earliest time, and counts the number of error bits counted there by the 1 / N selection circuit 212. Since the selection is made prior to the detection, the synchronization pull-in can be completed in a shorter time. Further, an error bit number counting circuit 213 is provided for counting the number of error bits selected and output by the 1 / N selection circuit 212 on a cell basis, and outputs the number of error bits for each cell. The conduction characteristics can be inspected for each cell, and the conduction characteristics can be confirmed in more detail.

The pseudo-random pattern processing units 201 to 201
The number of 20N (1 to N planes) depends on the total number of bits of the generation bit 501 and the pull-in detection bit 502 and the time from the end of the reading of the pull-in detection bit 502 until the input selection circuit 221 can be controlled based on the synchronization pull-in result. Depends on the required time td. Further, in the above description, the case where each surface is operated in a continuous bit phase of the pseudo random pattern has been described. However, the present invention is not limited to this. For example, several bits may be provided as an interval between each phase. Alternatively, each phase may partially overlap, and can be set arbitrarily according to the required test accuracy.

[0049]

As described above, according to the present invention, the continuity test cell inspection means for performing the synchronization pull-in process and the error detection process of the pseudo-random pattern stored in the inspection target cell is provided in parallel with the reception cell. And a first selecting means for selecting and outputting one of the processing results output from each of the continuity test cell inspection units, and performing a process when out of synchronization with one of the continuity test cell inspection means. When instructing the synchronization pull-in process as the other, and instructing the other to perform the error detection process as the synchronization process, if the synchronization state of the immediately prior inspection target cell is out of synchronization,
The instruction of switching the processing of each continuity test cell inspection unit for the next cell to be inspected and the selection state of the first selection unit for the processing result of the cell being processed is given.

Therefore, after the processing result for one reception cell is output by one continuity test cell inspection unit as in the conventional case, the processing is performed on the reception cell from which the pseudo random pattern can be accurately read. Compared to the case of the above, the synchronization can be performed to the pseudo random pattern in a shorter time, and more accurate error detection processing can be performed. In this case, the conduction characteristics of VP and VC can be accurately tested without requiring a large-capacity cell buffer.

Further, as a continuity test cell inspection means, a synchronization pull-in process and an error detection process of the pseudo-random patterns stored in the cells with different phases are performed.
A plurality of pseudo-random pattern processing means for outputting a synchronization state and the number of error bits as the processing result are provided in parallel with the received cell, and any one of the pseudo-random pattern processing means is selected. Is selected and output as the processing result for the received cell, so that the synchronization pull-in condition can be determined when the synchronization pull-in fails, compared with the case where the synchronization pull-in is performed by one pseudo-random pattern processing unit as in the related art. The determination of the synchronization pull-in condition is performed for each phase slightly shifted with time without further waiting for the required time, and the synchronization pull-in can be completed in a relatively short time.

Further, the synchronization state output from each pseudo-random pattern processing means is monitored, and the synchronization state that has become the earliest synchronization state is selected, so that synchronization synchronization can be completed in a shorter time. Becomes Further, since the number of error bits from the pseudo-random pattern processing means selected by the selection means is totalized and output for each reception cell, it is possible to inspect the continuity characteristics for each test OAM cell. The conduction characteristics can be checked.

[Brief description of the drawings]

FIG. 1 is a block diagram of an ATM continuity test apparatus according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a continuity test cell inspection unit of FIG. 1;

FIG. 3 is an explanatory view showing a test OAM.

FIG. 4 is a timing chart showing a selection operation of a continuity test cell inspection unit.

FIG. 5 is a timing chart showing the operation of the pseudo random pattern processing circuit.

FIG. 6 is a block diagram of a conventional ATM continuity test device.

[Explanation of symbols]

100: Sequence number inspection unit, 101: OA to be inspected
M cell extraction circuit, 102... Sequence number extraction circuit, 1
03: sequence number counter, 104: sequence number collation circuit, 105: abnormal cell counter, 106: timing generation circuit, 110: pseudo random pattern inspection unit,
111: surface control circuit (control means), 112: selection circuit (first selection means), 113: operation control circuit (control means), 200A, 200B: continuity test cell inspection section, 20
1 to 20N: pseudo-random pattern processing unit, 211: pull-in detection circuit (second selection means), 212: 1 / N selection circuit (second selection means), 213: error bit number counting circuit, 214: out of synchronization Detection circuit, 215 latch circuit, 221 input selection circuit, 222 pseudo-random pattern generation circuit, 223 comparison circuit, 224 synchronization protection circuit, 225 input control circuit, 226 addition control circuit, 2
27 ... Error bit number adding circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 11/12 H04L 11/20

Claims (5)

(57) [Claims] An OAM cell for a predetermined test is received via a virtual path or a virtual channel, and the pseudo-random pattern stored in the OAM cell for the test is checked for normality. In an ATM continuity test apparatus for testing continuity characteristics of a channel, a synchronization pull-in process and an error detection process of a pseudo-random pattern provided in parallel with a reception cell input and stored in a cell to be inspected to be inspected. And a continuity test cell inspection means for outputting a synchronization state and the number of error bits as a processing result, and selecting one of processing results output from each continuity test cell inspection unit as an inspection result for the inspection target cell. First selecting means for outputting, and one of each continuity test cell inspecting means Instruct one to perform synchronization pull-in processing as out-of-synchronization processing, and instruct the other to perform error detection processing as synchronization processing, and check the synchronization state of the inspection target cell processed immediately before the inspection target cell currently being processed. If it is out of synchronization, it instructs to switch the processing of each continuity test cell inspection unit for the next cell to be inspected after the cell currently being inspected,
An ATM continuity characteristic testing apparatus, comprising: control means for instructing switching of a selection state of a first selection means with respect to an inspection result of an inspection target cell currently being processed. 2. An ATM continuity test apparatus according to claim 1.
In the above, the continuity test cell inspection means is provided in parallel with the reception cell, and is provided for the cell to be inspected.
Synchronization processing of the stored pseudo-random pattern
And error detection processing in different phases, and
Outputs the synchronization status and the number of error bits as the processing result
Select one of multiple pseudo-random pattern processing means and each pseudo-random pattern processing means
And processing the processing result for the inspection target cell.
An ATM continuity test device, comprising: a second selecting means for selecting and outputting a result. 3. An apparatus for testing ATM continuity characteristics according to claim 2.
In the above, the second selecting means is configured to execute the processing from each pseudo random pattern processing means.
Monitors the output synchronization status and provides the earliest synchronization status.
An ATM continuity characteristic test apparatus , wherein a selected one is selected . 4. The ATM conduction characteristic according to claim 2 or 3.
In the test apparatus, the continuity test cell inspection means may include a pseudo random pattern processing unit selected by the second selection unit.
The number of error bits from control means for each cell to be inspected
An ATM continuity characteristic test device comprising an error bit number counting means for outputting . 5. A virtual pass or virtual channel.
Receiving a predetermined test OAM cell via the
Of the pseudo-random pattern stored in the OAM cell
By checking the homeostasis, the virtual path or
ATM continuity test to test continuity characteristics of virtual channel
In the test method, it is provided in parallel with the received cell input and
Pseudo random pattern stored in the cell to be inspected
Synchronization and error detection
And the number of error bits and the synchronization status
And a continuity test cell inspection means for outputting a test result.
Select the deviation as the inspection result for the inspection target cell
Output means for selecting one of the continuity test cell inspection means.
Instruct synchronization pull-in processing as processing at the time of disconnection
To the other, instruct error detection processing as synchronization processing
Inspection performed immediately before the cell currently being inspected
If the synchronization status of the target cell is out of synchronization,
Each continuity of the cell under test to the next cell under test
While instructing to switch the processing of the test cell inspection means,
First selection for the inspection result of the cell to be inspected currently being processed
That the selection state of the selection means is switched and instructed.
ATM continuity characteristic test method, characterized in that it comprises.