JP2737771B2 - ATM connection test system and receiving unit of ATM connection test system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a virtual path (V) set as a connection between a transmission unit and a reception unit.
OAM (operation administration monitoring) in an ATM (asynchronous transfer mode) system that communicates using P) or a virtual channel (VC)
Regarding functions, especially VPs set as connections
Or, it relates to an ATM connection test method for testing a VC.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication (Kokai) No. 5-244196 discloses a VP test system which enables detection of mis-distributed cells and lost cells. Japanese Patent Application Laid-Open No. Hei 5-183573 discloses a test method capable of effectively performing a VP or VC continuity test, a characteristic test, and a test for isolating a failure point in a transmission line even if cell loss or mis-distribution frequently occurs. ing.

Conventionally, as shown in FIG. 3, this type of test system includes a transmitting unit 31 and a receiving unit 32, and an ATM system for transmitting and receiving a series of ATM cells between the transmitting unit 31 and the transmitting unit 32. It is used to test a VP or VC formed as a transmission path (connection) 33 between the unit 31 and the receiving unit 32 to measure the line quality.

In such an ATM system, in a normal communication state, an input signal IN provided in a cell form is transmitted from a transmission unit 31 to a reception unit 32 via a transmission line 33.

In order to test VP or VC as the transmission path 33, the transmission unit 31 includes a PN pattern generation circuit 41 for generating a PN (pseudo-noise) pattern, and a sequence number counter circuit for counting and outputting a sequence number. And a test cell insertion circuit 43 for inserting a PN pattern and a sequence number into the transmission data as test cells.

The receiving section 32 detects a test cell from the received signal as a detection cell, and detects a PN pattern and a sequence number from the detection cell as a detection PN pattern and a detection sequence number. Circuit 44 that latches and outputs
And the detection PN pattern of each detection cell is synchronized. When the detection PN pattern of each detection cell is synchronized, a control signal indicating synchronization is output, and the detection PN pattern of each detection cell is synchronized. If not, a synchronization determination circuit 45 that outputs a control signal indicating asynchronous, a sequence number comparison circuit 46 that checks the continuity of the detected sequence numbers and outputs the number of lost cells and the number of mis-distributed cells from the difference, and It has a lost cell number counter 47 for counting the number of cells and an incorrectly distributed cell number counter 48 for counting the number of incorrectly distributed cells.

The sequence number comparing circuit 46 checks the continuity of the detected sequence number only when the control signal indicating the synchronization is received (ie, when the cell is a test cell) as described above, and determines the loss from the difference. An operation of outputting the number of cells and the number of mis-distributed cells is performed, and an area corresponding to a sequence number when the cell is not a test cell is erroneously recognized as a sequence number to prevent malfunction.

Referring to FIG. 3 in addition to FIG. 3, sequence number comparing circuit 46 counts the number of detected cells as a count value, and has an internal reference counter that increases the count value by one each time a detected cell arrives. And compares the count value of the internal reference counter with the sequence number of the test cell that has arrived. The sequence number comparison circuit 46
When the control value indicating the synchronization is received, the count value of the internal reference counter is compared with the test cell sequence number.If the former is smaller, it is considered that test cell loss has occurred during that time, and the difference is regarded as the lost cell counter. 47, and the difference is added to the count value of the internal reference counter so that the count value of the internal reference counter matches the test cell sequence number. Conversely, if the former is large, an error in the distribution of test cells has occurred during that time. The difference is output to the mis-distributed cell number counter 48, and the difference is subtracted from the count value of the internal reference counter so that the count value of the internal reference counter matches the test cell sequence number.

[0009]

However, in this system, the number of losses / the number of mis-distributions is determined by the sequence number of the test cell with which the PN synchronization has been established. There is a disadvantage that the number of cells is not counted. In other words, when a test cell having a flow as shown in FIG. 4 arrives, each of the counters of the number of lost cells and the number of mis-distributed cells has a small value only when loss and mis-distribution occur consecutively. Not done.

In order to more accurately measure the line quality of a connection, it is necessary to consider a case where a loss and an incorrect distribution occur continuously.

Accordingly, an object of the present invention is to provide an ATM connection test system capable of accurately counting the number of lost cells and the number of mis-distributed cells even when a loss and a mis-distribution occur consecutively, thereby enabling a more accurate connection test. Is to provide.

Another object of the present invention is to provide an ATM connection test capable of performing a more accurate connection test by accurately counting the number of lost cells and the number of mis-distributed cells even when losses and mis-distributions occur continuously. It is to provide a receiving unit of a system.

[0013]

According to the present invention, there is provided an ATM connection test system for testing a connection between the transmitting unit and the receiving unit in an ATM system having a transmitting unit and a receiving unit. A PN pattern generation circuit that generates a PN pattern, a sequence number counter that outputs a sequence number representing a test cell number, a test cell insertion circuit that inserts the PN pattern and the sequence number as test cells into transmission data, A receiving circuit for detecting the test cell as a detection cell from a received signal, and detecting the PN pattern and the sequence number from the detection cell as a detection PN pattern and a detection sequence number; and The detection PN pattern is synchronized for each detection cell, and the detection P of each detection cell is synchronized. When the synchronization pattern is established, it outputs a control signal indicating synchronization, the detected PN of each detection cell
When the pattern is not synchronized, it has a synchronization determination circuit that outputs a control signal indicating asynchronous, and an internal reference counter that counts the number of the detection cells as a count value, and when a control signal indicating the synchronization is received. Comparing the detection sequence number with the count value, and when the detection sequence number is larger than the count value, outputs the difference between them as the number of lost cells, and compares the count value of the internal reference counter with the detection sequence. When the detected sequence number is smaller than the count value, the difference between the two is output as the number of mis-distributed cells,
A sequence number comparison circuit that sets the count value of the internal reference counter to a value equal to the detection sequence number, and a detection number of the detection cell while the sequence number comparison circuit continuously outputs a control signal indicating the asynchronous state. The number of out-of-sync cells that counts the number as the number of consecutively out-of-sync cells that are out of synchronization, and the number of continuously out-of-sync cells in the out-of-sync cell number counter and the sequence number comparison circuit. A comparison / difference circuit that compares the output number of erroneous cells and outputs the difference if they do not match, and compares the difference output by the comparison / difference circuit with the error output by the sequence number comparison circuit. A first adding circuit for adding the number of cells to the number of cells and outputting the result, and the difference output by the comparing / differential circuit to the sequence number comparing circuit. A second adding circuit that adds the number of lost cells output by the second adding circuit to output the number of lost cells, an erroneous cell number counter that counts an output value of the first adding circuit as a total erroneous cell number, An ATM connection test method is provided, comprising: a lost cell counter for counting the output value of the adder circuit as the total number of lost cells.

According to the present invention, in order to test a connection between the transmitting unit and the receiving unit in an ATM system having a transmitting unit and a receiving unit, the transmitting unit includes a PN pattern generating unit for generating a PN pattern. An ATM connection test system comprising a circuit, a sequence number counter for outputting a sequence number representing a test cell number, and a test cell insertion circuit for inserting the PN pattern and the sequence number as test cells into transmission data. A receiving circuit for detecting the test cell as a detected cell from a received signal and detecting the PN pattern and the sequence number from the detected cell as a detected PN pattern and a detected sequence number; The detected PN pattern is synchronized with the detected PN pattern of each detected cell. A synchronization determination circuit that outputs a control signal indicating synchronization when the detection cells are synchronized, and outputs a control signal indicating asynchronous when the detection PN pattern of each detection cell is not synchronized; Has an internal reference counter that counts the number as a count value, and when receiving a control signal indicating the synchronization, compares the detection sequence number with the count value, and when the detection sequence number is larger than the count value. Outputting the difference between the two as the number of lost cells, and making the count value of the internal reference counter equal to the detection sequence number,
When the detection sequence number is smaller than the count value, a difference between the two is output as the number of mis-distributed cells, and a sequence number comparison circuit that sets the count value of the internal reference counter to a value equal to the detection sequence number; An out-of-synchronization cell number counter that counts the number of the detected cells while the sequence number comparison circuit continuously outputs the control signal indicating the non-synchronization as the number of erroneously distributed cells that are out of synchronization; A comparison / difference comparing the number of consecutively out-of-sync cells in the out-of-sync cell number counter and the number of incorrectly-arranged cells output by the sequence number comparison circuit, and outputting a difference if they do not match. And the difference output by the comparison / difference circuit is added to the number of mis-distributed cells output by the sequence number comparison circuit and output. A first adding circuit, the comparing /
A second adding circuit that adds the difference output by the difference circuit to the number of lost cells output by the sequence number comparing circuit and outputs the added value, and uses an output value of the first adding circuit as a total number of mis-distributed cells. An ATM connection test type receiving section is provided, which has a counter for counting the number of mis-distributed cells and a counter for counting the number of lost cells that counts the output value of the second adder circuit as the total number of lost cells.

According to the present invention, the number of lost cells and the number of mis-distributed cells can be accurately counted up to the case where losses and mis-distributions occur consecutively, that is, the case where a double failure is considered.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an ATM according to an embodiment of the present invention.
Only the receiving unit of the connection test system is shown, and the transmitting unit 31 shown in FIG.
And a PN pattern generation circuit 41, a sequence number counter circuit 42, and a test cell insertion circuit 43 are omitted.

The detection circuit 11, the synchronization determination circuit 12,
And the sequence number comparing circuit 13 corresponds to the detecting circuit 4 shown in FIG.
4, synchronization determination circuit 45, and sequence number comparison circuit 4
The same operation is performed with the same configuration as in FIG. The lost cell number counter 17 and the mis-distributed cell number counter 19 in FIG. 1 have the same configuration as the lost cell number counter 47 and the mis-distributed cell number counter 48 in FIG.

In the receiving section shown in FIG. 1, an out-of-synchronization counter 14, a comparison / difference circuit 15, and addition circuits 16 and 1
8 is newly provided.

Referring to FIG. 2 in addition to FIG. 1, out-of-synchronization cell number counter 14 counts the number of detected cells while sequence number comparison circuit 13 continuously outputs a control signal indicating asynchronous. , And counts as the number of erroneously delivered cells that are continuously out of synchronization. The comparison / difference circuit 15 compares the number of consecutively out-of-sync cells in the out-of-sync cell number counter 14 with the number of out-of-sync cells output by the sequence number comparison circuit 13, and if they do not match, the number is compared. Output the difference. The addition circuit 18 adds the difference output from the comparison / difference circuit 15 to the number of mis-distributed cells output from the sequence number comparison circuit 13 and outputs the result. The adder circuit 16 performs the comparison /
The difference output by the difference circuit 15 is added to the number of lost cells output by the sequence number comparison circuit 13 and output. The misplaced cell number counter 19 counts the output value of the adding circuit 18 as the total number of misplaced cells. The lost cell counter 17 counts the output value of the adding circuit 16 as the total number of lost cells.

Hereinafter, the operation of the receiver in FIG. 1 will be described in detail with reference to FIGS.

Upon receiving the test cell, the detection circuit 11 determines that the test cell is a test cell when detecting a predetermined specific identifier, and latches and outputs an area corresponding to a PN pattern and a sequence number.

The area determined to be a PN pattern is subjected to synchronization pull-in by the synchronization determination circuit 12, and synchronization is established when the number reaches the predetermined number of backward protection stages. After the synchronization is established, the synchronization determination circuit 12 compares the bits of the predetermined PN pattern with the PN pattern of the input test cell and counts the number of errors. When the number of errors exceeds a predetermined value of the number of forward protection stages in one cell, the synchronization is determined to be out of synchronization, and synchronization is pulled in again from the head of the next test cell. If a cell that is not a test cell attempts to pull in the synchronization in the synchronization determination circuit 21 due to an erroneous cell distribution, the number of error bits exceeds the number of protection stages and the synchronization is lost because the cell is not a PN pattern. Also, when a test cell loss occurs, a series discontinuity occurs between the PN pattern with the next test cell,
Similarly, synchronization is lost.

The continuity of the area determined as the sequence number is checked by the sequence number comparing circuit 13. The sequence number comparison circuit 13 has an internal reference counter, which operates in expectation of indicating the sequence number of the input test cell, and is incremented by one each time a cell arrives. Therefore, in a normal operation in which no loss / misplacement occurs, the two always take the same value. When a test cell loss occurs, the sequence number of the test cell with which synchronization has been established next indicates a value greater than the internal reference counter, and the difference is regarded as the number of lost cells and output to the comparison / difference circuit 15. If a test cell mis-distribution occurs, the internal reference counter indicates a value larger than the sequence number of the test cell with which synchronization is next established, and the difference is regarded as the number of mis-distributed cells and output to the comparison / difference circuit 15. I do.

Similar to the receiving section 32 in FIG. 3, the above operation is performed only when the control signal output from the synchronization determination circuit 12 indicates synchronization.

The out-of-sync cell counter 14 is provided for counting the number of out-of-sync cells when a test cell is out of sync. When the control signal output from the synchronization determination circuit 12 indicates asynchronous, the out-of-synchronization cell number counter 14 is reset to start the counter. The count up is performed up to the cell immediately before the next time the control signal indicates synchronization, and the value of the counter at that time, that is, the number of cells out of synchronization is output to the comparison / difference circuit 15.

The comparison / difference circuit 15 compares the number of cells out of synchronization with the number of lost cells or the number of mis-distributed cells output by the sequence number comparison circuit 13. The difference is output to the adder circuit 16 and the adder circuit 18 assuming that the cell is caused by the incorrect distribution.

The result obtained by adding the value obtained by the comparison / difference circuit 15, that is, the number of lost cells caused by the continuous loss / misplacement and the number of lost cells obtained by the sequence number comparison circuit 13 by the addition circuit 16 is the loss cell. It is counted by the number counter 17.

The result obtained by adding the value obtained by the comparison / difference circuit 15, that is, the number of mis-distributed cells caused by the continuous loss / mis-distribution and the number of mis-distributed cells obtained by the sequence number comparing circuit 13 by the addition circuit 18. It is counted by the misplaced cell counter 19.

In this way, as shown in FIG. 2, the number of lost cells and the number of mis-distributed cells when test cells are continuously lost and mis-distributed are accurately counted.

[0031]

As is clear from the above embodiments, in the present invention, the number of test cells from the point where synchronization is lost to the next cell where synchronization is obtained is counted, and the value is counted and the number of lost cells or mis-distributed cells is counted. By judging from the number that loss and mis-delivery have occurred continuously, and by incrementing both counters, the number of lost cells and the number of mis-distributed cells when loss and mis-delivery occur continuously can be accurately counted. Thus, an ATM connection test in consideration of a double failure can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a receiving unit of an ATM connection test system according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of a receiving unit of the ATM connection test system of FIG. 1;

FIG. 3 is a block diagram of a conventional ATM connection test method.

FIG. 4 is a diagram for explaining the operation of the ATM connection test system of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Detection circuit 12 Synchronization determination circuit 13 Sequence number comparison circuit 14 Out-of-synchronization cell number counter 15 Comparison / difference circuit 16 Addition circuit 17 Lost cell number counter 18 Addition circuit 19 Miscellaneous cell number counter 31 Transmitter 32 Receiver 41 PN pattern generation Circuit 42 Sequence number counter circuit 43 Test cell insertion circuit 44 Detection circuit 45 Synchronization determination circuit 46 Sequence number comparison circuit 47 Lost cell number counter 48 Misplaced cell number counter

Claims (6)

(57) [Claims] 1. An ATM connection test method for testing a connection between said transmitting unit and said receiving unit in an ATM system having a transmitting unit and a receiving unit, wherein said transmitting unit generates a PN pattern. A circuit, a sequence number counter that outputs a sequence number representing a test cell number, and a test cell insertion circuit that inserts the PN pattern and the sequence number as test cells into transmission data. A detection circuit for detecting the test cell as a detection cell from a signal, and detecting the PN pattern and the sequence number from the detection cell as a detection PN pattern and a detection sequence number; and synchronizing the detection PN pattern for each detection cell. Take
When the detection PN pattern of each detection cell is synchronized, a control signal indicating synchronization is output. When the detection PN pattern of each detection cell is not synchronized, a control signal indicating asynchronous is output. A determination circuit, having an internal reference counter that counts the number of the detection cells as a count value, and upon receiving a control signal indicating the synchronization, comparing the detection sequence number with the count value; Is larger than the count value, the difference between the two is output as the number of lost cells, and the count value of the internal reference counter is set to a value equal to the detection sequence number, and when the detection sequence number is smaller than the count value, The difference between the two is output as the number of mis-distributed cells, and the count value of the internal reference counter is set to the detection sequence number. A sequence number comparison circuit having a value equal to the number of the detection cells while the sequence number comparison circuit continuously outputs the control signal indicating the non-synchronization; The number of out-of-sync cells counting as a number, and comparing the number of mis-arranged cells continuously out of synchronization of the out-of-sync cell number counter with the number of mis-arranged cells output by the sequence number comparison circuit, A comparison / difference circuit that outputs the difference if they do not match, and a first addition that adds the difference output by the comparison / difference circuit to the number of mis-distributed cells output by the sequence number comparison circuit and outputs the result. A second adder circuit for adding the difference output by the comparison / difference circuit to the number of lost cells output by the sequence number comparison circuit and outputting the result. A mis-distributed cell number counter that counts the output value of the first adder circuit as the total number of mis-distributed cells; and a lost cell number counter that counts the output value of the second adder circuit as the total lost cell number. An ATM connection test method characterized by having: 2. The ATM system according to claim 1, wherein the connection between the transmitting unit and the receiving unit of the ATM system is a virtual path (VP) set between the transmitting unit and the receiving unit. The described ATM connection test method. 3. The ATM system according to claim 1, wherein the connection between the transmitting unit and the receiving unit of the ATM system is a virtual channel (VC) set between the transmitting unit and the receiving unit. The described ATM connection test method. 4. In order to test a connection between the transmitting unit and the receiving unit in an ATM system having a transmitting unit and a receiving unit, the transmitting unit generates a PN pattern.
An ATM having an N pattern generating circuit, a sequence number counter for outputting a sequence number representing a test cell number, and a test cell insertion circuit for inserting the PN pattern and the sequence number as test cells into transmission data.
In the connection test system, the receiving unit detects the test cell as a detection cell from a received signal, and detects the PN pattern and the sequence number from the detection cell as a detection PN pattern and a detection sequence number. Synchronize the detection PN pattern for each detection cell,
When the detection PN pattern of each detection cell is synchronized, a control signal indicating synchronization is output. When the detection PN pattern of each detection cell is not synchronized, a control signal indicating asynchronous is output. A determination circuit, having an internal reference counter that counts the number of the detection cells as a count value, and upon receiving a control signal indicating the synchronization, comparing the detection sequence number with the count value; Is larger than the count value, the difference between the two is output as the number of lost cells, and the count value of the internal reference counter is set to a value equal to the detection sequence number, and when the detection sequence number is smaller than the count value, The difference between the two is output as the number of mis-distributed cells, and the count value of the internal reference counter is set to the detection sequence number. A sequence number comparison circuit having a value equal to the number of the detection cells while the sequence number comparison circuit continuously outputs the control signal indicating the non-synchronization; The number of out-of-sync cells counting as a number, and comparing the number of mis-arranged cells continuously out of synchronization of the out-of-sync cell number counter with the number of mis-arranged cells output by the sequence number comparison circuit, A comparison / difference circuit that outputs the difference if they do not match, and a first addition that adds the difference output by the comparison / difference circuit to the number of mis-distributed cells output by the sequence number comparison circuit and outputs the result. A second adder circuit for adding the difference output by the comparison / difference circuit to the number of lost cells output by the sequence number comparison circuit and outputting the result. A mis-distributed cell number counter that counts the output value of the first adder circuit as the total number of mis-distributed cells; and a lost cell number counter that counts the output value of the second adder circuit as the total lost cell number. A receiving unit of an ATM connection test system, comprising: 5. The ATM system according to claim 4, wherein the connection between the transmitting unit and the receiving unit of the ATM system is a virtual path (VP) set between the transmitting unit and the receiving unit. The receiving unit of the ATM connection test method described in the above. 6. The communication system according to claim 4, wherein the connection between the transmission unit and the reception unit of the ATM system is a virtual channel (VC) set between the transmission unit and the reception unit. The receiving unit of the ATM connection test method described in the above.