JP3169309B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film semiconductor device having a thin film transistor and the like used for a display or an image sensor, and more particularly to a method of manufacturing a thin film semiconductor device which can be manufactured by a low temperature process. .

[0002]

2. Description of the Related Art In recent years, in a thin film semiconductor device, a thin film transistor (hereinafter referred to as T
FT) (abbreviated as FT) is formed in a large area.

FIG. 3 shows a cross-sectional view of the TFT portion. In this TFT, a semiconductor layer 12 is formed on an insulating substrate 11, and a gate insulating film 13 is formed so as to cover the surface of the semiconductor layer 12. On the gate insulating film 13,
The gate electrode 13 is overlapped with the center of the semiconductor layer 12.
Is formed, and the portion of the semiconductor layer 12 immediately below the gate electrode 13 serves as a channel portion. One of the semiconductor layer portions on both sides of the channel portion is a source portion, and the other is a drain portion.
An interlayer insulating film 15 and a lead electrode 16 are formed on the gate electrode 14, and the lead electrode 16 is connected to a source portion and a drain of the semiconductor layer 12 through contact holes provided in the gate insulating film 13 and the interlayer insulating film 15. Connected to the unit.

In the above TFT, when a glass substrate is used as the insulating substrate 11, TF is used to prevent thermal distortion and the like.
Preferably, the production of T is performed in a low temperature process at about 600 ° C. or less. For this reason, when manufacturing the gate insulating film 13, plasma CVD (Chemical Vapor) is used.
Deposition method, remote plasma CVD
Law, AP (Atomospheric Pressu)
re) CVD method, LP (Low Pressure) C
An insulating film such as a SiO ₂ film is formed by a deposition method capable of forming a film at a low temperature such as a VD method or a sputtering method. But,
Since the SiO ₂ films obtained by these methods are not dense, problems such as a decrease in the reliability of the TFT have occurred. To prevent this, for example, Japanese Patent Publication No. 5-46105
Japanese Patent Application Laid-Open Publication No. H11-163873 discloses a method of annealing an insulating film at a temperature of about 600 ° C., but this method cannot sufficiently densify the film.

When a substrate other than a glass substrate such as a quartz substrate or a silicon wafer is used as the insulating substrate 11,
A method of densifying the SiO ₂ film by high-temperature annealing at about 900 ° C. or lamp annealing in an N ₂ atmosphere is considered. However, in any case, about 600 ° C. is insufficient, and a high quality gate insulating film cannot be obtained unless high-temperature heat treatment at 600 ° C. or higher is performed.

[0006]

As described above [0006], not dense and high quality ones obtained when the gate insulating film is prepared at a low temperature of 600 ° C. or less, and those containing a large number of traps in the SiO ₂ film Therefore, the TFT characteristics are adversely affected. Since these traps cause hot electron injection, they also pose a problem in terms of device reliability. In addition, since the gate insulating film is formed at a low temperature, the interface state density is increased, and a favorable interface is not easily formed.

On the other hand, a gate insulating film formed at a relatively high temperature can be of high quality, but there is a strong demand for TFT manufacturing by a low-temperature process from the viewpoint of thermal distortion and the like.

The present invention has been made to solve such problems of the prior art, and a thin film semiconductor device in which the vicinity of an interface between a channel semiconductor layer and a gate insulating film is dense and which has excellent reliability in element characteristics. It is an object of the present invention to provide a method for producing the same.

[0009]

According to the present invention, there is provided a method of manufacturing a thin film semiconductor device having a structure in which a channel semiconductor layer and a gate insulating film are in contact with each other.
Forming sequentially the channel semiconductor layer and the gate insulating film;
Then, the channel semiconductor layer and the gate insulating film
Energy density such that the interface is 800 ° C to 1000 ° C
Laser annealing, and
After Neil, by heat treatment at a temperature of 550 ° C to 650 ° C
Annealing is performed, thereby achieving the above object.

[0010]

[0011]

[0012]

According to the present invention, laser annealing is performed after forming a gate insulating film on a semiconductor layer. By this laser annealing, densification of the gate insulating film near the interface between the semiconductor layer and the gate insulating film and reconstruction of the network of interface atoms are performed. For this reason, the interface state density decreases and a good interface is formed. Accordingly, a TFT having a high mobility and a low threshold voltage Vth and a low S coefficient (a value indicating a gate voltage necessary for increasing the current drawn from the drain portion of the transistor by one digit)
Properties can be obtained.

Further, since the gate insulating film can be made dense and high quality, there are few traps near the interface, and the gate insulating film can be made strong against hot electron injection. Therefore, a TFT having excellent reliability can be obtained. Since the gate insulating film can be formed at a low temperature, a TFT can be manufactured by a low-temperature process, and there is no problem such as thermal distortion.

Further, if annealing is performed by a conventional heat treatment after the laser annealing, the densification and the reconfiguration near the interface between the semiconductor layer and the gate insulating film can be performed more effectively. Becomes In addition, the region where the densification of the gate insulating film is performed can be made wider from the vicinity of the interface.

The effect of the laser annealing is too small when the energy density is too low, and a problem such as damage to the gate insulating film occurs when the energy density is too high. Therefore, the interface between the semiconductor layer and the gate insulating film is 800 ° C. to 1000 ° C. It is desirable to carry out at such an energy density. In particular, the interface is about 1000 ° C
It is optimal to carry out at an energy density such that

In the case of using a glass substrate, the annealing by the heat treatment is performed at about 600 ° C., specifically, 550 ° C.
It is good to carry out at 650 ° C. Annealing is performed in such a temperature range because if the temperature is too low, the effect is small, and if the temperature is too high, problems such as thermal distortion occur in the substrate.

The reason for performing the annealing by heat treatment after the laser annealing is that the laser annealing can locally raise the temperature to higher than 600 ° C. without significantly affecting the surroundings, and can cut off atoms such as hydrogen near the interface. This is because it becomes possible, and atoms such as hydrogen can be dispersed from the vicinity of the interface by annealing by the subsequent heat treatment. Therefore, the quality near the interface is improved.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1E is a sectional view showing a TFT to which the present invention is applied. In this TFT, a semiconductor layer 2 is formed on an insulating substrate 1, and a gate insulating film 3 is formed so as to cover the semiconductor layer 2. A gate electrode 3 is formed on the gate insulating film 3 so as to overlap a central portion of the semiconductor layer 2, and a portion of the semiconductor layer 2 immediately below the gate electrode 3 serves as a channel portion. One of the semiconductor layer portions on both sides of the channel portion is a source portion, and the other is a drain portion. An interlayer insulating film 5 and a lead electrode 6 are formed on the gate electrode 4, and the lead electrode 6 is connected to a source portion and a drain of the semiconductor layer 2 through contact holes provided in the gate insulating film 3 and the interlayer insulating film 5. Connected to the unit.

This TFT can be manufactured as follows.

First, as shown in FIG. 1A, a semiconductor layer 2 is formed on an insulating substrate 1. In this embodiment, about 6
An amorphous Si film was formed on a glass substrate 1 having a high strain point temperature capable of withstanding a heat treatment at 00 ° C. at a substrate temperature of about 450 ° C. by an LPCVD method using Si ₂ H ₆ gas. This amorphous Si film is placed in an N ₂ atmosphere at 600 ° C.
Annealing for about 2 hours in solid phase growth
The ly-Si film was recrystallized by excimer laser annealing. The obtained poly-Si
The film was islanded into a desired shape by etching, and the semiconductor layer 2 was formed.

Next, as shown in FIG. 1B, a gate insulating film 3 is formed so as to cover the semiconductor layer 2. In this embodiment, an S layer having a thickness of about 200 nm is formed by a plasma CVD method.
An iO ₂ film was formed to form a gate insulating film 3.

Subsequently, as shown in FIG. 1C, laser annealing is performed on the gate insulating film 3. In this embodiment, an excimer laser is used, and the laser power is set so that the interface between the semiconductor layer 2 made of poly-Si and the gate insulating film 3 made of SiO ₂ is about 800 to 1000 ° C.
The R density was set to 200 to 300 mJ / cm ² . Subsequently, annealing was performed by heat treatment at 600 ° C. for about 12 hours to densify the gate insulating film 3.

Next, as shown in FIG. 1D, a gate electrode 4 is formed on the gate insulating film 3. In this example,
A poly-Si film having a thickness of about 250 nm was formed and patterned into a desired shape to form the gate electrode 4.

Then, using the gate electrode 4 as a mask, an impurity element (N
A source portion (not shown) and a drain portion (not shown) are formed by doping in a self-alignment manner phosphorus (phosphorus for ch) and boron (Pch for Pch). In this embodiment, a source portion and a drain portion were formed by ion-implanting an impurity element at about 1 × 10 ¹⁵ ions / cm ² and about 40 ke to activate the impurities. At this time, an impurity element was simultaneously implanted into the gate electrode 4 to lower the resistance.

Next, an interlayer insulating film 5 is formed so as to cover the gate electrode 4. In this embodiment, an interlayer insulating film 5 was formed by forming a SiO ₂ film having a thickness of about 500 nm.

Finally, as shown in FIG. 1E, a contact hole is formed in the gate insulating film 3 and the interlayer insulating film 5, and a lead electrode 6 is formed on the interlayer insulating film 5. In this embodiment, the extraction electrode 6 was formed using aluminum.

Table 1 shows the TFTs obtained as described above.
(Example) is shown. As a comparative example, a TFT manufactured in the same manner as in the example except that laser annealing was not performed (however, annealing by heat treatment was performed).
Are also shown.

[0029]

[Table 1]

As can be seen from Table 1, the TF of the embodiment
T has higher mobility and lower Vth and S coefficient than the TFT of the comparative example. This indicates that the interface between the semiconductor layer and the gate insulating film was improved by laser annealing the gate insulating film.

FIG. 2 shows that the gate applied electric field strength was 8 MW / cm and the temperature was 15
The relationship (TDDB characteristic) between the stress time (horizontal axis) and the cumulative failure rate (vertical axis) when performed in the air at 0 ° C. is shown. In the drawings, the mark ○ indicates the case of the example, and the mark △ indicates the case of the comparative example.

As can be understood from FIG. 2, the TDDB characteristic of the gate insulating film in the TFT of the embodiment subjected to laser annealing is superior to the TDDB characteristic of the TFT of the comparative example without laser annealing. , And a highly reliable insulating film in which electron injection hardly occurs. This is because TF which is excellent in TFT characteristics and device reliability by laser annealing
This shows that T is obtained.

In the above embodiment, the case where laser annealing and annealing by heat treatment are performed is described. However, the present invention is not limited to this, and only laser annealing may be performed alone.

In the above embodiment, an excimer laser is used for laser annealing, but it is a matter of course that another laser can be used.

In the above embodiment, the TFT has a top gate configuration in which a semiconductor layer, a gate insulating film, and a gate electrode are stacked in this order. However, a bottom gate configuration in which the stacking order is reversed may be adopted.

Although the SiO ₂ film is used as the gate insulating film, another insulating material such as SiN may be used. Although polysilicon is used as the channel semiconductor layer, other semiconductor materials such as crystalline Si may be used.
In any case, the power density of the laser annealing is set at 800 to 1000 ° C. at the interface between the semiconductor layer and the gate insulating film.
It is desirable to set so that

[0037]

As is apparent from the above description, according to the present invention, the density of the gate insulating film near the interface between the semiconductor layer and the gate insulating film can be improved by performing laser annealing after forming the gate insulating film. And reconstruct the network of interfacial atoms. Therefore, it is possible to reduce the interface state density and to form a good interface,
TFT characteristics such as mobility, Vth, and S coefficient can be improved. In addition, since the gate insulating film can be made dense and high quality, traps near the interface can be reduced, and the resistance to hot electron injection can be increased. Therefore, a TFT having excellent reliability can be obtained. Furthermore, these effects can be further improved by performing annealing by heat treatment after performing laser annealing.

Further, according to the present invention, the gate insulating film can be formed at a low temperature.
T can be made. Therefore, a problem such as thermal distortion does not occur, and a TFT can be manufactured over a large area of a thin film semiconductor device using a glass substrate or the like.

[Brief description of the drawings]

FIGS. 1A to 1E are cross-sectional views illustrating a manufacturing process of a TFT to which the present invention is applied.

FIG. 2 shows TDDB in TFTs of an example and a comparative example.
It is a graph which shows a characteristic.

FIG. 3 is a cross-sectional view showing a conventional TFT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Semiconductor layer 3 Gate insulating film 4 Gate electrode 5 Interlayer insulating film 6 Leader electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21/268 H01L 21/324 H01L 21/336

Claims (1)

(57) [Claims] 1. A method for manufacturing a thin film semiconductor device having a structure in which a channel semiconductor layer and a gate insulating film are in contact with each other, comprising: sequentially forming the channel semiconductor layer and the gate insulating film;
Then, the channel semiconductor layer and the gate insulating film
Energy density such that the interface is 800 ° C to 1000 ° C
Laser annealing, and
After Neil, by heat treatment at a temperature of 550 ° C to 650 ° C
A method for manufacturing a thin film semiconductor device, wherein annealing is performed .