JP3160972B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which an antireflection film is formed on the surface of an aluminum-based metal wiring.

[0002]

2. Description of the Related Art In recent years, as VLSIs have become finer, the width of wirings has tended to become smaller and smaller. In addition, problems that have not been encountered in microfabrication are becoming apparent. For example,
As the pattern size becomes smaller, the reflection of light due to the aluminum-based metal wiring becomes a problem in improving the accuracy in the photolithography process. That is, light is reflected by the aluminum-based metal wiring at the time of exposure, so that the side wall of the pattern is roughened, or the pattern is narrower than the expected width due to the reflection of light at the step portion of the substrate. Has occurred.

In order to solve these problems, a method of forming an antireflection film for preventing reflection of light at the time of exposure on the surface of an aluminum-based metal wiring is being adopted. Examples of the material of the antireflection film include amorphous silicon and titanium oxynitride (hereinafter also referred to as TiON).
Is becoming mainstream.

[0004]

Although an etching technique for an aluminum-based metal wiring material when TiON is used as a material for an anti-reflection film is being developed, the generation of an aluminum crown, which will be described in detail below, or an interlayer insulating film will be described. The problem of poor etching has become apparent.

The problem of the occurrence of an aluminum crown in a conventional method for manufacturing a semiconductor device will be described with reference to FIG. Forming an insulating layer 102 made of silicon dioxide (hereinafter abbreviated as SiO ₂ ) on a silicon substrate 100;
An aluminum-based metal wiring 104 is formed thereon. The metal wiring 104 has a barrier metal structure using titanium oxynitride as a barrier metal, and includes a titanium (hereinafter abbreviated as Ti) layer, a TiON layer, and aluminum containing Si (hereinafter abbreviated as Al-Si). Consists of layers.

On the surface of the metal wiring 104, an antireflection film 106 made of, for example, 25 μm thick TiON is formed. The metal wiring 104 and the anti-reflection film 106 can be formed by patterning a metal wiring layer having a barrier metal structure and an anti-reflection film layer by a photolithography method, and then etching.

Next, the insulating layer 102 and the antireflection film 106
On top of this, an interlayer insulating film 108 made of, for example, PSG is deposited. Then, a resist 110 having an opening 112 formed thereon is formed (see FIG. 6A). The opening 112 of the resist 110 is provided for forming a connection hole for making an electrical connection to the metal wiring 104 in a later step. The opening 112 can be formed by a photolithography method.

Next, using a reactive ion etching (hereinafter abbreviated as RIE) apparatus, for example,
₂ / CHF ₃ = 8/75 SCCM, 50 mtorr, 1350W
Under the above conditions, the interlayer insulating film 108 is etched to form the connection hole 114, and the antireflection film 106 is further etched (see FIG. 6B).

Under these etching conditions, the etching rate of the interlayer insulating film 108 made of PSG is 50 nm.
/ Min, whereas the etching rate of the antireflection film 106 made of TiON is about 10 nm / min. Therefore, an excessive over-etching state occurs because the anti-reflection film is etched. Since the etching rate in the wafer, the thickness of the interlayer insulating film, or the thickness of the antireflection film are not uniform, a certain degree of over-etching is required. However, when the already etched portion of the antireflection film is over-etched, the underlying Al-Si layer is sputtered,
Al-Si is formed on the side wall 114A of the connection hole 114 or the resist 1
This causes a problem of adhesion to the side wall of the opening 112 of the ten holes. The Al-Si attached to the side wall of the connection hole or the side wall of the opening of the resist is called an aluminum crown.

When an aluminum crown is generated, when the connection hole 114 is buried with a wiring material to electrically connect the metal wiring 104 and an upper wiring layer (not shown in FIG. 6), the wiring material is connected. It also deposits on the side walls 114A of the holes 114, resulting in filling the connection holes from the side walls 114A. Therefore, a failure occurs in the electrical connection between the metal wiring 104 and the upper wiring layer.

In order to prevent or reduce the generation of the aluminum crown, it is preferable to perform the etching with an anode coupling type etching apparatus having a low ion incident energy. However, since the ion incident energy is low, the etching rate of the antireflection film 106 made of TiON is low, and it takes a long time before the antireflection film is etched off. As a result, an undercut occurs in the interlayer insulating film 108 or the side wall 11
A problem of poor etching of the interlayer insulating film occurs that a concave portion 114B is generated in 4A (see FIG. 6C).

Accordingly, an object of the present invention is to prevent the occurrence of the above-mentioned aluminum crown or the poor etching of the interlayer insulating film when performing an electrical connection process to an aluminum-based metal wiring having a titanium-based antireflection film on the surface. Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can improve the electrical connection with an upper wiring layer.

[0013]

The object of the present invention is to provide (a) a step of forming an interlayer insulating film on an aluminum-based metal wiring having a titanium-based antireflection film on its surface, and (b) etching mainly using a radical mode. Forming a connection hole in the interlayer insulating film to expose the titanium-based anti-reflection film; and (c) a titanium-based anti-reflection film exposed at the bottom of the connection hole by etching mainly using ion mode. And exposing the aluminum-based metal wiring to achieve a method of manufacturing a semiconductor device according to the present invention.

As the titanium antireflection film, TiON can be mentioned.

As the aluminum-based metal wiring, an aluminum alloy containing Si, an aluminum alloy containing copper, or a barrier metal structure having a laminated structure of a Ti, TiON film or the like (for example, on the side near the silicon substrate) From Ti / TiON / Al-Si / TiON).

The radical mode etching can be performed by an anode coupling type plasma etching apparatus.

The ion mode etching can be performed by a cathode coupling type reactive ion etching apparatus or a magnetron reactive ion etching apparatus using magnetron discharge.

Preferably, the radical mode etching is performed by an anode coupling type etching apparatus, and the ion mode etching is performed by a cathode coupling type reactive ion etching apparatus.

A plurality of the aluminum-based metal wires may be formed on a step formed on a substrate.

The high frequency used in the anode coupling type etching apparatus is preferably 380 kHz to 13.56 MHz.

The gas system used in the cathode coupling type etching apparatus is preferably a mixed gas system of a gas containing fluorine, carbon and hydrogen, and a gas containing SF ₆ .

[0022]

In the method of manufacturing a semiconductor device according to the present invention, the opening of the connection hole to the interlayer insulating film is performed by a radical mode plasma etching apparatus of, for example, an anode coupling type. Play a role. The removal of the antireflection film is performed by, for example, RIE in the ion mode. by this,
An aluminum crown is prevented from being generated, and a connection hole having a good shape can be formed.

The ion incident energy of the etching apparatus depends on the conditions, but is generally higher in the cathode coupling system than in the anode coupling system. Preferred embodiments of the present invention take advantage of these features of these two types of etching equipment. That is, the opening of the connection hole to the interlayer insulating film is performed by an etching apparatus of an anode coupling type capable of obtaining a radical mode with a low ion incident energy, and the removal of the antireflection film is performed by a high ion incident energy with a high ion incident energy. Is performed by a cathode coupling type etching apparatus capable of obtaining the following.

[0024]

FIG. 4A shows an outline of a typical anode-coupling type plasma etching apparatus 50 suitable for opening a connection hole to an interlayer insulating film. The parallel plate type etching apparatus 50 has a vacuum chamber 52. In the vacuum chamber 52, a lower electrode 54 on which a wafer 64 is placed and an upper electrode 56 for applying a high frequency are provided. High frequency is supplied from a high frequency oscillator 58 to the upper electrode 56. The gas used for etching is supplied into the vacuum chamber 52 from the gas introduction unit 60, and is exhausted from the lower part 62 of the vacuum chamber 52 by an exhaust device (not shown). Since a high frequency is applied to the upper electrode 56, the ion incident energy incident on the wafer is lower than that of a cathode coupling type RIE apparatus described later.

FIG. 4B shows an outline of a typical RIE apparatus 70 of the cathode coupling type suitable for etching of the antireflection film. Such a parallel plate type RIE device 70
Has a vacuum chamber 72. In the vacuum chamber 72, a lower electrode 74 on which a wafer 84 is placed and an upper electrode 76 as a counter electrode are provided. The high frequency is supplied from a high frequency oscillator 78 to the lower electrode 74. The gas used for etching is supplied into the vacuum chamber 72 from the gas introduction unit 80, and is exhausted from the lower part 82 of the vacuum chamber 72 by an exhaust device (not shown). Wafer 8
Since 4 is placed on the lower electrode 74 to which a high frequency is applied, the ion incident energy incident on the wafer is higher than that of the above-described anode coupling type etching apparatus.

A preferred embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below.

(Embodiment 1) Si on a silicon substrate 10
An insulating layer 12 made of O ₂ is formed, and an aluminum-based metal wiring 14 is formed thereon. This metal wiring 14
It has a barrier metal structure using iON as a barrier metal,
Ti layer (14A), TiON layer (14B), and Al-
It consists of a Si layer (14C).

On the surface of the metal wiring 14, for example,
An antireflection film 16 made of 5 μm TiON is formed.
The metal wiring 14 and the anti-reflection film 16 are formed by depositing a metal wiring layer having a barrier metal structure and an anti-reflection film layer on the insulating layer 12, applying a resist, patterning the resist by a photolithography method, and then chlorine. These layers can be formed by etching these layers with a system gas and removing the resist.

Next, a thick silicon nitride film 18 is formed on the insulating layer 12 and the antireflection film 16 and a resist is applied over the entire surface. Then, the silicon nitride film 18 and the resist are etched at the same etching rate. Smoothing is performed by etching, so-called resist etch back. afterwards,
For example, PSG 20 is deposited. In this embodiment,
The interlayer insulating film 22 includes the silicon nitride film 18 and the PSG 20. Then, a resist 24 having an opening 26 is formed thereon (see FIG. 1A). The opening 26 of the resist 24 is provided for forming a connection hole for making an electrical connection to the metal wiring 14 in a later step. The opening 26 can be formed by a photolithography method.

Next, using a batch type anode coupling type plasma etching apparatus, etching mainly in the radical mode is performed under the following conditions. CHF ₃ = 20 SCCM C ₂ F ₆ = 80 SCCM Ar = 20 SCCM Pressure = 70 Pa (526 mtorr) RF frequency = 13.56 MHz RF power = 2.0 kW

Under the above etching conditions, the etching rate of the silicon nitride film 18 is 120 nm / min, and the etching rate of the PSG 20 is 98 nm / min. The etching rate of the anti-reflection film 16 made of TiON is as very small as 10 to 20 nm / min.

When etching is performed under the above etching conditions until the antireflection film 16 is etched as in the prior art, the etching time becomes longer, and the side wall 28A of the connection hole 28 is shown in FIG. Such a concave portion 28B is formed, and an etching failure occurs. The concave portion causes poor coverage when the connection hole 28 is buried with a wiring material for electrical connection with an upper wiring layer in a later step. The cause of the formation of the concave portion is excessive overetching in the etching by the anode coupling method.

In the method of manufacturing a semiconductor device according to the present invention, the connection hole 28 is formed in the interlayer insulating film 22 and the interlayer insulating film 22 is etched by an anode coupling type etching apparatus with the antireflection film 16 exposed. Is stopped (see FIG. 1B). In this state, the connection hole 28
No recess is formed on the side wall 28A. The antireflection film 16 plays a role as an etching stopper.

Next, reactive ion etching mainly in ion mode is performed by a cathode coupling type RIE apparatus in which the ion incident energy is higher than that of the anode coupling type etching apparatus. The etching conditions were as follows. C ₂ F ₆ = 30 SCCM Ar = 20 SCCM Pressure = 5 Pa (38 mtorr) RF frequency = 13.56 MHz RF power = 800 W

Under the above etching conditions, TiO
The etching rate of the antireflection film 16 made of N is 11 n
m / min. Then, by performing the etching for 3 minutes or more, the antireflection film 16 having a thickness of 25 nm was able to be removed from the underlying Al—Si layer (14C) (see FIG. 1C). At this time, no deterioration of the shape of the connection hole 28 was observed. As described above, by using the cathode coupling type RIE apparatus, the etching is performed in the ion mode, and the connection hole can be processed without deteriorating the shape of the connection hole.

Example 2 As shown in FIG. 2A, a step portion 30 was formed on a silicon substrate 10 on which elements were formed. In addition, a wiring not shown in FIG. 2A is provided in the step portion 30. Step 3
An insulating layer (not shown) is formed on the surface of the “0”. On the insulating layer, metal wirings 14a and 14b are formed in the same manner as in Example 1, and metal wirings 14a and 14b are formed.
The anti-reflection films 16a and 16b are formed on the substrate.

Thereafter, a thick silicon nitride film 18 is formed on the insulating layer and the antireflection films 16a and 16b in the same manner as in Example 1, and smoothing is performed by resist etch back. Next, for example, PSG 20 is deposited on the silicon nitride film 18. Also in this embodiment, the interlayer insulating film 22 includes the silicon nitride film 18 and the PSG 20. Then, a resist 24 having openings 26a and 26b is formed on the interlayer insulating film 22 in the same manner as in Example-1 (see FIG. 2A).

Next, etching was performed mainly in the radical mode under the following conditions using a single-wafer anode coupling type plasma etching apparatus. CF ₄ = 70 SCCM CHF ₃ = 30 SCCM Ar = 450 SCCM Pressure = 2.3 torr RF frequency = 380 kHz RF power = 600 W

Under the above etching conditions, the etching rate of the silicon nitride film 18 was 500 nm / min, and the etching rate of the PSG 20 was 800 nm / min. The etching rate of the antireflection films 16a and 16b made of TiON was very small, 5 nm / min.
Therefore, the thick interlayer insulating film 22 is etched,
Although the connection holes 28a and 28b can be formed, the thin antireflection films 16a and 16b are exposed without being removed (see FIG. 2B).

When the etching is further performed as in the prior art, the antireflection film 16a at the bottom of the connection hole 28a located at the thin portion of the interlayer insulating film is replaced with the bottom of the connection hole 28b located at the thick portion of the interlayer insulating film. Is etched prior to the antireflection film 16b. As a result, the anti-reflection film 16
The over-etching state where the Al-Si layer a is exposed causes an aluminum crown. Alternatively,
As shown in FIG. 3B, a recess is formed on the side wall of the connection hole 28a.

In the present invention, next, reactive ion etching mainly in the ion mode is performed by a cathode coupling type RIE apparatus. The etching conditions were as follows. Incidentally, it was varied the flow rate of SF ₆ and CHF ₃ within the range described below. SF ₆ = 3 to 20 SCCM CHF ₃ = 20 to 0 SCCM He = 50 SCCM Pressure = 53.5 Pa (400 mtorr) RF frequency = 13.56 MHz RF power = 300 W

FIG. 5 shows the relationship between the etching rates of the antireflection film 16, the silicon nitride film 18, the interlayer insulating film 22, and the resist, and the flow rates of SF ₆ and CHF ₃ .
As is apparent from FIG. 5, when the flow rate of SF ₆ is increased, the etching rate of the antireflection film made of TiON tends to increase. Although not shown in FIG. 5, when the flow rate of SF ₆ was 0 SCCM, that is, when a mixed gas system of only CHF ₃ and He was used, the etching rate of the antireflection film was very small at 10 nm / min. . Therefore, based on the results shown in FIG. 5, the antireflection film 16 was etched under the following conditions. SF ₆ = 15 SCCM CHF ₃ = 10 SCCM He = 40 SCCM Pressure = 46.7 Pa (350 mtorr) RF frequency = 13.56 MHz RF power = 300 W

FIG. 2 in which the antireflection films 16a and 16b are exposed.
By starting the etching under the above conditions from the state shown in FIG. 3B, the antireflection films 16a and 16b could be removed without deteriorating the shapes of the connection holes 28a and 28b. Further, the etching of the antireflection film 16a at the bottom of the connection hole 28a located at the thin portion of the interlayer insulating film and the etching of the antireflection film 16b at the bottom of the connection hole 28b located at the thick portion of the interlayer insulation film are performed. Excessive over-etching is not required to proceed simultaneously. As a result, generation of an aluminum crown can be almost prevented.

Although the method of manufacturing a semiconductor device according to the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments.

As the insulating layer 12, for example, PSG, BSG, BPSG, AsSG, or a silicon nitride film can be used other than SiO ₂ . As the barrier metal, for example, TiN, TiW, W, Mo, or a metal silicide layer under an aluminum layer can be used.
As the interlayer insulating film, other than the combination of the silicon nitride film / PSG, a silicon nitride film / BPSG, a silicon nitride film / BSG, a PSG / silicon nitride film / PSG, or the like can be used.

In the present invention, the same etching effect is obtained regardless of whether the high frequency used in the anode coupling type etching apparatus is 13.56 MHz or 380 kHz. Therefore, the frequency used is not particularly limited.

The etching of TiON in the cathode-coupling type etching apparatus can be performed in a gas system containing fluorine. In particular, by adding SF ₆ , the etching rate of TiON can be significantly increased. etching of TiON gas system containing SF ₆ is very effective.

[0048]

According to the conventional method of manufacturing a semiconductor device, a method for forming a connection hole in an interlayer insulating film formed on an aluminum-based metal wiring and removing the anti-reflection film is required.
Only one etching process is performed. As a result, problems such as generation of an aluminum crown or poor etching of an interlayer insulating film occur. On the other hand, in the method of manufacturing a semiconductor device according to the present invention, a connection hole is formed in the interlayer insulating film by radical mode etching, and then the antireflection film is removed by ion mode etching. As a result, excessive overetching after the antireflection film is removed can be prevented, and problems such as deterioration of the shape of the connection hole or generation of an aluminum crown can be effectively solved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device, showing a part of a process of an embodiment according to a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor device, showing a part of the steps of another embodiment according to the method of manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional view of a semiconductor device showing a problem due to a conventional method of manufacturing a semiconductor device.

FIG. 4 is a diagram showing an outline of an etching apparatus suitable for carrying out the method of the present invention.

FIG. 5 is a diagram showing a relationship between a flow rate ratio of a gas used for etching and an etching rate of various materials.

FIG. 6 is a schematic cross-sectional view of a semiconductor device for illustrating a part of a process of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 10, 100 Silicon substrate 12, 102 Insulating layer 14, 104 Metal wiring 16, 106 Antireflection film 18 Silicon nitride film 20 PSG film 22, 108 Interlayer insulating film 24, 110 Resist 26, 112 Opening 28, 114 Connection hole

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-262122 (JP, A) JP-A-4-266022 (JP, A) JP-A-63-196039 (JP, A) JP-A-4- 102331 (JP, A) Japanese Utility Model Showa 63-38322 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3065 H01L 21/3205

Claims (3)

(57) [Claims] (A) forming an interlayer insulating film on an aluminum-based metal wiring having a titanium-based anti-reflection film on its surface; and (b) opening a connection hole in the interlayer insulating film by radical mode etching. And (c) removing the titanium-based anti-reflection film exposed at the bottom of the connection hole by ion-mode etching and exposing the aluminum-based metal wiring. A method for manufacturing a semiconductor device, comprising: 2. The radical mode etching is performed by an anode coupling type etching apparatus, and the ion mode etching is performed by a cathode coupling type reactive ion etching apparatus. Item 2. A method for manufacturing a semiconductor device according to item 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said aluminum-based metal wiring is formed on a step formed on a substrate.