JP3160383B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as a dynamic RAM which requires a high-speed read operation, and more particularly to a measure for reducing access time.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional semiconductor integrated circuit device. In FIG. 5, reference numeral 2 denotes an address transition detection circuit that detects a transition of the address signal 1 and generates an address transition detection signal 3. Reference numeral 4 denotes an internal clock that generates an output activation signal 5 based on the address transition detection signal 3. A generation circuit 6 is a decoder, 7 is a memory cell in which data is written, 9 is a sense amplifier for amplifying data 8 from the memory cell 7, and 10 is an output activation signal of the internal clock generation circuit 4. A main amplifier 11 driven by 5 and amplifying data from the sense amplifier 9;
Driven by the output activation signal 5 of the internal clock generation circuit 4, the data from the main amplifier 10
An output buffer circuit for outputting to the output terminal 13 as 12.

[0003] A read operation in the semiconductor integrated circuit device will be described below.

First, an externally input address signal 1
Transitions, the address transition detection circuit 2 detects a transition of the address signal and generates an address transition detection signal 3.
At the same time, the address signal 1 selects data 8 to be read from the memory cell 7 via the decoder 6 and the sense amplifier 9. The selected data 8 is amplified by the sense amplifier 9 and transferred to the main amplifier 10.

On the other hand, the address transition detection signal 3 operates the internal clock generating circuit 4 to generate the output activating signal 5 and sequentially operate the main amplifier 10 and the output buffer circuit 11. The data 8 transferred to the main amplifier 10 is sequentially transferred by the sequential operation of the main amplifier 10 and the output buffer circuit 11, and is finally output as output data 12 to the output terminal 13.

Next, a conventional example of the output buffer circuit 11 is shown in FIG. The output buffer circuit 11 includes an output transistor drive circuit 14, a high output transistor 15 for outputting data "H", and a low output transistor 16 for outputting data "L". The output transistor driving circuit 14 operates according to the output activating signal 5 generated by the internal clock generating circuit 4, and drives the high output transistor 15 when outputting data “H” based on data from the main amplifier 10. When outputting data "L", the low output transistor 16 is driven.

[0007]

However, in the above semiconductor integrated circuit device, both output transistors 15 and 16 have the same time to start driving.
Even if the driving capabilities are the same, the data output waveforms are different due to restrictions on the layout arrangement of each of the output transistors 15, 16 and the output terminal 13, resulting in a difference in the access time.

More specifically, the two output transistors 15, 16
Is disposed near the power supply terminal 19, the output of the data "L" is delayed because the parasitic impedance 17 of the power supply wiring is low and the parasitic impedance 18 of the ground wiring is high. Conversely, both output transistors 15 and 16 are connected to ground terminal 20
, The parasitic impedance 18 of the ground wiring is low and the parasitic impedance 17 of the power supply wiring is high, so that the output of data “H” is delayed.

Therefore, when the above-described conventional semiconductor integrated circuit device is applied to the case where a plurality of output terminals 13 are provided, the access time is determined by the access time of the output terminal 13 which is the slowest. That is, in a semiconductor integrated circuit device in which a large number of simultaneously operating output transistors exist on one chip, there is a problem that the variation in the access time at each output terminal 13 is large, and as a result, the entire access time is delayed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit device in which the variation in access time between output terminals is suppressed and the access time is short.

[0011]

In order to achieve the above object, the measures taken by the invention according to claim 1 first include a power supply.
A first output connected to the power supply line at a position relatively close to the terminal
Power supply line at a position relatively far from the buffer circuit and power supply terminal
And a second output buffer circuit connected to the second output buffer circuit.
Then, of the first and second output buffer circuits,
Before output of normal data, only output buffer circuit 2
A high charge transistor that charges the output node to H level
It is configured to include .

[0012] Further , means taken by the invention according to claim 2
Is connected to the ground wire at a position relatively close to the ground terminal.
The first output buffer circuit and the ground terminal.
A second output buffer circuit connected to the ground line
It has. And the first and second output buffers
Only the second output buffer circuit of the
Before output is output, the output node is charged to L level.
It is configured to include an electronic transistor.

[0013] The invention according to claim 3 has taken measures.
In the invention according to claim 1 or claim 2,
Transition of the address signal is detected when
An address transition detection circuit that outputs a transition detection signal
Address transition detection from the address transition detection circuit
In response to the signal, the charging transistor is driven.
ing.

[0014]

According to the present invention, when reading data, the address transition detecting circuit detects a transition of the address signal and outputs an address transition detecting signal. The output buffer circuit receives the address transition detection signal of the address transition detection circuit.

And a power supply terminal of the output buffer circuit.
The second output buffer circuit relatively far from the
A second output with a radiator or relatively far from the ground terminal.
The power buffer circuit has a low charge transistor
Thus, the output node is charged to the H level or the L level before outputting the normal data, and then the normal data is output. As a result, the normal data is output with the output node shifted to the high level or the low level, so that the access time as a whole is shortened.

[0016]

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the same components as those of the related art are denoted by the same reference numerals, and the overall block configuration of the semiconductor integrated circuit device is the same as that of FIG.

FIG. 1 shows four output buffer circuits 11A1, 11A.
It is a layout conceptual diagram in case A2, 11B1, and 11B2 are provided on one chip. In FIG. 1, a first ground-side output buffer circuit 11A1 and a second ground-side output buffer circuit 11A2 are arranged near a ground terminal 20, and a first power-supply-side output buffer circuit 11B1 and a second Power supply output buffer circuit 11
B2 is disposed near the power supply terminal 19, and the output buffer circuits 11A1, 11A2, 11B1, and 11B2 are connected to the parasitic impedance 17 of the power supply wiring and the parasitic impedance of the ground wiring, respectively.
The power supply terminal 19 and the grounding terminal 20 are connected via 18 and the output terminals 13A1, 13A2, 13B1, and 13B2.

FIG. 2 shows a ground-side output buffer circuit 11.
FIG. 3 is a circuit configuration diagram of A1 and 11A2, and FIG. 3 is a circuit configuration diagram of the power supply side output buffer circuits 11B1 and 11B2. Each of the output buffer circuits 11A1, 11A2, 11B1, 11B2
An output transistor drive circuit 14, a high output transistor 15 for outputting data "H", and a low output transistor 16 for outputting data "L" are provided. The power supply terminal 19 and the ground terminal 20 are connected via the parasitic impedance 18 of the ground wiring. Then, the output transistor drive circuit 14 is operated by the output activation signal 5 generated by the internal clock generation circuit 4, and when outputting data “H” based on data from the main amplifier 10, the high output transistor 15 is driven. When outputting data "L", the low output transistor 16 is driven.

On the other hand, as a feature of the present invention, in the ground side output buffer circuits 11A1 and 11A2 shown in FIG. 2, a high charge transistor 21 is provided between an output node and a power supply node. When the address transition detection signal 3 generated by the address transition detection circuit 2 activates the internal clock generation circuit 4, the high charge transistor
21 is driven, the output node is once charged to a high level, then brought into a high impedance state, and then the high output transistor 15 or the low output transistor 16 is driven to output normal data.

As a feature of the present invention, in the power supply side output buffer circuits 11B1 and 11B2 shown in FIG. 3, a low charge transistor 22 is provided between an output node and a ground node. The address transition detection signal 3 generated by the address transition detection circuit 2 activates the internal clock generation circuit 4 and simultaneously operates the low charge transistor.
After driving the output node 22 to once charge the output node to a low level, the output node is set to a high impedance state, and then the high output transistor 15 or the low output transistor 16 is driven to output normal data.

Next, the output buffer circuits 11A1, 11A
The data output operation of 2, 11B1, 11B2 will be described with reference to FIG.

First, when the address signal 1 transitions, the address transition is detected by the address transition detection circuit 2 and the address transition detection signal 3 rises. When the address transition detection signal 3 rises, the high charge transistor 21 and the low charge transistor 22 are driven, and the output node starts to be charged to "H" or "L" (see A1 and A2 in FIG. 4).

Subsequently, the falling edge of the address transition detection signal 3 causes the internal clock generating circuit 4 to generate an output activating signal 5, and the output transistor driving circuit 14 is driven to output a high output signal based on the data of the main amplifier 10. The transistor 15 or the low output transistor 16 is driven, and normal data is output (see T1 in FIG. 4).

At the time of data output, since the output node is in a high impedance state while being charged to "H" or "L" as described above, the output of data "H" in the ground side output buffer circuits 11A1 and 11A2 is performed. (See B1 in FIG. 4), and the output of data “L” in the power supply side output buffer circuits 11B1 and 11B2 is accelerated (see B2 in FIG. 4). That is, from the output of data "H" in the conventional ground-side output buffer circuit (T2 in FIG. 4).
), The ground-side output buffer circuits 11A1 and 11A2 of this embodiment.
Output of data "L" at high speed (see T3 in FIG. 4),
Also, the output of data "H" in the power supply side output buffer circuits 11B1 and 11B2 of this embodiment is faster than the output of data "L" in the conventional power supply side output buffer circuit (see T2 in FIG. 4) (FIG. 4). T3). As a result, the access time can be reduced (T2−T3) as compared with the related art, the variation in the access time among the output terminals 13A1, 13A2, 13B1, and 13B2 can be suppressed, and the overall access time can be shortened.

In this embodiment, the ground-side output buffer circuits 11A1 and 11A2 and the power-supply-side output buffer circuits 11B1 and 11B
The semiconductor integrated circuit device provided with B2 has been described,
The present invention may include any of the ground-side output buffer circuits 11A1 and 11A2 or the power-supply-side output buffer circuits 11B1 and 11B2.

Further, the present invention is not limited to a storage device, and can be applied to various semiconductor integrated circuit devices that output data by performing calculations and the like.

[0027]

As described above, according to the present invention, an address transition is detected at the time of reading data, and the output node is charged to "H" or "L" before outputting the normal data. Therefore, it is possible to suppress variations in access at the output terminal. As a result, the access time can be shortened, and a high-speed read operation can be realized.

[Brief description of the drawings]

FIG. 1 is a layout conceptual diagram of the present invention.

FIG. 2 is a circuit diagram showing a ground-side output buffer circuit of the present invention.

FIG. 3 is a circuit configuration diagram showing a power supply side output buffer circuit of the present invention.

FIG. 4 is a timing chart at the time of data output.

FIG. 5 is a block diagram showing a semiconductor integrated circuit device.

FIG. 6 is a circuit diagram showing a conventional output buffer circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address signal 2 Address transition detection circuit 3 Address transition detection signal 4 Internal clock generation circuit 5 Output activation signal 6 Decoder 7 Memory cell 8 Data 9 Sense amplifier 10 Main amplifier 11A1,11A2,11B1,11B2 Output buffer circuit 12 Output data 13A1 , 13A2,13B1,13B2 Output terminal 14 Output transistor drive circuit 15 High output transistor 16 Low output transistor 17 Parasitic impedance of power supply wiring 18 Parasitic impedance of ground wiring 19 Power supply terminal 20 Ground terminal 21 High charge transistor 22 Low charge transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H03K 19/0175 H03K 19/00 101F

Claims (3)

(57) [Claims] A power supply line is connected at a position relatively close to a power supply terminal.
Compared with the connected first output buffer circuit and power supply terminal
The second output buffer circuit connected to the power line at a position far from
And the first and second output buffer circuits.
That is, only the second output buffer circuit outputs normal data.
High charge transistor that charges output node to H level before
A semiconductor integrated circuit device comprising: 2. A grounding wire which is relatively close to a grounding terminal.
Comparison with the connected first output buffer circuit and the ground terminal
The second output buffer circuit connected to the ground line at a remote position
And the first and second output buffer circuits.
That is, only the second output buffer circuit outputs normal data.
Low charge transistor that charges output node to L level before
A semiconductor integrated circuit device comprising: 3. The transition of an address signal when reading data.
Address that detects the transition and outputs the address transition detection signal
A transition detection circuit, and an address transition detection signal from the address transition detection circuit.
Receiving and driving the charging transistor.
The semiconductor integrated circuit device according to claim 1.