JPH0652695A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To remove an useless waiting time such as a margin time and to increase a speed for reading data by deciding the latch timing of a flip-flop corresponding to the real ascertaining time of a sense amplifier. CONSTITUTION:This device is provided with sense amplifiers 5a1-5d1 for reading the contents of memory cells 2a-2d specified by address signals A0-A18 and a timing deciding means 10 deciding a timing for taking the outputs of the sense amplifiers out of the chips. The first dummy part 11 in the constituting elements of the timing deciding means 10 is provided with a dummy memory cell having the same composition or the same input/output delay as that of the memory cells and a second dummy part 12 is provided with a dummy sense amplifier having the same composition or the same input/output delay as that of the sense amplifier. Also, a signal generating part 13 is provided and the timing for taking the outputs of the sense amplifiers 5 a1-5ad out of the chips based on the time when the output of the dummy sense amplifier is ascertained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an improved read speed.
In recent years, in a personal computer, a word processor, etc., an OS (operating system) and application software are converted into a ROM (read only memory) to enable a much faster system start-up than a floppy disk or a hard disk. However, when launching large-scale software, R
Even with OM, some waiting time cannot be denied. Therefore, in order to improve the system start-up performance, a semiconductor memory device capable of higher-speed reading is required.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a conventional semiconductor memory device and is a block diagram of a mask ROM. In FIG. 5, 1 is an address buffer, 2a to 2d are memory cell arrays, 3a and 3b are row decoders, 4 is a column decoder group, 5 is a sense amplifier group, 6 is a flip-flop group, and 7 is a group.
Is an output buffer, 8 is a control circuit, and 9 is a timing circuit. The column decoder group 4 includes eight column decoders 4a _{i to} 4d _i (i is 1 or 2), the sense amplifier group 5 includes eight sense amplifiers 5a _{i to} 5d _i , and the flip-flop group includes Reference numeral 6 is composed of eight flip-flops 6a _{i to} 6d _i .

This mask ROM has a chip select signal CE (bars omitted in the specification) and an output enable signal OE (bars omitted in the specification).
Is set to the L level and the address signals A _{0 to} A ₁₈ are sequentially updated during the L level period, the contents of the memory cell arrays 2a to 2d can be continuously read in byte units. O _{1 to} O ₈
Is read data of 1 byte (8 bits), and the output timing of this data is from the timing circuit 9 which permits the latch operation of each of the flip-flops 6a _{i to} 6d _i (i is 1 or 2) of the flip-flop group 6. Timing signal TMG.

FIG. 6 is a block diagram of the timing circuit 9. The timing circuit 9 includes inverter gates 9a-9
d, P-channel MOS transistor 9e, OR gate 9
A rise of an ATD (address transient detection) signal (a positive logic pulse signal generated in response to a change in the address signals A _{0 to} A ₁₈ ) formed by the address buffer 1 and composed of f, a resistor 9g and a capacitor 9h. From the time point, a signal (TMG) that maintains the H level is generated for a predetermined time td that is mainly determined by the time constants of the resistor 9g and the capacitor 9h. The latch operation of the flip-flops 6a _{i to} 6d _i is permitted at the falling timing of the signal TMG.

That is, as shown in FIG. 7, when the ATD signal is produced in response to the change of the address signal when CE (and OE) is at the L level, the TMG signal is synchronized with the rising edge of the ATD signal. Changes to H level. This is because the output of the inverter gate 9a becomes L level and P
This is because the channel MOS transistor 9e is turned on and the capacitor 9h is rapidly charged to the potential of the high-potential-side power supply V _CC , so that the charging potential (corresponding to the H level) of the capacitor 9e is two-stage inverter gates 9c, 9d This is because the same logic is taken out through the NOR gate 9f.
When the ATD signal returns to L level, the inverter gate 9a
Output goes high and the P-channel MOS transistor 9e is turned off. At this time, since the output of the other inverter gate 9b becomes L level, the charge of the capacitor 9h is discharged toward this L level (the discharge time constant is mainly determined by the value of the capacitor 9h and the value of the resistor 9g), When the voltage falls below the threshold value of the inverter gate 9c, the output of the NOR gate 9f changes to the L level.

Therefore, in such a conventional mask ROM, first, a specific memory cell in the memory cell array is designated by an address signal, then the content of the memory cell is amplified by a sense amplifier, and then a TMG signal is supplied. A series of operations is obtained in which the output of the sense amplifier is latched by the flip-flop at the falling edge of.

[0007]

However, in such a conventional semiconductor memory device, the latch timing of the flip-flop, that is, the output timing of the read data to the outside of the chip is a constant time determined by the resistor 9g and the capacitor 9h. Since it was defined by "td",
There is a technical problem to be solved, which is insufficient from the viewpoint of further improving the reading speed.

That is, it is "ideal" that the time td coincides with the time from when the address signal changes (when the ATD signal is generated) until the outputs of all the sense amplifiers are completely determined. This is because a certain amount of variation cannot be avoided in the output confirmation time of the sense amplifier due to a manufacturing error or the like. Therefore, in practice, an appropriate margin time tm for absorbing this variation must be taken into consideration. . [Purpose] Therefore, according to the present invention, by determining the latch timing of the flip-flop in correspondence with the actual fixed time of the sense amplifier, unnecessary waiting time such as margin time is eliminated, and the data reading speed is increased. The purpose is to

[0009]

In order to achieve the above object, the present invention determines a sense amplifier for reading the contents of a memory cell designated by an address signal and a timing for taking out the output of the sense amplifier to the outside of the chip. And a dummy memory cell having the same configuration or input / output delay as the memory cell, and the same configuration or input / output delay as the sense amplifier. The same dummy sense amplifier is provided, the content of the dummy memory cell is changed in response to the change of the address signal, the content of the dummy memory cell is read by the dummy sense amplifier, and the dummy sense amplifier The output of the sense amplifier is extracted to the outside of the chip based on the time when the output is fixed. And determining the timing.

[0010]

According to the present invention, when the address signal changes, the content of the memory cell designated by the address signal is read from the sense amplifier, and in parallel with this, the content of the dummy memory cell is read from the dummy sense amplifier. . Then, in response to the confirmation of the output of the dummy sense amplifier, the output of the sense amplifier is taken out of the chip.

Therefore, the data can be read at a timing almost equal to the actual output of the sense amplifier, and the dead time corresponding to the margin time can be eliminated to speed up the data reading.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are views showing an embodiment of a semiconductor memory device according to the present invention, in which a mask RO similar to the conventional example at the beginning is used.
This is an example applied to M. The same reference numerals are given to the circuit elements common to the conventional ones.

First, the structure will be described. In FIG. 1, 1
Uses the lower 10 bits (A _{0 to} A ₉ ) of the 19-bit address signal A _{0 to} A ₁₈ provided from the outside of the chip as the column address signal C _ADRS , and the remaining 9 bits (A _{10 to} A ₁₈ ).
Is output as a row address signal R _ADRS , and a pulse-shaped ATD signal is output each time the address signals A _{0 to} A ₁₈ change. 2a to 2d are 512 × 2k bits (1k is 1024 bits). Memory cell arrays 3a, 3b having memory cells (not shown)
Is a row decoder that selects one of 512 word lines (also referred to as row lines) of the memory cell arrays on both sides according to the row address signal R _ADRS .

Reference numeral 4 denotes eight column decoders 4a _i.
4d _i (i is 1 or 2), and each column decoder has a half (1) of 2k bit lines (also called column lines) of the memory cell array.
k), and selects one of 1k according to the column address signal C _ADRS . Also, 5
Are sense amplifiers 5a _{i to} 5d _i for each column decoder.
Is a group of sense amplifiers, each of which senses the contents of the memory cell via the data line selected by the corresponding column decoder, and amplifies and outputs the read data.

[0015] 6 is a flip-flop group including a flip-flop 6a _i ~6a _i for each sense amplifier, each of the flip-flop latches the output of the corresponding sense amplifier at a timing of the falling of the TMG signal It is a thing. An output buffer 7 outputs the contents of eight flip-flops as 1-byte (8-bit) read data O _{1 to} O ₈ to the outside of the chip.
A control circuit 8 generates various control signals based on the negative logic chip select signal CE and the output enable signal OE.

Here, 10 is a timing determining means which is a feature of this embodiment. Timing determination means 10
Consists of a first dummy section 11, a second dummy section 12 and a signal generating section 13, the detailed configuration of which is shown in FIG. In FIG. 2, the first dummy section 11 includes a two-stage inverter gates 11a and 11b, a P-channel MOS transistor 11c and a capacitor 11d connected between a high potential side power supply V _CC and a low potential side power supply V _SS. A resistor 11e connected between the inverter gate 11b in the subsequent stage and the drain of the P-channel MOS transistor 11c, and an N-channel MOS transistor 11f having a gate-source potential as a potential across the capacitor 11d. here,
It is important that the N-channel MOS transistor 11f is a device having the same configuration as each memory cell (hereinafter, true memory cell) forming the memory cell array of FIG. 1 or a device having the same input / output delay. This is the N
This is a requirement for causing the channel MOS transistor 11f to function as a dummy memory cell. Also, the resistor 11e
Is set to be equivalent to the resistance component of the word line of the memory cell array of FIG. 1, and the capacitance of the capacitor 11d is
It is desirable to set it to be equivalent to the parasitic capacitance of the same word line.
This allows the resistor 11e and the capacitor 11d to function as a dummy word line.

ATD signal transits from L level to H level
Then, the output of the first-stage inverter gate 11a (L level
The P-channel MOS transistor 11c is turned off by
Via the P-channel MOS transistor 11c
And capacitor 11d is V_CCBecause it is charged to N channel
The MOS transistor 11f is turned on, and the signal DM
_OUTIs output at a potential corresponding to the L level. Also, A
When the TD signal changes from H level to L level,
The second MOS transistor 11c is turned off and the second stage
The output (L level) of the inverter gate 11b of
The discharge of the capacitor 11d is started. The discharge time constant is
Mainly the size of the resistor 11c and the capacity of the capacitor 11d
Given in. The potential across the capacitor 11d is
N channel MO after a predetermined time determined by the electric time constant
Lowered to below the threshold of S-transistor 11f
Then, the N-channel MOS transistor 11f is turned off.
And the signal DM_OUTIs the potential corresponding to H level (high
Peedance state).

The second dummy section 12 has the same structure as the sense amplifier of FIG. 1, and functions as a dummy sense amplifier as described in the gist of the invention as a whole. Here, when the signal DM _OUT has a potential corresponding to the L level, the gate of the N-channel MOS transistor 12b is raised via the P-channel MOS transistor 12a, and the N-channel MOS transistor 12b and the P-channel M
Node N via OS transistors 12c and 12d
Signal D of the potential with pulling slightly V _CC direction i.e. H level, the node N and the reverse logic through the CMOS gates 12e~12g of three stages (i.e. DM _OUT opposite logic)
It is configured to output S _OUT . Also, DM _OUT
When a transition from the potential corresponding to the L level to the potential corresponding to the H level, the potential of the node N (potential corresponding to the H level) at that time passes through the N channel MOS transistor 12h and the N channel MOS transistor 1
The gate of 2b is lowered to turn off the N-channel MOS transistor 12b to bring the node N to a potential corresponding to the H level. The P-channel MOS transistor 12d and the N-channel MOS transistor 12i are elements that control the operation / non-operation of the second dummy portion 12, and will be described later in TMG (bar).
The operation is permitted when the signal is input at the L level.

The signal generator 13 outputs an ATD (bar) signal having an inverse logic to the ATD signal, and an inverter gate 13a.
And a flip-flop 13d formed by connecting two AND gates 13b and 13c in a crossed manner, and a T having an inverse logic to the output (TMG signal) of the flip-flop 13d.
An inverter gate 13e for outputting an MG (bar) signal is provided, and as shown in the time chart of FIG. 3, the flip-flop 13d is set (TMG = H level) at the fall of the ATD signal (bar), that is, the rise of the ATD signal. Is reset and reset at the falling edge of DS _OUT (TMG =
L level). The set period of the flip-flop 13d represents the substantial signal delay time DTd of the first dummy section 11 and the second dummy section 12. However, the time chart of FIG. 3 shows a case where the signal delays of the inverter gates 13a and 13e and the flip-flop 13d are ignored.

As described above, in this embodiment, as shown in the time chart of the read operation in FIG. 4, the TMG signal falls at the same time when the output of the dummy sense amplifier 12 is fixed. One flip-flop 6a _{i to} 6d _i can be latched, and after the outputs of the sense amplifiers 5a _{i to} 5d _i are determined, the outputs of the sense amplifiers 5a _{i to} 5d _i can be quickly read out to the outside of the chip. That is, since the data read timing corresponds to the actual read delay, unnecessary waiting time such as margin time is eliminated, the read cycle (address update cycle) is shortened, and the read speed is further improved. Can be planned.

[0021]

According to the present invention, since the latch timing of the flip-flop is determined in correspondence with the actual fixed time of the sense amplifier, useless waiting time such as margin time can be eliminated and data reading can be performed. Can be speeded up.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment.

FIG. 2 is a configuration diagram of a timing determining unit according to an embodiment.

FIG. 3 is a timing chart of the timing determining means of the embodiment.

FIG. 4 is a timing chart of a read operation according to an embodiment.

FIG. 5 is an overall configuration diagram of a conventional example.

FIG. 6 is a configuration diagram of a timing circuit of a conventional example.

FIG. 7 is a timing chart of a read operation of a conventional example.

[Explanation of symbols]

A _{0 to} A ₁₈ : Address signals 5a _{i to} 5d _i : Sense amplifier 10: Timing determining means 11d: Capacitor (dummy word line) 11e: Resistor (dummy word line) 11f: N-channel MOS transistor (dummy memory cell) 12: Second dummy section (dummy sense amplifier)

Claims (2)

[Claims] 1. A semiconductor memory device comprising: a sense amplifier for reading the contents of a memory cell designated by an address signal; and a timing determining means for determining a timing for taking out the output of the sense amplifier to the outside of the chip, The determining unit includes a dummy memory cell having the same configuration as that of the memory cell or the same input / output delay as that of the memory cell, and a dummy sense amplifier having the same configuration as that of the sense amplifier or having the same input / output delay as the sense amplifier. In response to the change, the content of the dummy memory cell is changed, the content of the dummy memory cell is read by the dummy sense amplifier, and the output of the sense amplifier is compared to the chip based on the time when the output of the dummy sense amplifier is determined. Semiconductor memory characterized by deciding the timing of taking out to the outside apparatus. 2. The semiconductor memory according to claim 1, wherein the content of said dummy memory cell is changed in accordance with a predetermined signal in response to a change in said address signal transmitted via a dummy word line. apparatus.