JP3152713B2 - Electroplating method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for electroplating a semiconductor device, and more particularly to a method for electroplating a semiconductor device in which the surface of a semiconductor substrate is electroplated.

[0002]

2. Description of the Related Art As a typical example of a conventional semiconductor device manufacturing method, there is an electrolytic plating method in a bump electrode forming step of a semiconductor device. FIG. 7 shows a manufacturing apparatus for performing this electrolytic plating method.

In a semiconductor device 1 shown in FIG. 7, a semiconductor element is formed on a substrate 2, and an insulating protective film 4 having an opening above an Al electrode pad 3, for example, Pd
/ Ti or other metal layer 5 is deposited on the entire surface. A photoresist layer 6 having an opening corresponding to a bump diameter of a desired size is formed only on the electrode pad 3 on the metal layer 5.
Are formed as plating masks.

In the semiconductor device 1 having the above-described structure, a plating surface on which a plating mask is formed faces downward, as shown in FIG. Then, as shown in FIG. 8, the photoresist layer 6 is broken by the cathode electrode pins 8 around the cup 7 holding the semiconductor device 1, and the electrical conduction with the metal layer 5 under the photoresist layer 6 is established. Can be

[0005] Further, as shown in FIG.
Is supplied to the plating surface by blowing up from the lower part of the cup 7 to the upper part through the anode electrode 10 and returns to the liquid tank from the upper part of the cup 7 in an overflow manner. Also, by spraying the N ₂ gas 11 on the back surface of the substrate 2 of the semiconductor device 1, the plating solution 9 is prevented from wrapping around to the back surface, and unnecessary plating deposition is suppressed. As a mass production device, a device in which 24 to 25 cups are installed in parallel in one plating tank is generally used.

[0006]

According to the above-mentioned prior art, since the plating solution is blown up and overflown, the flow rate of the plating solution is smaller at the peripheral portion than at the central portion of the plating surface. Correspondingly, as shown in FIG. 9, the plating thickness, that is, the bump height is lower at the peripheral portion than at the central portion, and the in-plane uniformity is poor, which causes a TAB lead bonding failure.

[0007] Further, in the above-described technique, it is advantageous to be able to prevent plating deposition on the back surface.
In the case of the above plating electrode and Au plating, a metal layer such as Pd / Ti serving as a layer for suppressing mutual diffusion with an Al electrode pad is formed by a vacuum deposition method, a sputtering method, or the like, and beveling of the outermost periphery of the semiconductor substrate. A metal layer is partially deposited on a portion where a photoresist layer as a plating mask cannot be formed, such as a processed portion. Therefore, plating deposition occurs and becomes a source of dust in the back surface grinding process and dicing process of the semiconductor device. In the case of a soft metal such as Au plating, the grinding wheel and the dicing blade become clogged and become unusable. cause. As a matter of course, plating deposition other than on the upper part of the electrode pad 3 is equivalent to an increase in the deposition area, and a low bump height can be obtained with a plating current value set to obtain a desired bump height. I will.

Further, in order to hold the plating surface of the semiconductor device downward, bubbles generated by the piping system of the plating solution 9 and the dissolved gas in the plating solution 9 become a plating mask on the plating surface, and are locally localized. There is no plating deposition, which causes an accident that results in a defective chip. For this reason, the bump formation step adds a further step to the finished product as a normal semiconductor device, and a decrease in the yield in the bump plating step results in a significant increase in cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is directed to a process for electrolytic plating a semiconductor device surface.
A semiconductor that does not become bumps lower than a desired height, improves in-plane uniformity of plating thickness, does not cause bonding failure of a TAB lead, and does not cause a significant cost increase due to a decrease in yield in a bump plating process. An object of the present invention is to provide a method for electroplating an apparatus.

[0010]

That is, the present invention relates to an electrolytic plating method for forming a bump electrode of a semiconductor device.
Electroplating is performed by holding only the plating surface of the semiconductor device surface exposed in a plating solution tank and arranging an anode electrode as a common electrode of a plurality of substrates without facing the semiconductor device. And

Further, the present invention provides an electrolytic plating method for forming a bump electrode of a semiconductor device, wherein only the plating surface of the semiconductor device is held in a state of being exposed in a plating solution tank, and the plating surface of the semiconductor device is held. And the normal line of the above-mentioned anode electrode is orthogonally arranged to perform electrolytic plating.

[0012]

In the method for electroplating a semiconductor device according to the present invention, for example, in a bump electrode forming step, a jig for sealing the back surface and the outermost beveling portion of the semiconductor substrate is used to place the semiconductor substrate in a plating tank. And a plurality of common anode electrodes are arranged so as to be orthogonal to the semiconductor substrate without facing the semiconductor substrate at the time of plating.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a structure of a plating apparatus for performing an electrolytic plating method for a semiconductor device according to the present invention.

FIG. 1A shows the arrangement of electrodes in a multi-plate simultaneous plating bath, and FIG.
FIG. In FIG. 1, a pair of anode electrodes 13, which are mesh-shaped electrodes made of a Ti material whose surface is coated with Pt and serve as anodes during electrolytic plating, are arranged in a plating tank 12. A plurality of jigs 14 are vertically arranged between the anode electrodes 13. In these jigs 14, a photoresist layer having an opening corresponding to a bump diameter of a desired size is formed as a plating mask only on the upper part of the electrode pad, and formed on the entire lower layer of the resist layer. A metal layer of Pd / Ti or the like serves as a cathode electrode during electroplating to expose a plating surface 15 of the surface of the semiconductor substrate into a plating solution 16 to cut off contact between the plating solution and the back surface of the semiconductor device and the peripheral bevel processing site. Things.

The cathode electrode 17 is provided outside the plating tank 12, and the electrical connection between the cathode electrode 17 and the plating surface 15 is made from the cathode electrode 17 to the plating surface 15 via the jig 14. This is done by reaching the electrode pins or the like.
FIG. 2 shows a configuration example of the jig 14.
2A is a perspective view, FIG. 2B is a sectional view of FIG. 2A, and FIG. 2C is a side view of FIG.

The jig 14 includes a main body 14 ₁ , an upper cover 1
4 and consists of _2, the main body portion 14 ₁ of the power feeding plug 14 that in part is connected to an external cathode electrode 17 ₃ and packing screw 14 ₄ are provided. Also, the upper cover 14
The substantially central portion of the _2, holes 14 ₆ so as to secure the wafer to the opposite position and wafer placing portion 14 ₅ formed on the main body portion 14 ₁ is formed. Wafer, on section 14 ₅ placing the wafer, a plating surface to be set in the table.

Further, the main body portion 14 ₁ and the upper lid portion 14 ₂ is opened and closed in the arrow A direction axis Kaidakku round bar 14 _7. The entire surface of the jig 14 is coated with Teflon except for a part. In addition, 14 ₈
Energizing unit 14 ₉ is packing.

In this embodiment, a current density of 5 mA / cm ² is used by using a cyan Au plating solution (trade name: Tempery 401). , Plating bath temperature 65 ° C, plating time 60
An Au bump having a bump diameter of 60 × 60 μm and a bump height of 18 μm is formed under the plating conditions of minute.

In particular, in the case of electrolytic deposition from a plating solution that forms metal complex ions in a solution, it is considered that the factor governing in-plane uniformity is greater in the effect of the plating solution flow than the electric field, This is the process of controlling the supply of complex ions. Therefore, as shown schematically in FIG. 7, the flow of the plating solution,
In the case of the conventional cup method, the plating layer is thicker in the central portion of the wafer than in the peripheral portion. Therefore, in the case of the wafer immersion method as shown in FIG. 1B, it is considered that the in-plane uniformity of the plating thickness is improved by making the flow of the plating solution uniform on the wafer surface.

FIG. 3 shows the results of actually performing bump plating on a 5-inch wafer under the above plating conditions and examining the in-plane distribution of bump height. This clearly indicates that the in-plane uniformity of the bump height can be significantly improved. The relationship between the bump height and the flow rate and the relationship between the height variation and the flow rate will be described below with reference to FIGS.

FIG. 5 is a diagram showing the flow of the plating solution when the wafer (cathode electrode) 17 and the anode electrode 13 are arranged to face each other in the plating tank 12. The plating solution that has overflowed the plating bath 12 flows into the plating solution circulation bath 18. At this time, the bump height (Au deposited on the wafer)
The amount is dependent on the flow rate of the liquid rather than the distance between the wafer and the anode electrode (the magnitude of the electric field). The greater the flow rate, the greater the amount of deposition. That is, the supply rate of Au ions is determined.

On the other hand, the behavior of the in-plane variation is also dominated by the flow rate. Therefore, it can be seen that in the case of plating deposition from complex ions, the flow of the liquid is the dominant factor. Therefore,
The arrangement of the anode electrode does not need to be opposed to the wafer.

Further, since the effect of the electric field on the in-plane uniformity is small, as shown in FIG. 1, even if the wafer plating surface 15 serving as a cathode and the anode electrode 13 are orthogonally arranged in a plating solution, the surface of the bump height may be reduced. In order not to affect the internal distribution, the anode electrode 1
3 can be used as a common electrode to plate a large number of wafers in the same tank, and there is an advantage that the installation area can be greatly reduced as compared with a conventional cup-type apparatus. In the case of processing a large number of sheets per power supply, a high resistance (about 100 to 200Ω) is pre-loaded on the jig 14 so that the contact resistance between the electrode pins and the plated surface 15 and the resistance of the jig itself are non-uniform (~ (Approximately 1Ω), so that the current flows evenly through each wafer.

The present invention is not limited to this. For example, as shown in FIG. 6, the jig 14 may be inserted and arranged in a horizontal direction, and the wafer may be immersed in a plating solution with the plating surface 15 facing upward. . In this case, the common anode electrode 19 and the wafer are orthogonal.

[0025]

As described above, according to the present invention, the in-plane uniformity of the bump height can be remarkably improved, and the bonding failure of the TAB lead can be reduced. Significant improvements in reliability and yield can be achieved.

[Brief description of the drawings]

FIG. 1 is a view showing a structure of a plating apparatus for performing an electrolytic plating method of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a view showing details of the jig of FIG. 1;

FIG. 3 is a diagram showing an in-plane distribution of bump height.

FIG. 4 is a characteristic diagram showing a relationship between a bump height and a flow rate, and a relationship between a height variation and a flow rate.

FIG. 5 is a diagram showing a flow of a plating solution in a plating tank when a wafer (cathode electrode) and an anode electrode are arranged to face each other.

FIG. 6 is a view showing another example of the present invention, in which the wafer is immersed in a plating solution with the wafer facing upward.

FIG. 7 is a diagram showing a part of a manufacturing apparatus for performing a conventional electrolytic plating method.

FIG. 8 is a view showing a manufacturing apparatus for performing a conventional electrolytic plating method.

FIG. 9 is a diagram showing a conventional in-plane distribution of bump height.

[Explanation of symbols]

12: plating bath, 13: anode electrode, 14: jig, 1
5 plating surface, 16 plating solution, 17 cathode electrode, 18
... Plating solution circulation tank.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toru Watanabe 72 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Horikawa-cho Plant (56) References JP-A-4-107283 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/60 C25D 7/12 H01L 21/288

Claims (3)

(57) [Claims] In an electrolytic plating method for forming a bump electrode of a semiconductor device, only a plating surface of the semiconductor device is held in a state of being exposed in a plating bath, and an anode electrode is used as a common electrode of a plurality of substrates. Is disposed without facing the semiconductor device, and electrolytic plating is performed. 2. An electroplating method for forming a bump electrode of a semiconductor device, wherein only a plating surface of the surface of the semiconductor device is held in a state of being exposed in a plating solution tank, and a normal line of a plating surface of the semiconductor device is provided. And electroplating by orthogonally arranging the normal lines of the anode electrode and the anode electrode. 3. The electrolytic plating method for a semiconductor device according to claim 1, wherein the electrolytic plating uses a plating solution in which a metal complex ion of a metal to be deposited is formed.