JPH0354829A - Electrolytic plating process of bump electrode for integrated circuit device - Google Patents

Electrolytic plating process of bump electrode for integrated circuit device

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Publication number
JPH0354829A
JPH0354829A JP18985289A JP18985289A JPH0354829A JP H0354829 A JPH0354829 A JP H0354829A JP 18985289 A JP18985289 A JP 18985289A JP 18985289 A JP18985289 A JP 18985289A JP H0354829 A JPH0354829 A JP H0354829A
Authority
JP
Japan
Prior art keywords
wafer
plating
film
contact
electrolytic plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18985289A
Other languages
Japanese (ja)
Inventor
Yoshikiyo Usui
吉清 臼井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP18985289A priority Critical patent/JPH0354829A/en
Publication of JPH0354829A publication Critical patent/JPH0354829A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To avoid the metallic separating and the defective contact due to any leakage current by a method wherein a metallic film connecting to underneath film is provided on the rear surface of a wafer; the wafer with its surface faced downward is brought into contact with a plating liquid PL while the rear surface metallic film is connected to a power supply to perform the plating process. CONSTITUTION:A wafer 10 is covered with an oxide film 3; electrode films 4 are arranged on the positions of oxide film 3 whereon bump electrodes are to be provided; after covering the electrode films 4 with a protective film 5, a window is made so as to coat the surface 10a side of the wafer 10 with an underneath film 7 in contact with the electrode films 4 in the window part. The periphery 6a of the underneath film 6 is coated creeping in the rear surface side chamfer 10a. The rear surface 10b is coated with a metallic film 7 connecting to the underneath film 6. Next, the other underneath films 8 are formed on the surface 10a and removed leaving the positions to provide bump electrode 11 furthermore, the films 8 are exposed to provide a photoresist film 9. Finally, the wafer 10 with its surface 10a looking downward is inserted into a plating jug 25 and then the metallic film 7 is connected to a plating power supply 30 through the intermediary of the contactors 26 of the cover 25 so that the jet stream of plating liquid PL may be brought into contact with the surface 10a to perform the electrolytic plating process for depositing the bump electrodes 11.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路装置のいわゆるフリップチップに外部
との接続用にバンプ電極を設けるため、集積回路装置用
のウェハの表面にバンプ電極をその下地膜をめっき電極
膜に利用して電解めっきによって戒長させる方法に関す
る. 〔従来の技術〕 近年の著しい高集積化技術の進展に伴い、小形の半導体
チップ内に非常に?j!雑な集積回路を作り込めるよう
になったが、これに並行して実装構造を合理化する必要
があり、この有力な手段として外部との接続のためにバ
ンプ電極ないしは突起電極を備えたフリップチップ構造
の重要性が増している.周知のように、フリップチソプ
はパッケージに収納することなくそのままセラミック配
線基板等に実装できるので、実装に要するスペースを極
小にし手間を大幅に省くことができる.さらに最近のマ
イクロバンブ電極は、そのサイズを10μ程度にまで縮
小して数閃角の小形チンプの周縁部に数百個もの外部接
続点を配列できる.かかるバンプ電極は金等の貴金属で
形成されることが多く、そのチップ面からの突出高さは
少なくとも10μ.ふつうは数十n程度が必要なので、
主に経済的な理由で選択的な電解めっき法で或長させる
のが通例で、この電解めっきはチップに単離する前のウ
ェハ状態で行なわれる. 実装時にバンプ電極による確実な接続を保証するにはバ
ンブ電極の高さを精度よく揃えて置く必要があり、ウェ
ハ内の数千個ないしそれ以上のバンブ電極を電解めっき
により均一に或長させるため種々の工夫がなされて来た
.第2図にこの従来の代表的な電解めっきの要領を示す
. 第2図(a)はウェハ10の周縁部の拡大図である.ウ
ェハ10は例えば半導体基板1の上にエビタキシャル層
2を戒長させて集積回路用に図示しない半導体層を作り
込んだもので、図のようにこのウェハ10の表面10a
を下側に,l1面lObを上側にした状態で電解めっき
が行なわれる.ウェハ10の全面を覆う酸化膜3上に配
列された電111i1114を保護膜5で覆い、これに
明けた窓部内でバンブ電極を金属の下地[6と8を介し
て電極膜4と接続するように電解めっきするが、この際
のめっき電極とするため下地膜6で表面10aを覆い、
バンブ電極を設けるべき個所に下地膜8をパターンニン
グし、この下地IIl8を露出させるようにフォトレジ
ストWX9で表面10aを覆う. 第2図(b)はめっき治具20を用いてこのウェハ10
を電解めっきする要領を示す。治具20は漏斗状内面を
もつ本体21と125を備え、本体21の内部には綱状
または多孔板状の陽極22が納められ、そのフランジ状
部2laには鋭い先端をもつめっきビン24が数本立て
込まれていて、その上にウェハ10を前述のようにその
表面10aを下側にして置いた後に蓋25をそのガイド
25aに沿って本体2lに嵌め合わせると、ウェハ10
がその裏面fob側から板ばね27により押されて、同
図(a)のようにめっきピン24の先端がウェハlOの
周縁部でフメトレジストIIi9を突き抜けて下地膜6
と接続される. 電解めっきは、治具本体21の下部開口2lbをめっき
槽40のめっき液導入管41に嵌め込んでめっき液PL
の噴流をウェハ10の表面10aに接触させ、めっきt
if130の正側端子を陽8i22のリード22gに,
負側端子をめっきピン24にそれぞれ接続した状態で行
なわれ、フォトレジスト膜9の窓部内に露出された下地
膜8をめっき#i極としてその上にバンプ電極用金属が
成長される. 以上説明した方法によれば、ウェハ10を治具20に単
にセットするだけで、めっき電極膜としての下地膜6を
めっきピン24を介してめっき電源30と簡単に接続す
ることができ、この状態でフォトレジスト膜9をマスク
として下地膜8上にバンブ電極用の貴金属類を選択的に
,従ってむだなく電解めっき法で或長させることができ
る.また、ウェハ10に接触するめっき液PLが絶えず
入れ換わるので、バンブ電極用金属のめっき厚みのウェ
ハ面内分布を均一にすることができる. 〔発明が解決しようとする課題〕 ところが、上述の従来方法では、ウェハの下地膜とめっ
きピンとの間の接続を両者間のごく小面積の接触に頼っ
ており、しかもこの接触点がめつき液PLで濡れている
ので接触状態が電解めっき中に変化することがあり、こ
のために接触不良になるとめっき淳みのウェハ面内分布
が著しく不均一になって、バンブ′W18iの高さに大
きなばらつきが出る問題がある.第3図はこの接触不良
の発生状態を示すものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides bump electrodes on the surface of a wafer for the integrated circuit device in order to provide a so-called flip chip of an integrated circuit device with bump electrodes for connection with the outside. This paper relates to a method of using a base film as a plating electrode film and increasing the length by electrolytic plating. [Conventional technology] With the remarkable progress in highly integrated technology in recent years, there is a large amount of space available within small semiconductor chips. j! It has become possible to create complex integrated circuits, but at the same time it is necessary to rationalize the mounting structure, and an effective means for this is the flip-chip structure with bump electrodes or protruding electrodes for external connection. is becoming increasingly important. As is well known, flip chips can be mounted directly onto ceramic wiring boards, etc., without being packaged, which minimizes the space required for mounting and greatly saves time and effort. Furthermore, recent microbump electrodes have been reduced in size to about 10μ, making it possible to arrange hundreds of external connection points on the periphery of a small chimp with several flash angles. Such bump electrodes are often formed of noble metals such as gold, and their protrusion height from the chip surface is at least 10 μm. Usually about a few tens of nanometers is required, so
Mainly for economical reasons, it is customary to increase the length by selective electrolytic plating, which is performed on the wafer before it is isolated into chips. To ensure a reliable connection using bump electrodes during mounting, it is necessary to precisely align the heights of the bump electrodes, and in order to uniformly lengthen several thousand or more bump electrodes within a wafer by electrolytic plating. Various efforts have been made. Figure 2 shows the procedure for this typical conventional electrolytic plating. FIG. 2(a) is an enlarged view of the periphery of the wafer 10. The wafer 10 has, for example, an epitaxial layer 2 formed on a semiconductor substrate 1 to form a semiconductor layer (not shown) for integrated circuits, and as shown in the figure, the surface 10a of the wafer 10
Electrolytic plating is performed with the l1 plane and lOb on the lower side and the lOb side on the upper side. The electrodes 111i1114 arranged on the oxide film 3 covering the entire surface of the wafer 10 are covered with a protective film 5, and the bump electrodes are connected to the electrode film 4 through the metal base [6 and 8] within the window opened in this. The surface 10a is covered with a base film 6 to serve as a plating electrode at this time.
A base film 8 is patterned at a location where a bump electrode is to be provided, and the surface 10a is covered with a photoresist WX9 so as to expose the base II18. FIG. 2(b) shows this wafer 10 using a plating jig 20.
This shows how to electrolytically plate. The jig 20 includes main bodies 21 and 125 with funnel-shaped inner surfaces. A rope-shaped or perforated plate-shaped anode 22 is housed inside the main body 21, and a plating bottle 24 with a sharp tip is installed in the flange-shaped portion 2la. When the wafer 10 is placed on top of the wafer 10 with its surface 10a facing down as described above and the lid 25 is fitted onto the main body 2l along the guide 25a, the wafer 10
is pushed by the leaf spring 27 from the back side of the fob, and as shown in FIG.
is connected to. Electrolytic plating is performed by fitting the lower opening 2lb of the jig body 21 into the plating solution introduction pipe 41 of the plating tank 40, and introducing the plating solution PL.
The jet stream is brought into contact with the surface 10a of the wafer 10, and the plating t
Connect the positive terminal of if130 to lead 22g of positive 8i22,
This is carried out with the negative side terminals connected to the plating pins 24, respectively, and the base film 8 exposed within the window portion of the photoresist film 9 is used as the plating #i pole, and a bump electrode metal is grown thereon. According to the method described above, by simply setting the wafer 10 on the jig 20, the base film 6 as a plating electrode film can be easily connected to the plating power supply 30 via the plating pins 24, and in this state Using the photoresist film 9 as a mask, noble metals for bump electrodes can be selectively and wastelessly deposited over a certain length on the base film 8 by electrolytic plating. Furthermore, since the plating solution PL in contact with the wafer 10 is constantly replaced, the distribution of the plating thickness of the bump electrode metal within the wafer surface can be made uniform. [Problems to be Solved by the Invention] However, in the above-mentioned conventional method, the connection between the wafer base film and the plating pins relies on a very small area of contact between the two, and furthermore, this contact point is close to the plating liquid PL. Because the contact condition is wet during electrolytic plating, the contact condition may change during electrolytic plating, and if this causes poor contact, the distribution of plating thickness within the wafer surface becomes extremely uneven, resulting in large variations in the height of bumps W18i. There is a problem that occurs. FIG. 3 shows how this contact failure occurs.

図のように、めっきピン24にもちろん絶縁24aが施
されているのであるが、下地l16と接触するめっきピ
ン24の先端露出部がめつき液PLで濡れてしまい、あ
るいはめっきピン24とフォトレジスト膜9の間の僅か
な隙間からめっき液PLが先端露出部に侵入するので、
めっき電流の一部が漏れて図のような金属析出Dが生じ
やすい.Rいことに、この析出が進むにつれて金属析出
Dの表面積が増えるのでめっき電流に対する漏洩電流の
割合が漸次増加し、最後にはめっきビン24と下地膜6
の接触抵抗が加速度的に増大するに至る.もちろん、め
っきピン24は数個所で下地[6と接触してはいるが、
かかる接触不良が生じた個所の付近のバンブ電極11が
図のようにいわば極端な発育不全の状態になるので、そ
のウェハを不良として廃棄するはかなくなってしまう. 本発明の目的は、電解めっき中のかかる漏れ電流による
金属析出や接触不良の発生を防止して、ウェハ全面に亘
って均一な厚みでバンブ電極用金属を成長させることに
ある. 〔課題を解決するための手段〕 本発明によればこの目的は、前述のようにウェハの表面
にバンブ電極をその下地膜をめっき電極膜に利用して電
解めっきにより或長させるため、ウェハの裏面にこの表
面の下地膜と接続された接続金漠膜を設け、ウェハの表
面を下に向けてそれのみをめっき液に接触させ、かつウ
ェハ真面の接続金属膜をめっき電源に接続した状態で電
解めっきを行なうことによって達威される. なお、上記構或中のウェハ裏面に設ける接続金属膜に下
地膜と異なる材料を用いることができるが、むしろ同じ
材料を用いるのがウェハプロセスを簡単にする上で最も
望ましい.この接続金属膜をウェハ表面側の下地膜と確
実に接続するには、下地膜と接続金属膜を蒸着やスパッ
タで被着する際のいわゆる回り込みを利用して、両膜が
ウェハの周縁において互いに重なり合うようにするのが
最も簡単である.この際、ウェハの周縁の面取りを従来
より若干大きくして置くことにより、この重なり合いを
確実にすることができる.本発明方法においても、従来
と同様な本体の内面が漏斗状に形威されためっき治具を
用いて前述の噴流式めっき法の利点をそのまま活かすこ
とができる.この際、治具蓋に小流量のガスを導入して
ウェハの周縁から洩れ勝手にすることにより、ウェハの
裏面側へのめっき液の侵入を完全に防止して、ウェハの
表面だけにめっき液を接触させる本発明の条件を確実に
することができる.なお、従来のウェハ抑え用の仮ばね
は、接続金属膜に対する接触子として本発明方法に利用
できる.〔作用〕 従来はめっき電極膜としての下地膜へのめっきビンの接
触点がめつき液で濡れる点に問題の原因があるので、本
発明方法はこの下地膜と接続された接続金属膜をウェハ
の裏面に設け、電解めっき時にめっき液をウェハの表面
のみに接触させ、めっき液で濡れないウェハの裏面側で
接続金属膜をめっきtIlに接続することにより、めっ
き電流の洩れをなくしてウェハ全面にバンブ電極用金属
を均一に或長させるものである. 〔実施例〕 以下、第1図を参照しながら本発明の実施例を説明する
.図中の前に説明した第2図に対応する部分には同じ符
号が付されている. 第1図(a)は複数個の集積回路装置用のウェハ10の
第2図(a)に対応する周縁部の拡大断面であり、本発
明の場合その周縁の表filloa側の面取り10dと
冨面10b側の面取りfeeは、第2図(2)の場合の
面取り10cよりも図示のように大きいめにするのがよ
く、かつ表面側の面取り10dの傾斜は若干緩やかにす
るのが望ましい.従来と同じく、このウェハ10をまず
酸化膜3で覆い、その上のバンブ電極を設けるべき個所
に集積回路と接続された電極W14を配設し、これを窒
化シリコン等の保護膜5で覆った後に電極WA4上に窓
を明け、この窓部内で電極膜4に導電接触するようにチ
タン等の下地膜6をウェハ10の表面10a側に蒸着法
やスバッタ法でふつう 0.2〜0.5μ程度の厚みに
被着する.この下地膜6の周a6aは裏面側面取り10
eの方にふつう10n程度回り込んで被着される.本発
明方法における接続金属膜7は、この下地WA6との被
着に引き続きかつそれと同材料,同方法で、ただし若干
厚めの例えば0.5n前後の厚みに被着するのがよく、
蒸着ないしスパッタ時にその周縁7aが前と同様にウェ
ハの表面側面取り10dの方に回り込んで被着され、こ
れによってごく低い接触抵抗で下地膜6と接続される.
次に従来と同様に、ウェハの表面10aにバンブ電極側
の下地膜8として例えば銅を0.5〜1nの厚みに全面
被着してフォトエッチングによりバンプ電極を設けるべ
き個所のみを残して除去し、さらにフォトプロセスによ
り表面10a側にフォトレジスト膜9を下地膜8を露出
させるように設ける. この第l図(a)がウェハ1oの電解めっき準備の完了
状態であって、裏面lOb側の接続金属M7は表面10
a側のめっき電極膜としての下地膜6と上述の周縁の重
なり合いにより確実に接続され、ウェハ10のめっき液
と接触する表面10aとその面取り部10dはバンブ電
極側下地!I!8を除いてフォトレジスト膜9によって
覆われる. 第1図山》に電解めっきの状態を示す.めっき治具20
が漏斗状内面をもつ本体21と蓋25とを備え、これに
ウェハ10を表面10aを下側に向けて装入するのは従
来と同じであるが、本体21の上部のフランジ状部21
aにウェハ10用の支承ピン23を周方向の複数個所例
えば3個所に備え、125に小径のガス導入管25bと
接触子26とを備える点が異なる.本体21側の支承ピ
ン23は絶縁物や絶縁被覆された金属線で、その先端で
ウェハ10の周縁部を複数個所で支承する役目を果たす
.陽8i22は従来と同じであるが、金めつき用には白
金めっきされたチタン網等が,はんだめっき用にははん
だの多孔板等がそれぞれ用いられる.蓋25側の接触子
26は従来と同じ板ばねであってよいが、ウェハ富面1
0bの接続金属膜7と導電接触させるので白金等のめっ
きを施して置くのが望ましい.ガス導入管25bからは
小流量の窒素ガスN等を蓋25とウェハ10との間に導
入し、ウェハ10の周縁から多少洩れ勝手にして置くこ
とにより、ウェハ裏面10bのめっき液による濡れを完
全に防止できる. 電解めっきに際しては、めっきpl40のめっき液導入
管41に下部開口2lbが嵌め込まれた治具本体21の
支承ピン23上にウェハ10をその表面10aを下向け
にして載置し、蓋25を被せることにより接触子26を
ウェハ裏面10b上の接続金i膜7と接続しかつウェハ
10を支承ビン23に押し付けて正確に位置決めする.
次に、めっき液PLの噴流をウェハ表面10aに接触さ
せ、望ましくはガス導入管25bから窒素ガスN等を導
入した状態で、めっき$B30の正負端子に陽極22用
のりード22aと接触子26を接続して電解めっきを行
なう. 第1図(C)はウェハ10の完戒状態を示し、上述の電
解めっきにより下地膜8上に金やはんだ等のバンプ電極
11を或長させた後、同図(a)のフォトレジストM9
を除去し、次に下地M8とバンブt極11をマスクとし
てウェハ表TliflOaの下地膜6と稟面10bの接
続金属M7を化学エッチングして図示の状態とする.接
続金属l!l7が下地膜6と同じチタン膜の場合、薄い
ぶつ酸液による同時エッチングで両膜を簡単に除去でき
る. 以上の本発明方法においては、電解めっきの対象である
ウェハlOの表面10aにのみめっき液PLが接触し、
裏面10b側の接続金II!Wl47と接触子26との
接続点がめつき液PLで濡れることがないので、従来の
ようなめっき電流の洩れのおそれがなく、電解めっき中
この接続状態を常に安定に保ってウェハの全面に亘リバ
ンプ電極用金属を均一に或長させることができる.本発
明の実施により、同一ウェハ内のすべてのS積回路用チ
ップについてバンプ電極の高さのばらつきを±10%以
下に抑え、この高さの不揃いによる不良率を従来の数分
のlからlO分の1に減少させることができる.以上説
明した実施例に限らず本発明方法は種々の態様で実施を
することができる.例えば、接続金属膜や下地膜用材料
はもちろん電解めっきの種類等に応じて種々の選択が可
能であり、電解めっき用治具の構威も望ましい実例では
あるがあくまで例示であって、電解めっき作業上の条件
や必要に応じて種々変形された構或ないし構造のものを
用いて本発明を実施できる. 〔発明の効果〕 以上の説明からすでに明らかなように、本発明方法では
集積回路装置用ウェハの表面にバンプ電極をその下地膜
をめっき電極膜として電解めっきにより戒長させるに際
し、ウェハの裏面に表面の下地膜と接続された接続金属
膜を設け、ウェハの表面を下に向けてそれのみにめっき
液を接触させかつウェハの裏面の接続金属膜をめっき電
源に接続した状態で電解めっきを行なうことにより、め
っき電8i膜としての下地膜をそれと接続された接続金
属膜を介してめっき液で濡れることがないウェハの裏面
でめっき電源と接続することができ、これにより従来の
ような電解めっき中漏れ電流による金属析出や接触不良
の発生を完全に防止し、ウェハ全面に亘って均一な厚み
でバンブ電極用金属を或長させることができる. 本発明方法は、小形のバンプ電極を多数個設ける集積回
路装置の製造にとくに適し、バンブ電極の高さを均一に
揃えて実装時の接続の信頼性を高める効果を上げること
ができる. 本発明の実施にはウェハの裏面に接続金属膜を被着する
工程を追加する必要があるが、望ましくはこれと下地膜
を同材料および同手段で引き続いて被着することにより
、実質上従来と変わらない工程で接続金属膜を設けるこ
とができ、かつバンプ電極の電解めっき後の両膜の除去
を1工程で済ませることができる.また実施例のように
、本発明は従来の例えば噴流めっき用治具の構造を僅か
変えるだけ実施でき、ウェハの装入と取り出しが容易で
めっき条件の管理が容易なその利点をそのまま活かしな
がら、その欠点を克服してめっき厚みの均一性を改善で
きる. このように本発明方法は、従来と実質上同等な工程と設
備で電解めっき作業を進めながら、ウェハ全面に亘って
バンブ電極を均一な高さに成長させて、高さの不揃いに
よる不良率を前述のように格段に減少させる効果を上げ
、とくに高集積度でバンブ電極数の多い小形のフリツブ
チップに適用して、その実装時の接続信頼性を高める著
効を奏することができる.
As shown in the figure, the plated pin 24 is of course provided with an insulator 24a, but the exposed tip of the plated pin 24 that comes into contact with the base l16 gets wet with the plating solution PL, or the plated pin 24 and the photoresist film become wet. Since the plating solution PL enters the exposed tip part through the small gap between 9,
Part of the plating current leaks and metal deposits D as shown in the figure are likely to occur. In particular, as the deposition progresses, the surface area of the metal deposit D increases, so the ratio of leakage current to the plating current gradually increases, and eventually the plating bottle 24 and the base film 6
The contact resistance increases at an accelerating rate. Of course, the plated pin 24 is in contact with the base [6] at several places,
Since the bump electrode 11 near the location where the contact failure has occurred becomes extremely stunted as shown in the figure, it becomes impossible to discard the wafer as defective. The purpose of the present invention is to prevent metal deposition and poor contact caused by such leakage current during electrolytic plating, and to grow bump electrode metal with a uniform thickness over the entire wafer surface. [Means for Solving the Problems] According to the present invention, this object is achieved by forming a bump electrode on the surface of a wafer to a certain length by electrolytic plating using the underlying film as a plating electrode film as described above. A connection metal film connected to the base film on the front surface is provided on the back side, the front surface of the wafer is facing down, and only it is in contact with the plating solution, and the connection metal film on the front side of the wafer is connected to the plating power source. This can be achieved by electrolytic plating. Although it is possible to use a different material from the base film for the connecting metal film provided on the back surface of the wafer in the above structure, it is most desirable to use the same material in order to simplify the wafer process. In order to reliably connect this connection metal film to the base film on the wafer surface side, the so-called wraparound when depositing the base film and connection metal film by vapor deposition or sputtering is used to ensure that both films meet each other at the periphery of the wafer. The easiest way is to make them overlap. At this time, this overlapping can be ensured by making the chamfer around the wafer's periphery slightly larger than before. In the method of the present invention, the advantages of the jet plating method described above can be utilized as is by using a conventional plating jig whose inner surface is shaped like a funnel. At this time, by introducing a small flow of gas into the jig lid to prevent it from leaking from the periphery of the wafer, the plating solution is completely prevented from entering the back side of the wafer, and the plating solution is applied only to the surface of the wafer. It is possible to ensure the conditions of the present invention that bring the two into contact with each other. Note that the conventional temporary spring for holding down the wafer can be used in the method of the present invention as a contact for the connecting metal film. [Function] Conventionally, the problem was that the contact point of the plating bottle to the base film as the plating electrode film was wetted by the plating solution, so the method of the present invention removes the connection metal film connected to the base film from the wafer. By connecting the connecting metal film to the plating tIl on the back side of the wafer, which is not wetted by the plating solution, by making the plating solution contact only the front surface of the wafer during electrolytic plating, the plating current can be applied to the entire surface of the wafer, eliminating leakage of plating current. This is to uniformly lengthen the metal for bump electrodes. [Example] Hereinafter, an example of the present invention will be described with reference to FIG. Parts in the figure that correspond to those in Figure 2 described above are given the same reference numerals. FIG. 1(a) is an enlarged cross-section of the peripheral edge of a wafer 10 for a plurality of integrated circuit devices, which corresponds to FIG. It is preferable that the chamfer fee on the surface 10b side be larger than the chamfer 10c in the case of FIG. 2 (2), as shown, and that the slope of the chamfer 10d on the surface side be slightly gentler. As in the past, this wafer 10 was first covered with an oxide film 3, and then an electrode W14 connected to an integrated circuit was provided at a location on which a bump electrode was to be provided, and this was covered with a protective film 5 made of silicon nitride or the like. Afterwards, a window is opened on the electrode WA4, and a base film 6 of titanium or the like is deposited on the surface 10a of the wafer 10 by vapor deposition or spatter to make conductive contact with the electrode film 4 within this window. It adheres to a certain thickness. The periphery a6a of this base film 6 has a back side chamfer 10
It is usually deposited around 10n toward e. In the method of the present invention, the connecting metal film 7 is preferably deposited following the deposition with the base WA6 using the same material and method, but to a slightly thicker thickness, for example, around 0.5 nm.
During vapor deposition or sputtering, the peripheral edge 7a wraps around the side chamfer 10d of the wafer surface and is deposited as before, thereby connecting it to the base film 6 with very low contact resistance.
Next, in the same manner as in the past, copper, for example, is deposited on the entire surface of the wafer as the base film 8 on the bump electrode side to a thickness of 0.5 to 1 nm, and is removed by photo-etching, leaving only the areas where the bump electrodes are to be provided. Further, a photoresist film 9 is provided on the surface 10a side by a photo process so as to expose the base film 8. This FIG. 1(a) shows the state in which the preparation for electrolytic plating of the wafer 1o is completed, and the connecting metal M7 on the back surface 1Ob side is connected to the surface 10.
The surface 10a of the wafer 10 in contact with the plating solution and its chamfered portion 10d are securely connected to the base film 6 as the plating electrode film on the a side by the overlapping of the above-mentioned peripheral edges, and the surface 10a of the wafer 10 that contacts the plating solution and its chamfered portion 10d are the base film on the bump electrode side! I! All parts except 8 are covered with a photoresist film 9. Figure 1 shows the state of electrolytic plating. Plating jig 20
is equipped with a main body 21 having a funnel-shaped inner surface and a lid 25, and the wafer 10 is loaded into the main body 21 with the surface 10a facing downward, as in the conventional case.
The difference is that a is provided with supporting pins 23 for the wafer 10 at a plurality of locations, for example, three locations in the circumferential direction, and a small diameter gas introduction pipe 25b and a contactor 26 are provided at 125. The support pins 23 on the side of the main body 21 are made of an insulating material or a metal wire covered with an insulating material, and their tips serve to support the peripheral edge of the wafer 10 at a plurality of locations. The positive 8i22 is the same as the conventional one, but a platinum-plated titanium mesh is used for gold plating, and a perforated solder plate is used for solder plating. The contactor 26 on the lid 25 side may be the same leaf spring as the conventional one, but the wafer rich surface 1
Since it makes conductive contact with the connecting metal film 7 of 0b, it is desirable to plate it with platinum or the like. A small flow rate of nitrogen gas N or the like is introduced between the lid 25 and the wafer 10 from the gas introduction pipe 25b, and is allowed to leak slightly from the periphery of the wafer 10, thereby completely preventing wetting of the back surface 10b of the wafer by the plating solution. This can be prevented. During electrolytic plating, the wafer 10 is placed on the support pin 23 of the jig main body 21 in which the lower opening 2lb is fitted into the plating solution introduction pipe 41 of the plating PL 40, with its surface 10a facing downward, and the lid 25 is covered. By doing this, the contactor 26 is connected to the connection gold i film 7 on the back surface 10b of the wafer, and the wafer 10 is pressed against the support pin 23 for accurate positioning.
Next, the jet stream of the plating solution PL is brought into contact with the wafer surface 10a, and preferably with nitrogen gas N etc. introduced from the gas introduction pipe 25b, the lead 22a for the anode 22 and the contactor are connected to the positive and negative terminals of the plating $B30. Connect 26 and perform electrolytic plating. FIG. 1(C) shows the complete state of the wafer 10. After the bump electrodes 11 made of gold, solder, etc. are made to a certain length on the base film 8 by the above-mentioned electrolytic plating, the photoresist M9 shown in FIG. 1(a) is formed.
Then, using the base layer M8 and the bump t-electrode 11 as a mask, the base film 6 of the wafer surface TliflOa and the connection metal M7 between the vertical plane 10b are chemically etched to obtain the state shown in the figure. Connecting metal! If l7 is the same titanium film as base film 6, both films can be easily removed by simultaneous etching with a thin acid solution. In the above-described method of the present invention, the plating solution PL contacts only the surface 10a of the wafer 10, which is the target of electrolytic plating,
Connection gold II on the back side 10b! Since the connection point between the Wl47 and the contact 26 is not wetted by the plating liquid PL, there is no risk of leakage of plating current unlike in the conventional method, and this connection state is always kept stable during electrolytic plating to cover the entire surface of the wafer. The metal for the rebump electrode can be made uniformly long. By implementing the present invention, variations in the height of bump electrodes for all S-product circuit chips on the same wafer can be suppressed to ±10% or less, and the defect rate due to uneven height can be reduced from a few liters to 10 It can be reduced to one-fold. The method of the present invention is not limited to the embodiments described above, and the method of the present invention can be implemented in various ways. For example, various selections are possible depending on the type of electrolytic plating, as well as the materials for the connecting metal film and base film, and the structure of the electrolytic plating jig is a desirable example, but it is just an example. The present invention can be carried out using structures or structures that are variously modified depending on work conditions and needs. [Effects of the Invention] As is already clear from the above description, in the method of the present invention, when a bump electrode is formed on the surface of a wafer for an integrated circuit device by electrolytic plating using the underlying film as a plating electrode film, a bump electrode is formed on the back surface of the wafer. A connecting metal film is provided that is connected to the base film on the front surface, and electrolytic plating is performed with the front surface of the wafer facing down, allowing the plating solution to contact only that layer, and with the connecting metal film on the back side of the wafer being connected to the plating power source. By doing so, the base film as the Plating Electrolyte 8i film can be connected to the plating power supply via the connecting metal film connected to it on the back side of the wafer, which is not wetted by the plating solution. It completely prevents metal deposition and poor contact caused by leakage current, and allows the bump electrode metal to be made to have a uniform thickness over the entire wafer. The method of the present invention is particularly suitable for manufacturing integrated circuit devices in which a large number of small bump electrodes are provided, and can improve the reliability of the connection during mounting by making the height of the bump electrodes uniform. To carry out the present invention, it is necessary to add a step of depositing a connecting metal film on the back side of the wafer, but preferably this and a base film are subsequently deposited using the same material and the same method, so that it is substantially the same as in conventional methods. The connecting metal film can be provided in the same process as the conventional method, and both films can be removed in one step after electrolytic plating of the bump electrode. Furthermore, as in the embodiments, the present invention can be implemented by only slightly changing the structure of a conventional jet plating jig, for example, while taking advantage of the advantages of easy loading and unloading of wafers and easy control of plating conditions. This drawback can be overcome and the uniformity of plating thickness can be improved. In this way, the method of the present invention grows bump electrodes to a uniform height over the entire wafer surface while proceeding with electrolytic plating using substantially the same process and equipment as conventional methods, thereby reducing the defective rate due to uneven heights. As mentioned above, it can be applied to small flip-chip chips with a high degree of integration and a large number of bump electrodes, and can be particularly effective in increasing connection reliability during mounting.

【図面の簡単な説明】[Brief explanation of drawings]

第1図が本発明に関し、本発明方法によるバンプ電極用
金属の電解めっき前および完戒時のウェハの周縁部の拡
大断面図、ならびに電解めっきの要領を示すめっき治具
の断面図である.第2図以降は従来技術に関し、第2図
は従来方法によるバンブ電極用金属の電解めっき前のウ
ェハの周録部の拡大断面図および電解めっきの要領を示
すめっき治具の断面図、第3図はその問題点を示すウェ
ハの周縁部の拡大断面図である.図において、1:集積
回路装置用半導体基板、2:エビタキシャル層、3;酸
化膜、4:バンプt8iを設けるべき電極膜、5:保護
膜、6:めっき電極膜としての下地膜、6a:下地膜の
[縁部、7:接続金属膜、7a:接続金属膜の周縁部、
8:バンプ電極側下地膜、9:フォトレジストa、10
:集積回路装置用ウェハ、10a :ウェハの表面、l
Ob;ウェハの裏面、10c〜10e:ウェハ周縁の面
取り、lljバンブ電極、20:めっき治具、21:治
具の本体、21a:フランジ状部、21b二下部開口、
22:電解めっき用陽極、22a:陽極のリード、23
ニウエノ)支承ビン、24:従来のめつきピン、24a
:めっきピンの絶縁被覆、25:治具の蓋、25a+ガ
イド、25b=ガス導入管、26:接続金WAVAへの
接続用接触子、27:板ばね、30:めっき電源、40
:めっき槽、41:めっき液導入管、D:金属析出、N
:窒7冷廼譲潰 I0b[励 3 10ウIハ 第1図 〃ハ”;7瞥陽
FIG. 1 is an enlarged cross-sectional view of the periphery of a wafer before and after electrolytic plating of metal for bump electrodes according to the method of the present invention, and a cross-sectional view of a plating jig showing the steps of electrolytic plating. Figure 2 and subsequent figures relate to the prior art; Figure 2 is an enlarged cross-sectional view of the circumference of a wafer before electrolytic plating of bump electrode metal according to the conventional method, and a cross-sectional view of a plating jig showing the steps of electrolytic plating; This is an enlarged cross-sectional view of the wafer periphery showing the problem. In the figure, 1: semiconductor substrate for integrated circuit device, 2: epitaxial layer, 3: oxide film, 4: electrode film on which bump t8i is to be provided, 5: protective film, 6: base film as plating electrode film, 6a: [Edge of base film, 7: Connecting metal film, 7a: Periphery of connecting metal film,
8: Bump electrode side base film, 9: Photoresist a, 10
: Wafer for integrated circuit device, 10a : Surface of wafer, l
Ob; back surface of wafer, 10c to 10e: chamfering of wafer periphery, llj bump electrode, 20: plating jig, 21: main body of jig, 21a: flange-shaped portion, 21b two lower openings,
22: Electrolytic plating anode, 22a: Anode lead, 23
Niueno) Supporting pin, 24: Conventional pin, 24a
: Insulation coating of plating pin, 25: Jig lid, 25a + guide, 25b = gas introduction pipe, 26: Contact for connection to connecting metal WAVA, 27: Leaf spring, 30: Plating power supply, 40
: Plating tank, 41: Plating solution introduction pipe, D: Metal deposition, N
:Ni7 cold transfer I0b

Claims (1)

【特許請求の範囲】[Claims]  集積回路装置用ウェハの表面にバンプ電極をその下地
膜をめっき電極膜として電解めっきにより成長させる方
法であって、ウェハの裏面に表面の下地膜と接続された
接続金属膜を設け、ウェハの表面を下に向けてこの表面
のみにめっき液を接触させ、かつウェハの裏面の接続金
属膜をめっき電源に接続した状態で電解めっきを行なう
ことを特徴とする集積回路装置用バンプ電極の電解めっ
き方法。
This is a method of growing bump electrodes on the surface of a wafer for integrated circuit devices by electrolytic plating, using the base film as a plating electrode film. A method for electrolytic plating of bump electrodes for integrated circuit devices, characterized in that electrolytic plating is carried out with the wafer facing downward and in contact with a plating solution only on this surface, and with the connecting metal film on the back side of the wafer connected to a plating power source. .
JP18985289A 1989-07-21 1989-07-21 Electrolytic plating process of bump electrode for integrated circuit device Pending JPH0354829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18985289A JPH0354829A (en) 1989-07-21 1989-07-21 Electrolytic plating process of bump electrode for integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18985289A JPH0354829A (en) 1989-07-21 1989-07-21 Electrolytic plating process of bump electrode for integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0354829A true JPH0354829A (en) 1991-03-08

Family

ID=16248266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18985289A Pending JPH0354829A (en) 1989-07-21 1989-07-21 Electrolytic plating process of bump electrode for integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0354829A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452281B1 (en) 2001-01-29 2002-09-17 Sharp Kabushiki Kaisha Semiconductor integrated circuit and fabrication process therefor
US8586246B2 (en) 2008-09-01 2013-11-19 Sony Corporation Positive electrode active material, positive electrode using the same and non-aqueous electrolyte secondary battery
US8828606B2 (en) 2007-08-02 2014-09-09 Sony Corporation Positive electrode active material, positive electrode using the same and non-aqueous electrolyte secondary battery
USRE45310E1 (en) 2008-02-13 2014-12-30 Sony Corporation Cathode active material, cathode therewith and nonaqueous electrolyte secondary battery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63239844A (en) * 1987-03-26 1988-10-05 Nec Kansai Ltd Plating method for bump

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63239844A (en) * 1987-03-26 1988-10-05 Nec Kansai Ltd Plating method for bump

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452281B1 (en) 2001-01-29 2002-09-17 Sharp Kabushiki Kaisha Semiconductor integrated circuit and fabrication process therefor
US8828606B2 (en) 2007-08-02 2014-09-09 Sony Corporation Positive electrode active material, positive electrode using the same and non-aqueous electrolyte secondary battery
USRE45310E1 (en) 2008-02-13 2014-12-30 Sony Corporation Cathode active material, cathode therewith and nonaqueous electrolyte secondary battery
US8586246B2 (en) 2008-09-01 2013-11-19 Sony Corporation Positive electrode active material, positive electrode using the same and non-aqueous electrolyte secondary battery

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