JPH0193154A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0193154A JPH0193154A JP62250883A JP25088387A JPH0193154A JP H0193154 A JPH0193154 A JP H0193154A JP 62250883 A JP62250883 A JP 62250883A JP 25088387 A JP25088387 A JP 25088387A JP H0193154 A JPH0193154 A JP H0193154A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- insulating resin
- bump
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000009713 electroplating Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 abstract description 7
- 238000000206 photolithography Methods 0.000 abstract description 4
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 17
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 239000004809 Teflon Substances 0.000 description 6
- 229920006362 Teflon® Polymers 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は半導体装置の製造方法、特に電解メッキ法に
よりバンプ電極を形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming bump electrodes by electrolytic plating.
（従来の技術）
半導体装置の製造工程で、信号入出力用の電極としてバ
ンプと称する金属突起電極を電極パッドに形成する工程
がある。(Prior Art) In the manufacturing process of semiconductor devices, there is a process of forming metal protruding electrodes called bumps on electrode pads as signal input/output electrodes.
従来の半導体装置のバンプ電極形成工程について第２図
（ａ）ないしくｅ）の断面図を用いて説明する。第２図
（ａ）において拡散済みのシリコン基板１上にシリコン
酸化膜が形成され、その上にアルミ電極バッド２が形成
されている。そして、半導体素子上の全面にアルミ電極
バッド２上の部分を開孔した保護用のシリコン窒化膜か
らなる絶縁１１３が被覆されている。この基板の全面に
真空蒸着法またはスパッタリング法により金属膜４を形
成する。次に、第２図（ｂ）のようにドライフィルム（
感光性絶縁樹脂ｌ！Ｉ）５をホットラミネータでラミネ
ートし、アルミ電極パッド２の上部にのみ、所望の大き
さのバンプ径をパターニング開孔後、ベークする。この
ドライフィルム５をメッキマスクとして、金属膜４を電
解メッキの一方の電極（この場合は陰極）とする。その
際、金属膜４を電極とするため、第２図（Ｃ）のように
テフロン加工された電極ピン９でドライフィルム５を破
り、ウェハの所定の三点に電極ピン９を立てる。A conventional process for forming bump electrodes of a semiconductor device will be explained using cross-sectional views shown in FIGS. 2(a) to 2(e). In FIG. 2(a), a silicon oxide film is formed on a diffused silicon substrate 1, and an aluminum electrode pad 2 is formed thereon. The entire surface of the semiconductor element is covered with an insulation 113 made of a protective silicon nitride film with holes formed above the aluminum electrode pads 2. A metal film 4 is formed on the entire surface of this substrate by vacuum evaporation or sputtering. Next, as shown in Figure 2(b), dry film (
Photosensitive insulation resin! I) 5 is laminated with a hot laminator, and after patterning and opening a bump diameter of a desired size only on the upper part of the aluminum electrode pad 2, it is baked. This dry film 5 is used as a plating mask, and the metal film 4 is used as one electrode (in this case, a cathode) for electrolytic plating. At this time, in order to use the metal film 4 as an electrode, the dry film 5 is broken with a Teflon-treated electrode pin 9 as shown in FIG. 2(C), and the electrode pin 9 is erected at three predetermined points on the wafer.
そして、第２図（ｄ）のように電解メッキでアルミ電極
パッド２の上部にのみ、選択的にＡｕバンプ８を析出さ
せる。次にドライフィルム５の除去を行い、析出させた
Ａｕバンプ８をマスクとして電極パッド上部以外の金属
膜をエツチング除去する。Then, as shown in FIG. 2(d), Au bumps 8 are selectively deposited only on the upper part of the aluminum electrode pad 2 by electrolytic plating. Next, the dry film 5 is removed, and the metal film other than the upper part of the electrode pad is etched away using the deposited Au bumps 8 as a mask.
このようにして選択的にアルミ電極バッド２の上部に金
属膜２を介してＡｕバンプ８が形成される。しかし、こ
の製造工程には問題がある。ＡＵバンプ８析出時に電極
ピン９でフォトレジスト５を破くためにメッキ液が入り
込み、破いた所にも第２図（４Ｅｌ）のようにＡｕ１０
を析出させてしまう。In this way, Au bumps 8 are selectively formed on top of the aluminum electrode pads 2 with the metal film 2 interposed therebetween. However, there are problems with this manufacturing process. When the AU bump 8 is deposited, the electrode pin 9 breaks the photoresist 5, so the plating solution enters the photoresist 5, and Au10 is deposited in the broken area as shown in Figure 2 (4El).
will precipitate.
また、電極ピン９を何回か使用しているうちにテフロン
加工がはがれてしまうため、電極ピン９自体がＡ ｕ
ｉｏを析出させてしまう。そのたびに電極ピンは交換、
またはテフロンコーティングをしなければならず、経済
的にも好ましくない。また、こうして析出されたＡ ｕ
１０は本来ならばＡｕバンプ８の形成に使われるもの
である。工程上、バンプ形成は析出面積×高さに応じて
メッキ時の電流値と時間を決められているので他の部分
に析出したＡ ｕ １０の分だけＡｌｌバンプ８の高さ
は目標値よりも低めになってしまう。この結果、ウェハ
内及びウェハ間のＡｕバンプ８の高さにばらつきを招く
という問題がある。In addition, the Teflon coating peels off after the electrode pin 9 is used several times, so the electrode pin 9 itself becomes A u
io will be precipitated. Replace the electrode pin each time.
Alternatively, it must be coated with Teflon, which is not economically desirable. Moreover, the A u precipitated in this way
10 is originally used for forming the Au bumps 8. In the process, the current value and time during plating for bump formation are determined according to the deposition area x height, so the height of All bump 8 will be lower than the target value by the amount of A u 10 deposited on other parts. It becomes low. As a result, there is a problem in that the heights of the Au bumps 8 within a wafer and between wafers vary.
（発明が解決しようとする問題点）
従来の半導体装置におけるバンプ形成工程では、Ａｕ析
出時に電極ピンでドライフィルムを破くためにメッキ液
が入り込み、その破いた所にもＡｕが析出されてしまう
。また、電極ピンも何回か使用しているうちテフロン加
工がはがれてしまうために電極ピンそれ自体Ａｕが析出
する。よって、Ａｕバンプを形成する際、その析出する
ＡＵの分だけ形成する高さが低くなってしまう。この結
果、ウェハ内及びウェハ間のＡｕバンプの高さのばらつ
きを招くという問題があった。この発明は上記事情を解
決すべくなされたものであり、その目的は高さが均一な
バンプ電極を形成する半導体装置の製造方法を提供する
ことにある。(Problems to be Solved by the Invention) In a conventional bump forming process for a semiconductor device, when Au is deposited, the electrode pin tears the dry film, so a plating solution enters the film, and Au is deposited at the broken part as well. Further, after the electrode pin is used several times, the Teflon coating peels off, and thus Au is deposited on the electrode pin itself. Therefore, when forming an Au bump, the height of the bump is reduced by the amount of precipitated AU. As a result, there is a problem in that the height of the Au bumps varies within a wafer and between wafers. This invention was made to solve the above-mentioned situation, and its purpose is to provide a method for manufacturing a semiconductor device in which bump electrodes having a uniform height are formed.
［発明の構成］
（問題点を解決するための手段）
この発明の半導体装置の製造方法は、半導体基板の全面
に金属薄膜を形成する工程と、バンプ電極形成領域に開
口部を有する感光性絶縁樹脂膜を上記金属薄膜上に被着
する工程と、先端部を除いて絶縁性樹脂によって覆われ
た電極ピンを上記感光性絶縁樹脂膜を突き破って上記金
属膜に接触させ、絶縁性樹脂と感光性絶縁樹脂膜とを密
着させた状態で上記金属膜を所定電位に設定する工程と
、電解メッキ法により上記開口部から露出したバンプ電
極形成領域の表面にバンプ電極材料を選択的に析出させ
てバンプ電極を形成する工程とからなる。[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of forming a metal thin film on the entire surface of a semiconductor substrate, and a step of forming a photosensitive insulator having an opening in a bump electrode formation region. A step of depositing a resin film on the metal thin film, and an electrode pin covered with an insulating resin except for the tip part is brought into contact with the metal film by breaking through the photosensitive insulating resin film, and the electrode pin is coated with the insulating resin and photosensitive. a step of setting the metal film to a predetermined potential while in close contact with a conductive insulating resin film, and selectively depositing bump electrode material on the surface of the bump electrode formation region exposed from the opening by electrolytic plating. The method includes a step of forming bump electrodes.
（作用）
金属膜と接触させる電極ピンを絶縁性樹脂で覆い、絶縁
性樹脂と感光性絶縁樹脂膜を密着させてメッキ液の侵入
を防ぐ。そして、電極ピン自体のバンプ電極形成材料の
析出、及び電極ピンを金属膜とを接触させるために破い
た感光性絶縁樹脂膜の場所にバンプ電極形成材料が析出
されるのを防止する。よって、電極ピンの交換、または
テフロンコーティングの必要がなく、高さが均一なバン
プ電極を形成することができる。(Function) The electrode pin that comes into contact with the metal film is covered with an insulating resin, and the insulating resin and photosensitive insulating resin film are brought into close contact to prevent intrusion of the plating solution. This prevents the bump electrode forming material from being deposited on the electrode pin itself and at the location of the photosensitive insulating resin film that has been torn in order to bring the electrode pin into contact with the metal film. Therefore, there is no need to replace the electrode pins or coat the electrode with Teflon, and it is possible to form a bump electrode with a uniform height.
（実施例）
以下、図面を参照してこの発明の一実施例について詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ）ないしく媛）はこの発明に係る半導体装置
の製造工程を示す断面図である。まず、第１図（ａ）に
示すよ）にトランジスタ、ダイオード等の素子が形成さ
れた半導体基板１上に選択的にアルミ電極バッド２を形
成する。このアルミ電極パッド２上を含む半導体基板１
の全面にシリコン窒化膜からなる絶縁１１３を被覆し、
ホトリソグラフィ技術を用いてアルミ電Ｉ！ｉ２上を開
孔する。FIGS. 1(a) to 1(a) are cross-sectional views showing the manufacturing process of a semiconductor device according to the present invention. First, as shown in FIG. 1(a), aluminum electrode pads 2 are selectively formed on a semiconductor substrate 1 on which elements such as transistors and diodes are formed. Semiconductor substrate 1 including the top of this aluminum electrode pad 2
The entire surface is covered with an insulation 113 made of a silicon nitride film,
Aluminum electric I! using photolithography technology! Drill a hole on i2.
この絶縁膜３は半導体基板１に形成された回路素子のパ
ッシベーション膜として作用する。なお、このパッシベ
ーション膜はシリコン窒化膜に限定されない。つづいて
開孔部を含む全面にスパッタリング法または真空蒸着法
によりｐｔ、 Ｔｉ等からなる金属膜４を形成する。次
に、第１図（ｂ）に示すようにドライフィルム（感光性
絶縁樹脂膜）５をコーティングし、ホトリソグラフィ工
程を用いてドライフィルム５を開孔する。そして、第１
図（Ｃ）のような絶縁性樹脂（Ａｕの場合シリコン樹脂
）６に先端部を除いて埋め込まれた電極ピン７を用いて
第１図（ｄ）のようにドライフィルム５に密着させる。This insulating film 3 acts as a passivation film for circuit elements formed on the semiconductor substrate 1. Note that this passivation film is not limited to a silicon nitride film. Subsequently, a metal film 4 made of PT, Ti, etc. is formed on the entire surface including the openings by sputtering or vacuum evaporation. Next, as shown in FIG. 1(b), a dry film (photosensitive insulating resin film) 5 is coated, and holes are formed in the dry film 5 using a photolithography process. And the first
Using an electrode pin 7 embedded in an insulating resin (silicon resin in the case of Au) 6 except for the tip as shown in FIG. 1(C), it is brought into close contact with the dry film 5 as shown in FIG. 1(d).
これにより電極ピン７が約２０ｐｎ下の金Ｂ膜４に到達
する。電極ピン７と接触した金属１ｉ１４は電解メッキ
を行う一際の一方の電極として働き、電極バッド２の上
部にのみ選択的に高さが均一なＡｕバンプ８が形成され
る。次にドライフィルム５を除去し、析出させたＡｕバ
ンプ８をマスクとしてアルミ電極バッド２の上部以外の
金ｍｉＩをエツチング除去する。このようにして、第１
図（ｅ）に示すようなアルミ電極バッド２の上部に金属
！Ｉ３を介して高さが均一なＡＬＪバンプ８が形成され
る。As a result, the electrode pin 7 reaches the gold B film 4 approximately 20 pn below. The metal 1i14 in contact with the electrode pin 7 acts as one electrode during electrolytic plating, and Au bumps 8 having a uniform height are selectively formed only on the upper part of the electrode pad 2. Next, the dry film 5 is removed, and the gold miI other than the upper part of the aluminum electrode pad 2 is etched away using the deposited Au bump 8 as a mask. In this way, the first
Metal! on the top of the aluminum electrode pad 2 as shown in Figure (e)! ALJ bumps 8 having a uniform height are formed via I3.
このように、電極ピン７を金属膜４と接触させる電解メ
ッキ時、電極ピン７を絶縁性樹脂６で覆うことによって
、ドライフィルム５を破った際に絶縁性樹脂６とドライ
フィルム５が密着しているためメッキ液の侵入を防止で
きる。そして、電極ピン７自体、及び破いたドライフィ
ルム５の場所におけるＡＵ析出がなくなる。In this way, by covering the electrode pin 7 with the insulating resin 6 during electrolytic plating in which the electrode pin 7 is brought into contact with the metal film 4, the insulating resin 6 and the dry film 5 are in close contact with each other when the dry film 5 is torn. This prevents the plating solution from entering. Then, AU precipitation on the electrode pin 7 itself and at the location of the torn dry film 5 is eliminated.
なお、ドライフィルム５の代わりに７オトレジストを使
っても良く、バンプ電極形成材料としてもＡＬＪに限ら
ずＡＱ等いろいろな材料に実施できる。このような製造
方法にすれば電極ピンの交換、またはテフロンコーティ
ングの必要がなく、経済的にも優れ、高さが均一なバン
プ電極を形成することができる。Incidentally, 7 photoresist may be used instead of the dry film 5, and the material for forming the bump electrodes is not limited to ALJ but can be applied to various materials such as AQ. This manufacturing method eliminates the need for replacing electrode pins or Teflon coating, is economical, and allows formation of bump electrodes with uniform height.
［発明の効果］
以上詳述したようにこの発明によれば、高さが均一なバ
ンプ電極を形成することができ、経済的にも優れ、作業
性を高める半導体製造方法を提供することができる。[Effects of the Invention] As detailed above, according to the present invention, it is possible to form a bump electrode with a uniform height, and it is possible to provide a semiconductor manufacturing method that is economically superior and improves workability. .
第１図（ａ）ないしくｅ）はこの発明の一実施例に係る
Ａｕバンプ形成の製造方法の主要な工程を示す断面図、
第２図（ａ）ないしくｅ）は従来におけるＡＬＩバンプ
形成の製造方法の主要な工程を示す断面図である。
１・・・半導体基板、２・・・アルミ電極、３・・・絶
縁膜、４・・・金属膜、５・・・ドライフィルム（感光
性絶縁樹脂１１１）、６・・・絶縁性樹脂、７・・・電
極ピン、８・・・Ａｕバンプ。
出願人代理人 弁理士 鈴江武彦
箪１ 図FIGS. 1(a) to 1e) are cross-sectional views showing the main steps of a manufacturing method for forming Au bumps according to an embodiment of the present invention,
FIGS. 2(a) to 2(e) are cross-sectional views showing the main steps of a conventional manufacturing method for forming ALI bumps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Aluminum electrode, 3... Insulating film, 4... Metal film, 5... Dry film (photosensitive insulating resin 111), 6... Insulating resin, 7... Electrode pin, 8... Au bump. Applicant's agent Patent attorney Takehiko Suzue 1 Figure
Claims (1)
を上記金属薄膜上に被着する工程と、先端部を除いて絶
縁性樹脂部材によって覆われた電極ピンを上記感光性絶
縁樹脂膜を突き破って上記金属膜に接触させ、絶縁性樹
脂と感光性絶縁樹脂膜とを密着させた状態で上記金属膜
を所定電位に設定する工程と、 電解メッキ法により上記開口部から露出したバンプ電極
形成領域の表面にバンプ電極材料を選択的に析出させて
バンプ電極を形成する工程とからなる半導体装置の製造
方法。[Claims] A step of forming a metal thin film on the entire surface of a semiconductor substrate, a step of depositing a photosensitive insulating resin film having an opening in a bump electrode formation region on the metal thin film, and a step of depositing a photosensitive insulating resin film on the metal thin film except for the tip portion. An electrode pin covered with an insulating resin member is brought into contact with the metal film by breaking through the photosensitive insulating resin film, and the metal film is brought to a predetermined potential with the insulating resin and the photosensitive insulating resin film in close contact with each other. A method for manufacturing a semiconductor device comprising: a step of setting the bump electrode; and a step of forming a bump electrode by selectively depositing a bump electrode material on the surface of the bump electrode formation region exposed from the opening by electrolytic plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62250883A JPH0193154A (en) | 1987-10-05 | 1987-10-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62250883A JPH0193154A (en) | 1987-10-05 | 1987-10-05 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0193154A true JPH0193154A (en) | 1989-04-12 |
| JPH0519304B2 JPH0519304B2 (en) | 1993-03-16 |
Family
ID=17214435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62250883A Granted JPH0193154A (en) | 1987-10-05 | 1987-10-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193154A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0215622A (en) * | 1988-07-01 | 1990-01-19 | Fujitsu Ltd | Plating treatment and plating treatment device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0651207U (en) * | 1992-12-25 | 1994-07-12 | 厚木ナイロン工業株式会社 | Foot cover |
-
1987
- 1987-10-05 JP JP62250883A patent/JPH0193154A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0215622A (en) * | 1988-07-01 | 1990-01-19 | Fujitsu Ltd | Plating treatment and plating treatment device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0519304B2 (en) | 1993-03-16 |
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