CN102738071B - For filling the method and apparatus of interconnection structure - Google Patents

Abstract

Present application is related to the method and apparatus for filling interconnection structure.The present invention is provided to deposit the method, equipment and system of copper and other metals.In some embodiments, wafer substrates are provided to equipment.The wafer substrates have the surface with some field areas and a feature.Layers of copper is plated on the surface of the wafer substrates.The layers of copper is annealed so that copper is redistributed to the feature from some regions of the wafer substrates.The embodiment of disclosed method, equipment and system allows the bottom-up filling of tight to the feature in wafer substrates.

Description

For filling the method and apparatus of interconnection structure

CROSS REFERENCE TO RELATED refers to

Present application advocates the priority of following application case：No. 13/108,894 to file an application on May 16th, 2011 No. 13/108,881 U.S. patent application case and in April, 2011 that U.S. patent application case, on May 16th, 2011 file an application No. 61/476,091 U.S. provisional patent application cases filed an application for 15th；All three application cases are by reference simultaneously Enter herein.

Technical field

The present invention relates to semiconductor processing techniques, in particular, are related to a kind of method for filling interconnection structure and set It is standby.

Background technology

Damascene process (semiconductor processing techniques) can be used to form interconnection on the integrated.Damascene process, which is related to, to be formed Embedded metal wire is formed in groove and via hole in dielectric layer.In typical mosaic technology, served as a contrast in semiconductor wafer The pattern of groove and via hole is etched in the dielectric layer at bottom.Then, (for example) physical vapour deposition (PVD) (PVD) technique is passed through Double-deck barrier layer of such as tantalum (Ta), tantalum nitride (TaN) or TaN/Ta is deposited in wafer surface.Then, usually using electricity Depositing process fills the groove and via hole with copper.Due to plating usually require occur on the electrically conductive, therefore can first by Chemical vapor deposition (CVD) or the PVD copper seed crystal layer on barrier layer.Then, copper can be electroplated onto to the copper seed crystal On layer.

The content of the invention

The present invention is provided to the method for plating coating copper and other metals, equipment and system.It is described according to various embodiments Method, which is related to, is plated to layers of copper in wafer substrates.The layers of copper can be annealed, this can make some regions of the copper from wafer substrates Some features being redistributed in wafer substrates.In some cases, plating and subsequent anneal serve as multi-cycle depositing operation One circulation.Therefore, the depositing operation can relate to two or more plating/anneal cycles continuously performed.

In some embodiments, a kind of method, which includes, provides wafer substrates to equipment.The wafer substrates include tool There is the surface of some field areas and a feature.Layers of copper is plated on the surface of the wafer substrates.Then by the copper Layer annealing, wherein the annealing makes copper be redistributed to the feature from some regions of the wafer substrates.

In some embodiments, the surface of the chip is further comprising the field areas and feature top Backing layer.In some embodiments, the backing layer can be annealed in reducing atmosphere before layers of copper described in plating.Can Institute is selected from the group being made up of ruthenium (Ru), cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), golden (Au) and rhodium (Rh) State backing layer.

In some embodiments, a kind of method, which includes, provides wafer substrates to equipment.The wafer substrates, which include, to be covered The surface of backing layer is stamped, the surface includes some field areas and a feature.Layers of copper is plated to by electroplating technology described On the surface of wafer substrates.Then the layers of copper is annealed, wherein the annealing makes copper from some of the wafer substrates Region is redistributed to the feature.Can be performed in reducing atmosphere at a temperature of about 150 DEG C to 400 DEG C the annealing of about The duration of 30 seconds to 180 seconds.

In some embodiments, a kind of equipment includes plating chamber, wafer substrates retainer, element and controller.It is described Plating chamber is configured to keep electrolyte.The wafer substrates retainer is configured to wafer substrates being held in the plating chamber In.The wafer substrates include the surface with some fringe regions, some field areas and a feature.

The element includes ion resistance main body, and there are some perforation to cause the perforation not in the master in the main body Communicating passage is formed in vivo.The perforation allows to convey the electrolyte via the element.The element is located to have Towards the surface on the surface of the wafer substrates, wherein when the wafer substrates are kept by the wafer substrates retainer When, the surface of the element is located in about 10 millimeters of the surface away from the wafer substrates.The ion resistance main body In the substantially all openings of the perforation on the surface towards the surface of the wafer substrates of the element Major dimension with no more than about 5 millimeters.The porosity of the element is about 1% to 3%.

The controller includes the instruction for being used for carrying out a technique.The technique includes：Using the plating chamber by layers of copper It is plated on the surface of the wafer substrates；And the layers of copper is annealed.Layers of copper annealing is made into copper from the chip Some regions of substrate are redistributed to the feature.

In some embodiments, a kind of nonvolatile computer machine readable media includes refers to for the program of control device Order.Described program instruction includes the code of the operation to contain the following：Wafer substrates are transported to and the equipment phase The module of association；Layers of copper is plated on the surface of the wafer substrates；And the layers of copper is annealed.The wafer substrates Include the surface with some field areas and a feature.Layers of copper annealing is made into copper from some regions of wafer substrates weight Newly it is distributed to the feature.

These and other of the embodiment of the subject matter described in this specification is illustrated in accompanying drawing and in being described below Aspect.

Brief description of the drawings

Fig. 1 displayings illustrate the example of the flow chart of the technique for plating coating copper.

The example of the cross section schematic illustration in the stage in the method for Fig. 2A and 2B displaying plating coating coppers.

Fig. 3 displayings illustrate the example of the flow chart of the technique for plating coating copper.

Fig. 4 A to 4G show the example of the schematic diagram of electric fill system.

The example of the cross-sectional view of Fig. 5 displaying electroplating devices.

Fig. 6 A and 6B show the example of the view of one-dimensional resistive element.

Embodiment

Introduction

In the following detailed description, numerous particulars are illustrated to provide thorough understanding of the present invention.However, As it will be apparent to those skilled in the art that, can be in the case of without these specific details or by using alternative elements or technique To put into practice the present invention.In other examples, well-known technique, program and component are not described in detail so as not to understand unnecessarily Obscure the aspect of the present invention.

In this application, term " semiconductor wafer ", " chip ", " substrate ", " wafer substrates " and " partially fabricated Integrated circuit " is interchangeably used.Those skilled in the art will appreciate that term " integrated circuit of partially fabricated " can refer to Silicon wafer of the generation during any one of many stages of integrated circuit are made thereon.Disclosed operation can be performed to it Workpiece can have variously-shaped, size and material.In addition to semiconductor wafers, example is also included using other workpiece of the present invention The various objects of such as printed circuit board (PCB).

Current techniques for metallized integrated circuit include via physical vapour deposition (PVD) (PVD) process deposits barrier layer and Backing layer, sowed with the copper (Cu) deposited via PVD to the backing layer and then use offer tight bottom-up The technique electro-coppering of filling.However, electroplating technology is not easy to extend below about 18 nanometers of feature sizes.In these sizes Under, small feature opening can due to barrier layer and backing layer coating and (for example) is reduced to about 2 before electroplating technology Nanometer is to 4 nanometers.This causes the feature to turn into the feature of very high aspect ratio, and it may not allow by some electroplating technologies Carry out void-free bottom-up filling.

Embodiment disclosed herein can by sequentially plating layers of copper and make copper redistribute it is very small to fill Feature fills the difficulty of the feature to overcome.The big I of this little feature is below about 100 nanometers and it has high aspect ratio.This Disclosed in text to fill the embodiment of the method and apparatus for the small integrated circuit feature that can be coated with potential barrier/backing layer. In some embodiments, technological operation available copper is filled up completely with the feature.In addition, embodiment disclosed in some without using By the copper seed layer of physical vapour deposition (PVD) (PVD) process deposits.

In some embodiments, layers of copper is directly plated on the backing layer of wafer substrates.For example, the lining Layer can be layer of ruthenium or other suitable conductive barrier metal levels.So then plated layers of copper can be annealed.In some embodiments In, the annealing can be carried out about 30 seconds to 180 seconds in reducing atmosphere (such as forming gas) at about 150 DEG C to 400 DEG C.Institute Stating annealing can be such that the copper in layers of copper is redistributed in small feature.The annealing can also make the layers of copper and backing layer it is any with Exposed region is maintained in reducing condition afterwards.Repeatable copper plating and annealing process about 2 times to 8 times, so as to gradually and without sky Small feature is filled in unoccupied place, such as width or a diameter of feature from about 8 nanometers to 100 nanometers.In some embodiments, it is each The thickness of plated layers of copper can be about 2 nanometers to 20 nanometers, and this depends on feature sizes and aspect ratio.Can be then using conventional electricity Depositing process plating wafer substrates are to fill larger feature before the chemical-mechanical planarization (CMP).

In some embodiments, aid in being mitigated or eliminated in plating layers of copper using resistive element in electroplating device " end effect ".End effect can increase the Waffer edge with the greater than about wafer surface of the sheet resistance of 1 ohm-sq Neighbouring plating thickness, this is unacceptable.In some embodiments, resistive element includes several of close chip Through isolating and being not connected with through hole, the overall resistance of electroplating device is dominated whereby.

Method

Fig. 1 displayings illustrate the example of the flow chart of the technique for plating coating copper.At the frame 102 of method 100, there is provided Wafer substrates.The wafer substrates can include a feature and some field areas.The feature can have the width or diameter of change And aspect ratio.The aspect ratio of feature for the feature vertical sidewall height and the feature width ratio.

For example, the width of feature or diameter can be about 100 nanometers, about 90 nanometers, about 60 nanometers, about 30 nanometers, about 18 nanometers, about 15 nanometers, about 12 nanometers, about 8 nanometers, less than about 100 nanometers or less than about 18 nanometers.For with larger width Feature, for deposit copper other techniques may ratio method 100 embodiment it is more rapidly and more efficient.However, method 100 Available for the part or a part that this larger width characteristics is filled with copper.

In some embodiments, the wafer substrates can be to have undergone the wafer substrates of damascene process, and the chip Feature in substrate can be the line feature or conducting hole characteristic etched in the dielectric layer.For example, lose in the dielectric layer The aspect ratio of the feature at quarter can be about 10: 1 or bigger.In some embodiments, the dielectric layer can covered with barrier layer, And the barrier layer can be covered with backing layer.In other embodiments, potential barrier and lining can be a kind of single layer of material. That is backing layer can show barrier layer property so that not need single barrier layer and backing layer.For example, covering The aspect ratio for having the feature etched in the dielectric layer of potential barrier/backing layer can be about 12: 1 about 15: 1 or greater than about 12: 1.At it In its embodiment, the feature can be the contact via hole with about 15: 1 about 20: 1 or greater than about 15: 1 aspect ratio.

For example, the dielectric layer can be covered with tantalum nitride (TaN) barrier layer.The thickness of TaN barrier layers can be about 2 Nanometer.TaN barrier layers can be deposited by physical vapour deposition (PVD) (PVD) technique or chemical vapor deposition (CVD) technique.Other In embodiment, for example, the barrier layer can be tantalum (Ta), tungsten (W), tungsten nitride (WN), titanium (Ti) or titanium nitride (TiN).The barrier layer can be covered with ruthenium (Ru) backing layer.The thickness of Ru backing layers can be about 2 nanometers.Can be by CVD techniques To deposit Ru backing layers.In other embodiments, for example, the backing layer can be cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), golden (Au) or rhodium (Rh).

In some embodiments, the backing layer is selected so that copper soaks the backing layer.Soak and maintained for liquid The ability of contact with the surface of solids.The liquid of the wetting surface of solids crosses over the surface distribution.The liquid of the nonwetting surface of solids Body forms droplet or spheroid on said surface so that the contact with the surface minimizes.The liquid contacted with the surface of solids Wetness degree is determined by adhesion (that is, the power between liquid and solid) and cohesive force (that is, the power in liquid).For example, Oxidation behavior based on metal, the metal of copper wetting include Ru, Pt, Pd, Au and Rh.

At frame 104, the backing layer on the surface of substrate is annealed.In some embodiments, can be in reducing atmosphere Any natural oxide that backing layer is annealed to remove pollutant or reduce metal.For example, pollutant can include absorption To the carbon on the surface of backing layer.Shape in shikishima plating process described below can be aided in by removing pollutant or reducing natural oxide Into continuous layers of copper.

In some embodiments, reducing atmosphere includes and forms gas, atomic hydrogen or other chemical reducing agents.Form gas For mixture of the hydrogen (hydrogen mole fraction is variable) with nitrogen.In some embodiments, can be at about 150 DEG C to 400 DEG C It is lower that backing layer is annealed of about 30 seconds to 180 seconds.For example, backing layer can annealed at about 225 DEG C in forming gas Of about 90 seconds.In other embodiments, backing layer can be handled under other reducing conditions (such as hydrogen plasma or atomic hydrogen).

At frame 106, the plating layers of copper on backing layer.In some embodiments, by electroplating technology plating layers of copper, and In other embodiments, by electroless plating plating layers of copper.In some embodiments, can be (that is, about 20 DEG C in about room temperature To 29 DEG C or about 25.C the plating process in frame 106 is performed under).

In some embodiments, the thickness of plated layers of copper can be the width of feature or the pact of diameter in wafer substrates 20% to 80%.For example, the thickness of the layers of copper can be about 2 nanometers to 20 nanometers or about 2 nanometers to 10 nanometers.At some In embodiment, there is the layers of copper thickness to exist enough copper to be moved back by each at frame 110 described below About 10% to the 50% of fire operation filling feature.In some embodiments, the layers of copper can be both in the feature of wafer substrates Backing layer on form approximate conformal layer on backing layer in field areas again.

In some embodiments, plated layers of copper can be continuous layers of copper.That is, the layers of copper can be in backing layer Top forms pantostrat.In other embodiments, copper can be discontinuous.That is, some regions of backing layer may Not covered with layers of copper.For example, layers of copper can cover backing layer except above a part for the field areas of wafer substrates Backing layer outside region.

In some embodiments, layers of copper can show a certain preferred growth in feature, and in other embodiments, copper Layer can show the slightly slow growth in feature.

In some embodiments, layers of copper can include alloying element；That is, can on backing layer plated copper alloys layer.Alloy Element can have about 50 to 210 atomic mass.For example, alloying element can be chromium, iron, cobalt, nickel, zinc, ruthenium, rhodium, palladium, Silver, indium, tin, tellurium, platinum, gold or lead.One of these alloying elements or one or more of can be included in layers of copper.In some embodiment party In case, layers of copper includes about 0.1 weight % to 5 weight % one or some alloying element.As explained below, alloying element can carry For resisting a certain protection damaged as caused by electromigration.

As described above, in some embodiments, can be by electroplating technology plating layers of copper.In some embodiments, Electroplating solution and hardware can allow uniform across the chip deposition of copper.For example, electroplating solution can be that the height of dilution is compound Copper electroplating solution.By this little electroplating solution, copper nucleation can be uniformly and continuous in resistance wafer substrates.The height of dilution Compound copper electroplating solution is further described in No. 7,799,684 United States Patent (USP) being incorporated herein by reference. Electroplating solution, which can also include, can strengthen the plating rates in smaller feature to aid in filling the additive of these features, such as polymerize Thing.

It is described in by other methods of electroplating technology deposition copper in following application case：It is entitled " to be used for coated with ruthenium Chip on carry out two step copper electroplating technology (the TWO STEP with annealing of uniformly across chip deposition and voidless filled COPPER ELECTROPLATING PROCESS WITH ANNEAL FOR UNIFORM ACROSS WAFER DEPOSITION AND VOID FREE FILLING ON RUTHENIUM COATED WAFERS) " and filed an application on March 6th, 2008 12/075th, No. 023 U.S. patent application case, and it is entitled " be used for carried out on the chip coated with semi-precious metal uniformly across Chip deposits and copper electroplating technology (the COPPER ELECTROPLATING PROCESS FOR UNIFORM of voidless filled ACROSS WAFER DEPOSITION AND VOID FREE FILLING ON SEMI-NOBLE METAL COATED WAFERS the 12/785th, No. 205 U.S. patent application case) " and on May 21st, 2010 filed an application, the application case two Person is incorporated herein by reference.The equipment for electro-coppering is discussed further below.

As described above, in some embodiments, can be by electroless plating plating coating copper.In some cases, can be Electroless plating (also referred to as chemistry or autocatalysis plating) is performed in the case of without using external power.By electroless plating, have When the end effect that is present in electroplating technology be not present due to electric current not being delivered into wafer substrates from external source.At some In embodiment, layers of copper uniformity is more easily realized by electroless plating.Electroless plating and equipment are further described in 6th, 664, No. 122, the 6th, 815, No. 349, the 7th, 456, No. 102, in the 7th, 897, No. 198 United States Patent (USP), it is all these specially Profit is incorporated herein by reference.

At frame 108, rinse and dry wafer substrates.In some embodiments, can be at spin rinse drier (SRD) It is middle to rinse and dry wafer substrates.Processes and apparatus for rinsing and drying wafer substrates is further described in the side with reference In No. 7,033,465 United States Patent (USP) that formula is incorporated herein.

At frame 110, layers of copper is annealed so that copper is redistributed to the feature from some regions of wafer substrates.It is brilliant The region of piece substrate can include some field areas.In some embodiments, copper divides again from the field areas of wafer substrates Cloth is to the feature.In some embodiments, copper is redistributed to the bottom of feature from some regions of wafer substrates.One In a little embodiments, layers of copper is annealed of about 30 seconds to 180 seconds at about 150 DEG C to 400 DEG C.In some embodiments, may be used Annealing is performed under reducing atmosphere.The reducing atmosphere can be the oxygen for making backing layer be maintained in oxide-free state and preventing copper Any reducing atmosphere changed.For example, in some embodiments, reducing atmosphere includes and forms gas, atomic hydrogen or other Chemical reducing agent.

Heating layers of copper can be realized to be annealed by many different technologies.For example, can be by passing through electric current Layers of copper heats the layers of copper (that is, resistance heating).Layers of copper can also be heated by ultraviolet (UV) light or infrared (IR) light.One In a little embodiments, wafer substrates can constantly or be periodically heated during process cycles.

In some embodiments, the copper that layers of copper annealing causes plating to spread in feature is redistributed to the base of the feature Bottom.For example, the copper being plated on the side of feature can be redistributed to the bottom of the feature.In some cases, will Plated copper is drawn into feature from the field areas of wafer substrates.

Although being not intended to be limited to any theory, the redistribution for believing substrate of the copper to feature and to feature is capillary The result of tube effect.For example, if feature is fully small, then the surface tension (it is caused by the cohesive force in copper) of copper and The adhesion between backing layer in copper and feature can be acted on so that copper is drawn into the substrate of feature.

At frame 112, whether the aspect ratio for determining feature is sufficient.If the aspect ratio of feature is sufficient, then Method 100 terminates.If the aspect ratio of feature is inadequate, then repeats 106 to 110 untill aspect ratio abundance. In some embodiments, 106 to 110 about 2 times are repeated to 8 times.In some embodiments, the thickness of plated layers of copper with And annealing temperature and duration can be directed to the process sequence of operation 106 to 110 and change, but in general plated layers of copper Thickness is about 2 nanometers to 20 nanometers and annealing temperature is about 150 DEG C to 400 DEG C, lasts about 30 seconds to 180 seconds.

The sufficient aspect ratio of feature can be following aspect ratio：For the aspect ratio, can not formed in feature it is any Body layer electroplating technology is performed in the case of space.For example, the sufficient aspect ratio of feature can be about 2: 1 or smaller, about 2: 1 or About 1: 1.If perform body in the case where wafer substrates have high aspect ratio features before the embodiment of execution method 100 Layer electroplating technology, then copper metal may be plated in wafer substrates so that the opening of feature, which blocks, copper, and tamper Lower section has space.

After the feature in wafer substrates is filled into sufficient aspect ratio with copper, body electroplating technology copper body layer can be used Plating wafer substrates.In some embodiments, copper body layer can have about 0.2 nanometer to 0.5 nanometer of thickness.Electroplated by body Copper body layer is plated in wafer substrates by technique to improve plated film pattern before chemical-mechanical planarization (CMP).Chip The subsequent treatment of substrate after cmp follows standard Damascene technological process known to those skilled in the art.

Therefore, the embodiment of method 100 is used to fill feature with copper, so that it is guaranteed that the bottom-up of the feature is filled out Fill so that do not form space.In some embodiments, the operation 106 to 110 of method 100 is repeated, until feature is filled Untill.Or the operation 106 to 110 of repeatable method 100, until feature being filled into copper so that space can not formed In the case of perform body electroplating technology level.

In some embodiments, make to want copper level and technique behaviour in repeat block 106 to 110 to reach in feature The number of work minimizes.For example, feature can be reached by 2 times of the technological operation in frame 106 to 110 or 3 repetitions In want copper level.For example, can by frame 106 plating there is the layers of copper of optimal thickness to make the weight of technological operation Again number minimizes.Layers of copper should not be too thick, because if layers of copper is too thick, then characterized openings can be blocked up by copper in plating process Plug.However, plated layers of copper is thicker, more copper is just had in frame on some regions of wafer substrates (including field areas) The feature is redistributed to during annealing in 110.Therefore, plating thick copper layer can be redistributed to the copper of feature in offer Aspect is useful, but layers of copper should not be thick to so that it blocks the feature.

For example, wafer substrates can include 20 nanofeatures.In frame 106, can the nanometer thickness of plating about 5 layers of copper, it The flushing in frame 108 and the annealing in dry and frame 110 are carried out afterwards.Can be by 2 times or 3 repetition copper of operation 106 to 110 Feature is filled into proper level.

In some embodiments, the shikishima plating process in frame 106 can be performed at high temperature.For example, it can be used and use The electroplating solution of higher solvent performs electroplating technology at a temperature of the boiling point more than water., can be about as another example Electroless plating is performed at a temperature of 50 DEG C to 90 DEG C.In some embodiments, performing shikishima plating process at high temperature can plate Copper is set to be redistributed to feature at least in part during applying technique.

The example of the cross section schematic illustration in the stage in the method for Fig. 2A and 2B displaying plating coating coppers.In Fig. 2A In, 200 illustrate the wafer substrates with feature 204 and field areas 206.Layers of copper 202 is plated to the wafer substrates On, in frame 106 in Fig. 1.220 illustrate wafer substrates after an anneal process, such as in Fig. 1 frame 110.Such as Shown in 220, layers of copper 202 is redistributed to the bottom of feature 204, wherein the not residual copper in field areas 206.

In Fig. 2 B similar to Fig. 2A, 200 illustrate the wafer substrates with feature 204 and field areas 206.Will Layers of copper 202 is plated in the wafer substrates, in frame 106 in Fig. 1.240 illustrate the chip after annealing process Substrate, such as in Fig. 1 frame 110.As shown in 240, layers of copper 202 is set to be redistributed to the bottom of feature 204, wherein Some remaining copper in field areas 206 and in the side wall of feature 204.The difference of the amount of copper redistribution (is included in field areas Whether residual copper) be attributable to the different chips backing material that (for example) annealing time, annealing temperature or copper deposit to.

Fig. 3 displayings illustrate the example of the flow chart of the technique for plating coating copper.The class of method 250 demonstrated in Figure 3 Method 100 demonstrated in Figure 1 is similar to, wherein the additional plating cap layer in method 250.

At the frame 260 of method 250, after it is determined that whether the aspect ratio of feature is sufficient, cap layer is plated to layers of copper On.For example, the cap layer can include the layers of copper (that is, copper alloy layer) with alloying element.The copper alloying element can Include any one of alloying element described above.Copper alloying element can aid in reducing the electromigration of copper, this increase semiconductor The electromigration lifetime of device.The cap layer can also include the metal beyond the copper removal for the electromigration that auxiliary reduces copper.

In some embodiments, it can change the composition of layers of copper by each plating process in frame 106.Citing comes Say, can plating substantially pure copper layer in the first plating process.In the second plating process, can plating include about 2.5 weight % The layers of copper of alloying element.In the 3rd plating process, can plating include about 5 weight % alloying element layers of copper.Therefore, can be by The composition of layers of copper is gradually increased into the composition of cap layer.

Method 100 embodiment (by the layers of copper plating with alloying element in chip wherein in whole method 100 On substrate) in, after using body electroplating technology, copper body layer is plated in wafer substrates, the wafer substrates can be handled so that Make at least some diffusion of alloy elements in alloying element into body layer.In some embodiments, the processing can be at heat Reason.The copper alloying element being diffused into body layer can also aid in reducing the electromigration of copper, so as to increase the electromigration of semiconductor device Life-span.

Although above method is to could be applicable to other metals on copper plating and redistribution description, methods described Plating and redistribution, for example, include tin (Sn), silver-colored (Ag) and golden (Au).

Equipment

The embodiment for being configured to realize the suitable equipment of method described herein is included for realizing that technique is grasped The hardware of work and the system controller with the instruction for being used to control technological operation.It is configured to allow for wafer substrates efficiently to follow The equipment that ring is operated by order plating, rinsing, drying and annealing process is applied to the embodiment used in a manufacturing environment. The equipment can include instrument and/or the room for being configured to perform more than one technological operations.For example, the equipment can wrap Containing be also configured to rinse and dry wafer substrates plating chamber and annealing chamber.As another example, the equipment can include Plating chamber and being configured to is rinsed to wafer substrates, dries and the room of annealing.It is configured to rush wafer substrates The particular for the instrument washed, dry and annealed can be the spin rinse drier (SRD) combined with annealing station.

Fig. 4 A to 4G show the example of the schematic diagram of electric fill system.Fig. 4 A show the schematic diagram of electric fill system 300 Example.Electric fill system 300 includes three individually electricity filling modules 302,304 and 306.Electric fill system 300 is also comprising warp Configure three single modules 312,314 and 316 for various technological operations.For example, in some embodiments, Module 312 and 316 can be SRD, and module 314 can be annealing station.In other embodiments, module 312,314 and 316 can be Module (PEM) after electricity filling, it is each configured to chip by the processing of one of electricity filling module 302,304 and 306 The bevel angle for performing for example described chip afterwards removes, the function of back side etch and acid cleaning.

Electric fill system 300 includes middle electrocardio filled chamber 324.Middle electrocardio filled chamber 324 fills module to keep being used as electricity In electroplating solution chemical solution room.Electric fill system 300 also includes dosing system 326, and it, which can store and deliver, is used for The chemical addition agent of electroplating solution.Chemicals dilution module 322 can store and mix the etching for waiting to be used as in (for example) PEM The chemicals of agent.Filtering may filter that the electroplating solution for middle electrocardio filled chamber 324 and be drawn into institute with pump unit 328 State electricity filling module.

Annealing station 332 can be used for annealing of wafer to be used as pretreatment.Annealing station 332 can be additionally used in annealing of wafer with reality Existing copper redistribution, as described above.Annealing station 332 can include several stacking annealing devices, such as five stacking Annealing device.The annealing device can self ground, with individually stack or with other more device deployment arrangements in annealing station 332 In.

System controller 330 provides the electronics and Interface Controller part operated needed for electric fill system 300.The system control Device, which generally comprises one or more storage arrangements and is configured to execute instruction, causes equipment executable according to herein One or more processors of the method for described embodiment.Containing for controlling according to reality described herein The machine-readable medium for applying the instruction of the technological operation of scheme can be coupled to system controller.System controller 330 can also include Power supply for electric fill system 300.

Handover instrument 340 can select chip from wafer cassettes (for example, cassette 342 or cassette 344).Cassette 342 or 344 can For open front formula unified pods (FOUP).FOUP to be designed to that securely and safely chip is held in controlled environment and Allow to remove the chip for by handling equipped with the instrument of appropriate load port and robot transportation system or measurement Housing.Vacuum accessory or a certain other attachment means can be used to keep chip for handover instrument 340.

Handover instrument 340 can interface with annealing station 332, cassette 342 or 344, transfer station 350 or aligner 348.Handover work Tool 346 can be from transfer station 350 close to chip.Transfer station can be that handover instrument 340 and 346 can not pass through the feelings of aligner 348 Condition get off back transmission wafer slit or position.However, in some embodiments, in order to ensure being fitted on handover instrument 346 Locality alignment chip fills module with accurate delivery to electricity, and handover instrument 346 can be directed at chip by aligner 348.Handover work Chip can also be delivered to one of electricity filling module 302,304 or 306 or be configured for use in various technological operations by tool 346 One of three separate modulars 312,314 and 316.

It can be continued as follows according to the example of the technological operation of method as described above：(1) module 304 is filled in electricity It is middle that layers of copper is plated on chip；(2) rinsed in the SRD in module 312 and dry chip；And (3) in module 314 by crystalline substance Piece is annealed to realize that copper redistributes.If necessary to be used for the further copper plating of copper redistribution, then repeat the work Skill operates.After layers of copper and annealing process is completed, cap layer can be plated on chip in electricity fills module 302.Can be Copper body layer is plated on chip in electricity filling module 306.It can be also suitable to by being provided to electricity filling module 302,304 and 306 The electroplating solution of pending technique and be interchangeably used it is described electricity filling module.For example, electricity filling module 302 can be used In carrying out copper plating with a kind of electroplating solution.The electroplating solution can be discharged from electricity filling module 302 and be grasped used in subsequent technique The electroplating solution for being used for the plating of body layer copper in work is replaced.

In some embodiments, module 314 can be by the hot plate resistance electrical heating to layers of copper itself by annealing of wafer. In some embodiments, module 314 can be included to by ultraviolet (UV) light source of annealing of wafer or infrared (IR) light source.At some In embodiment, electric fill system 300 can be included constantly to heat the device of chip during plating process.This can be via Wafer backside is carried out.

As described above, it is configured to allow for wafer substrates efficiently to cycle through order plating, rinsing, drying and annealing The equipment of technological operation is applied to the embodiment used in a manufacturing environment.In order to realize this, module 312 can be configured as revolving Turn flushing drier and annealing chamber.By this module 312, chip would only need to defeated between electricity filling module 304 and module 312 Send for copper plating and annealing operation.In addition, in some embodiments, electric fill system 300 can keep wafer substrates The pollution of chip is avoided with auxiliary in vacuum environment or inert gas atmosphere.

Fig. 4 B to 4G displayings substitute the example of the rough schematic view of electric fill system.Pay attention to, shown in Fig. 4 B to 4G The some or all of spies in the feature included in the electric fill system 300 shown in Fig. 4 A can be included in electric fill system Sign.For example, the electric fill system shown in Fig. 4 B to 4G can include the electricity for being used for bevel angle removal or other operations Module (PEM) after filling.The example of some configurations in the possible disparate modules configuration of Fig. 4 B to 4G main presentations.

The electric fill system 400 shown in Fig. 4 B includes four plating/wash modules 402 and four dryings/annealing mould Block 404.Electric fill system 400 is also comprising the handover instrument 406 that can be similar to handover instrument 340 and 346 as described above.Institute Stating four plating/wash modules can each self-contained equipment for being configured to plating chip and rinsing chip.Four dryings/move back Fiery module each self-contained can be configured to dry chip and by the equipment of the annealing of wafer.In some embodiments, electricity is filled out Charging system 400 can include less module (for example, four modules or six modules) or compared with multimode (for example, ten modules or ten Two modules).In addition, in some embodiments, each of eight modules shown in electric fill system 400 can wrap Two, three or three stacked containing self are with upper module.For example, plating/wash module 408 can be included on each other Three plating/wash modules of lower stacking, and drying/annealing module 410 can include three drying/annealing that self is stacked Module.

Module in electric fill system 400 can include the equipment for different operating, as described in this article.Citing comes Say, four plating/wash modules 402 can be instead plating module, and four dryings/annealing module can instead rinse/ Drying/annealing module.As another example, some modules can be flushing/irradiation modules.In some embodiments, rinse/dry Dry module can be included and is configured so that the atwirl component of chip.

The electric fill system 430 shown in Fig. 4 C includes four plating/wash modules 402 and four dryings/annealing mould Block 404.Electric fill system 430 also includes handover instrument 406.Electric fill system 430 is similar to electric fill system 400, wherein one Individual difference is all plating/wash modules 402 are on the side of electric fill system 430 and four dryings/annealing module 404 is another On side.The different configurations of module can be more efficient in terms of quickly processing chip.For example, make between two modules Transfer distance and/or time minimize and can aid in rapidly processing chip.

Similar to the module in electric fill system 400, the module in electric fill system 430 can be included for different operating Equipment.For example, four plating/wash modules 402 can be instead plating module, and four dryings/annealing module can generation It is alternately flushing/drying/annealing module.

The electric fill system 460 shown in Fig. 4 D includes eight plating/flushing/irradiation modules 462 and eight annealing moulds Block 464.Electric fill system 460 also includes handover instrument 406.Eight plating/flushing/irradiation modules each self-contained can be configured to Plating chip, rinse chip and the equipment for drying chip.Eight annealing modules each self-contained can be configured to annealing of wafer Equipment.As demonstrated, module 464 of annealing is in two groups of annealing modules, and each of which group annealing module includes self heap Four folded annealing modules.

The electric fill system 470 shown in Fig. 4 E includes four plating modules 472 and four flushing/drying/annealing moulds Block 474.Electric fill system 470 also includes handover instrument 406.Four plating modules can each self-contained plating chip that is configured to Equipment.Four flushing/drying/annealing modules each self-contained can be configured to rinse chip, dry chip and by annealing of wafer Equipment.

The electric fill system 480 shown in Fig. 4 F includes four plating modules, 472, four annealing modules, 464, four punchings Wash/irradiation modules 482 and four overload plating modules 484.Electric fill system 480 also includes handover instrument 406.As demonstrated, Plating module 472, flushing/irradiation modules 482 and annealing module 464 stack self, so as to form the four of these modules Group.As described in this article, plating module 472 can be used for the copper that plating will redistribute by the annealing in annealing module 464. Also as described in this article, the plating module 484 that overloads can be used for plating coating copper body layer.

The electric fill system 490 shown in Fig. 4 G includes eight plating modules, 472, eight annealing modules, 464, eight punchings Wash/irradiation modules 482 and two overload plating modules 484.Electric fill system 480 also includes handover instrument 406.As demonstrated, Two plating modules 472 stack self, so as to form the four of these modules groups.As described in this article, plating module 472 can be used for the copper that plating will redistribute by the annealing in annealing module 464.Two flushing/irradiation modules 482 are also each other Stacked on top, so as to form the four of these modules groups.Eight annealing modules 464 all self stack, so as to form this One stacking of a little modules.Two overload plating modules 484 also self stack, so as to form these modules heap It is folded.Also as described in this article, the plating module 484 that overloads can be used for plating coating copper body layer.

In some embodiments of method as described above, copper is plated to the backing layer with high sheet resistance On.For example, thin layer of ruthenium can have the sheet resistance of about 100 ohm-sqs to 200 ohm-sqs.One layer of sheet resistance Reduce and increase with its thickness.When one layer of sheet resistance is high, the edge of chip is (in the edge in electroplating device Made electrical contact with) voltage drop (being referred to as end effect) between the center of chip be present.This resistance drop during electroplating technology after It is continuous exist up to sufficient plating increase across the conductance of chip and reduce voltage drop untill.Resistance drop causes to drive Waffer edge attached The larger voltage of near electroplating reaction and the faster plating rates for therefore causing wafer edge.Therefore, plated layer can have There is the thickness of the adjacent edges of chip relative to the increased recessed profile in center of chip.This end effect, which can substantially increase, to be had Sheet resistance be greater than about the plated thickness degree near the Waffer edge of the inculating crystal layer of 1 ohm-sq or the chip of backing layer and Edge thickness can be caused further to increase with sheet resistance and become larger.In general, end effect is producing thickness change The influence of aspect is concentrated mainly on outside 15mm to the 30mm places of wafer diameter.

When being electroplated on the surface with high sheet resistance, the electroplating solution with low conductivity can be used.When When electroplating solution conductance reduces, compared with the overall voltage drop through plating vessel, between center wafer and Waffer edge Relative voltage drop diminishes.The thickness distribution of plated metal is improved, because the voltage phase of the reaction of driving wafer edge It is not much bigger for the voltage at center wafer.In some embodiments, low conductivity (high resistivity) plating is molten Liquid has greater than about 200 Ω-cm or greater than about 1000 Ω-cm resistivity, and it is about 2 Ω-cm to 20 Ω-cm that it, which is significantly higher than, Conventional electroplating solution resistivity.However, electroplating solution can only have up to the resistivity of certain level and still containing enough copper with The electroplating solution plating coating copper can be used.

Included to reduce the other manner of end effect to electroplating device addition auxiliary cathode, screen and resistance member Part.All these devices and technology is discussed further below.

The example of the cross-sectional view of Fig. 5 displaying electroplating devices.Can be in electricity filling module as described above or plating Electroplating device 101 is included in any of module.Electroplating device 101 is included containing the plating for being shown as being in liquid level 105 The plating vessel 103 of solution.Chip 107 can be immersed in the electroplating solution and by being installed in rotatable spindle 111 " clam shell " holding jig 109 is kept.The rotatable spindle allows clam shell 109 to be rotated together with chip 107.Clam shell plating is set Standby to be further described in the 6th, 156, No. 167 United States Patent (USP) and the 6th, 800, No. 187 United States Patent (USP), both described patents are to draw Mode is incorporated herein.Certainly, the wafer holders in addition to clam shell fixture can be used.

Anode 113 is placed in plating vessel 103 below chip 107 and by anode film 115 (in some embodiments In, it is ion-selective membrane) separated with wafer area.Region below anode film is commonly referred to as " anode chamber ", and this Indoor electrolyte is referred to as " anolyte ".The ion that anode film 115 allows to electroplate between the anode and cathode zone of vessel connects It is logical, while prevent any particle caused by anode from entering near chip and pollute the chip.Anode film can also fit For redistributing electric current during electroplating technology and improving plating uniformity whereby.Anode film is further described in the 6th, In 126, No. 798 United States Patent (USP)s and the 6th, 569, No. 299 United States Patent (USP), both described patents are hereby incorporated herein by In.

Electroplating solution can be continuously provided to by plating vessel 103 by pump 117.In general, electroplating solution is worn upwards Cross anode film 115 and resistive element 119 flow to the center of chip 107 and then radially outward and across chip flowed. In some embodiments, it can be provided from the side of plating vessel 103 by electroplating solution into the anode region of the plating vessel. In some embodiments, electroplating solution can be fed in the anode and cathode zone of plating vessel via single entrance.

Resistive element 119 is located at chip (in various embodiments, at about 10 millimeters or about 3 millimeters To in 8 millimeters) and serve as the constant current source of chip.That is, resistive element 119 enters to the electrolyte electric current near chip Row is moulding to provide relatively uniform CURRENT DISTRIBUTION in wafer face.The element contains multiple one-dimensional through holes, and following article enters one Step description.Further detail below on resistive element " can be used for electric plating method and equipment (METHOD AND entitled APPARATUS FOR ELECTROPLATING) " and No. 12/291,356 U.S. being filed an application on November 7th, 2008 it is special Found in sharp application case, the application case is incorporated herein by reference.

Electroplating solution then overflows to overflow tank 121 from plating vessel 103, as indicated by arrow 123.It may filter that (not Displaying) electroplating solution and pump 117 is returned to as indicated by arrows 125, so as to complete the recycling of electroplating solution.

The second cathode chamber 127 containing the second negative electrode (that is, surreptitiously flowing negative electrode) 129 can be located on the outside of plating vessel 103 And chip periphery.In general, the second negative electrode can be positioned at several opening positions in plating vessel or on the outside of plating vessel.

In some embodiments, the weir wall of electroplating solution from plating vessel 103 is overflowed in the second cathode chamber 127. In some embodiments, the second cathode chamber 127 by the wall with the multiple openings covered by ion-permeable film and with electricity Plating vessel 103 separate.The film allow electroplate the cathode chamber 127 of vessel 103 and second between ionic communication, allow whereby by Electric current redirect to the second negative electrode.The porosity of film may be such that it does not allow granular materials to cross electricity from the second cathode chamber 127 Plate vessel 103 and cause wafer contamination.Opening in wall can take the other shapes of shape of circular port, slit or all size Formula.In one embodiment, the opening be with (such as) slit of about 12 millimeters × 90 millimeters of size.Come in handy In the other mechanism for allowing fluid and/or ionic communication between the second cathode chamber and plating vessel.Example includes wherein film Rather than impermeable wall provides most of gesture between the electroplating solution in electroplating solution and plating vessel in the second cathode chamber The design at base.In this little embodiment, rigid frame can provide the support to film.

Two DC electric power supplies 135 and 137 can be used to control chip 107 and the electricity to the second negative electrode 129 respectively Stream.Electric supply 135 has is electrically connected to chip 107 via one or more slip rings, brush or contact (not showing) Negative output lead 139.The positive output lead 141 of electric supply 135 is electrically connected to the anode in plating vessel 103 113.For example, the electric supply can have the output voltage for being up to about 250 volts.Similarly, electric supply 137 has There are the negative output lead 143 for being electrically connected to the second negative electrode 129 and the positive output lead 145 for being electrically connected to anode 113.Or can Using with it is multiple can an electric supply of independent control electrical outlet provide the electric current of varying level to chip and second Negative electrode.

Electric supply 135 and 137 may be connected to controller 147, and controller 147 allows to arrive electroplating device 300 to offer Element electric current and current potential modulation.For example, the controller can allow to enter with current controlled or current potential slave mode Row plating.System controller 330 can include regulation need to be applied to electric current and the voltage level of the various elements of electroplating device with And need to change the programmed instruction of the time of these level.For example, its can include be used for by chip be immersed into plating it is molten At once the programmed instruction of current control is converted to after in liquid from control of Electric potentials.

During use, by the negative electrode 129 of chip 107 and second, both are biased to relative to sun electric supply 135 and 137 Pole 113 has negative potential.This electric current for causing to flow to chip 107 from anode 113 is partially or substantially redirect to second the moon Pole 129.Circuit as described above can be also included anti-one or several two poles inverted here in undesirable current reversal Pipe.Unacceptable current feedback may occur during electroplating technology, because the anode 113 for being set as earthing potential is wafer electric The common elements of both road and the second cathode circuit.

Be applied to the electric current of the second negative electrode 129 level be typically set at electric current than being applied to chip 107 level it is low Value, wherein the second cathode current is rendered as a percentage of wafer current.For example, the 10% the second cathode currents correspond to At second negative electrode is 10% electric current to the electric current of chip.Sense of current as used herein is that net cation leads to The direction of amount.During plating, electrochemical reduction (such as Cu can occur in both wafer surface and the second cathode surface²⁺+ 2e^-=Cu⁰), this causes to deposit copper on the surface of both chip and the second negative electrode.Due to electric current is redirect into second from chip Negative electrode, therefore the thickness of institute's copper layer of the edge of chip can be reduced.This effect is generally at 20 millimeters of the outside of chip Occur and especially prominent at 10 millimeters outside it, particularly when performing plating to backing layer or thin inculating crystal layer.Second negative electrode 129 use can substantially improve the center ＆ periphery inhomogeneities as caused by end and field-effect.Can be individually or jointly other auxiliary Negative electrode or the multiple fixations of combination or dynamic barrier thing is helped to use the second negative electrode.

Further detail below on auxiliary cathode (including two level and three-level negative electrode) " can be used for electric plating method entitled And equipment (METHOD AND APPARATUS FOR ELECTROPLATING) " and filed an application on June 9th, 2009 Found in 12/481, No. 503 U.S. patent application case, the application case is incorporated herein by reference.It should be understood that auxiliary Negative electrode and its associated power supply are optional feature.

One or more screens (such as 149) can be positioned in plating vessel resistive element 119 and anode 113 it Between (for example, resistive element below) in chip face-down systems.The screen is usually the dielectric insertion of ring-shaped Part, it is used to carry out uniformity that is moulding and improving plating to current profile, such as is being hereby incorporated herein by In No. 6,027,631 United States Patent (USP) described in those.Other screens known to those skilled in the art can be used Cover thing design and shape.

In general, the screen can take any shape, comprising wedge shape, bar shaped, circle, the shape of ellipse and its Its geometry designs.The insert of ring-shaped can also have some patterns at its inside diameter, and the pattern can improve screen Moulding ability is carried out to current flux in a manner of desired.The function of the screen can be different, and this is being electroplated depending on it Position in vessel.The equipment can include any one of static mask thing and the moulding element of variable field, such as the 6th, Those described in 402, No. 923 United States Patent (USP)s and the 7th, 070, No. 686 United States Patent (USP), both described patents are with the side of reference Formula is incorporated herein.Equipment can also include the segmented anodes or such as the described in such as No. 6,497,801 United States Patent (USP) Any one of concentric anode described in 6,755, No. 954 and the 6th, 773, No. 571 United States Patent (USP), all patents are equal It is incorporated herein by reference.Although shielding insert is applicable to improve electroplating evenness, in some embodiments In, without using the shielding insert or it can use replacement shield configuration.

Screen (such as screen 151) can be positioned in plating vessel between resistive element 119 and chip 107.One In a little embodiments, circumference that screen can reside within around resistive element sentences that further to improve edge-center plating uniform Property.In some embodiments, screen can reside within resistive element just above.In some embodiments, screen can be determined Between resistive element and chip between at least some perforation in the perforation at the outer peripheral areas of barrier element and chip Path.

Resistive element

In some embodiments, resistive element 119 can be more microwell plates or disk with continuous three-dimensional pore space network (for example, the plate made of the sintering particle of ceramics or glass).Porous plate with three-dimensional pore space network includes entanglement hole, warp Chip not only can be advanced to through plate by the entanglement hole gas current vertically upward along the general direction of anode but also can be laterally Advance (for example, from the center of plate to edge).Example for the suitable design of this little plate, which is described in, to be herein incorporated by reference In No. 7,622,024 United States Patent (USP) herein.

In some embodiments, resistive element 119 can be included and provided through the path of the resistive element in element Main body in the hole or passage that do not communicate with each other substantially.This some holes gap or passage can be linearly or nonlinearly.This some holes gap Or passage can also direction that is parallel or being not parallel to gas current.

In some embodiments, resistive element 119 can include and be in substantially parallel relationship to the direction of gas current and in element The linear hole or passage (that is, the one-dimensional through hole in resistive element) not communicated with each other substantially in main body.This hole or passage are matched somebody with somebody The transverse shifting for putting the gas current made in element minimizes.Gas current is in a manner of one-dimensional (that is, approximately along perpendicular to resistance The vector direction of nearest plated surface (for example, chip 107) near element) flowing.This resistive element is referred to as one-dimensional resistance Element.

Resistive element (also referred to as one-dimensional porous high resistance virtual anodes or HRVA) comprising one-dimensional through hole is usually by having Have through disk made of the ion resistance material in multiple holes of its drilling (or otherwise making) and (other shapes also can be used Shape).The hole forms communicating passage not in the main body of disk and generally prolonged along the direction on the surface for being approximately perpendicular to chip Extend through the disk.Different kinds of ions resistance material can be used for disc body, comprising makrolon, polyethylene, polypropylene, poly- inclined Difluoroethylene (PVDF), polytetrafluoroethylene (PTFE), polysulfones etc..In some embodiments, disc material is in acidic electrolysis bath environment It is degradation resistant, relatively hard and handled easily by machining.

In some embodiments, the resistive element can be close to the overall resistance of workpiece and domination electroplating device. When the resistive element has sufficient resistance relative to workpiece thin layer resistance, the resistive element can approaches uniformity distributed current Source.In general, the sheet resistance for the layer being just plated is higher, the resistance of the resistive element required for auxiliary mitigation end effect It is higher, or the resistivity of electroplating solution is higher.By high-resistance resistive element, in some embodiments, can be used The electrolyte of low resistivity and vice versa.

By making workpiece remain close in resistive element, ion resistance ratio from the top of element to the surface of workpiece is from member The Ion paths resistance of center-top of part to the edge of work is much smaller, thin in the inculating crystal layer of backing layer so as to substantially compensate Layer resistance and workpiece overcentre guide significant quantity electric current.It is associated with using the resistive element close to chip Details is discussed further in No. 11/040,359 U.S. patent application case.

No matter resistive element is to permit the electric current more than one-dimensional or one-dimensional, and in some embodiments, it can be with work Part coextensive.Therefore, when workpiece is chip, resistive element has the diameter for the diameter for being generally near the chip being just plated. For example, resistive element diameter can be diametrically about 150 millimeters to 450 millimeters, wherein about 200 millimeters of resistive elements are used for 200 millimeters of chips, about 300 millimeters of resistive elements are used for 300 millimeters of chips, and about 450 millimeters of resistive elements are used for 450 millimeters of crystalline substances Piece, etc..Chip (such as recess or is wherein stopped with substantial circular shape but in edge with irregular concavo-convex wherein The flat site of cut crystal) example in, the resistive element of disc-shape still can be used, but electroplating device can be made other Compensation adjustment, as described in the 12/291st, No. 356 U.S. patent application case.

In some embodiments, resistive element has the diameter for the diameter for being more than the chip for treating plating (for example, being more than 200 millimeters or 300 millimeters) and there is non-porous outer edge portion (in the case of one-dimensional resistive element).This marginal portion Available for around the periphery of chip formed small―gap suture (resistive element marginal portion and Waffer edge or chip keep cup bottom it Between peripheral clearance) and auxiliary resistive element is installed in plating vessel.In some embodiments, non-porous resistive element side The size of edge (edge of the porose part of tool from the external margin of resistive element to resistive element) is about 5 millimeters to 50 millis Rice.

In some embodiments of one-dimensional resistive element, the number of the through hole in element can be big, each of which hole It is a diameter of small.In general, the diameter in each hole is smaller than the about a quarter in the gap between resistive element and workpiece. In some embodiments, the number in hole can be about 5,000 to 12,000.In some embodiments, each hole (at least 95% Hole) can have be less than about 5 millimeters or the diameter (or other major dimensions) less than about 1.25 millimeters.

Fig. 6 A and 6B show the example of the view of one-dimensional resistive element.The reality of the top view of Fig. 6 A displaying resistive elements 602 Example, it illustrates the top surface of resistive element.Resistive element 602 includes substantial amounts of minor diameter opening (being shown as stain). The example of the cross-sectional view of Fig. 6 B shows resistive element 602.As demonstrated in Figure 6 B, through hole is approximately perpendicular to the top of resistive element Portion and lower surface.

In some embodiments, the thickness of resistive element be about 5 millimeters to 50 millimeters, for example, about 10 millimeters to 25 milli Rice or about 10 millimeters to 20 millimeters.In some embodiments, the thickness of resistive element is less than about the 15% of wafer diameter.

Resistance for giving the resistive element in the electroplating device of electroplating solution depends on several parameters, includes resistance The thickness of element and the porosity of resistive element.The porosity of resistive element can be by opening institute of the hole on the surface of resistive element Area occupied by the area occupied divided by the surface of resistive element defines.Pay attention to, this area occupied by the surface of resistive element Plating is installed or be held in resistive element by being used for for active region (that is, with the area of electrolyte contacts) and not comprising resistive element Region in equipment.In some embodiments, the porosity of resistive element can be about 1% to 5% or about 1% to 3%.

In some instances, high-resistance resistive element can be used in the larger application of wherein end effect.Citing comes Say, high-resistance resistive element may the sheet resistance on the surface being just plated be about 100 ohm-sqs to 200 ohm/it is flat It is particularly useful when square.In the embodiment of method as described above, when copper is directly plated on backing layer, end is imitated Should may be big.For example, a such a backing layer can be ruthenium.

The resistive element can be determined by determining the resistance of the electroplating solution in the volume that treat to be occupied by resistive element Resistance.For example, a diameter of 288 millimeters of the zone of action can be included for electroplating the resistive element of 300 millimeters of chips (652cm²Active region) and its thickness be 1.27cm.Therefore, the plating of the resistivity with 1250 ohm-cms (Ω-cm) Resistance of the solution in the volume for treating to be occupied by resistive element is (1250 Ω-cm) * (1.27cm)/(652cm²) or 2.43 Ω. It is described in the case where resistive element is not in place in the case that resistive element in electroplating device has 2.43% porosity Only the 2.43% of volume can be used for conducting.Therefore, the resistance of resistive element is (2.43 Ω)/(2.43%) or 100.1 Ω.

Table 1 include for 1250 Ω-cm electroplating solutions have a diameter of 288 millimeters the zone of action some exemplary one Tie up the resistance of resistive element.

The resistance of the exemplary one-dimensional resistive element of table 1.

In some embodiments, the resistance of resistive element is (assuming that the resistance member for electroplating 300 millimeters of wafer substrates Part, its use at away from about 3 millimeters of distances to 8 millimeters of wafer substrate surface) it is about 25 ohm to 250 ohm (Ω), about 25 Ω to 75 Ω, about 75 Ω to 150 Ω or about 150 Ω to 250 Ω.

Resistive element can also be characterized by its resistance divided by the active area in the face of the resistive element.Therefore, resistance member Part can have about 0.04 Ω/cm²To 0.4 Ω/cm², about 0.04 Ω/cm²To 0.1 Ω/cm², about 0.1 Ω/cm²To 0.2 Ω/cm² Or about 0.2 Ω/cm²To 0.4 Ω/cm²Every area resistance.

Incorporating the electroplating device of high-resistance resistive element can need to have relative high output voltage with typical institute The electric supply of plating is carried out under expectation electric current level.For example, using the teaching of the invention it is possible to provide about 50 volts or bigger of output voltage Electric supply can be used together with high-resistance resistive element (such as 2X resistive elements in table 1).More particularly, electric power Supply can provide about 100 volts to 175 volts of output voltage (wherein 150 volts are representative instance).It can provide even more The electric supply of high output voltage (for example, about 150 volts to 250 volts) can with more high-resistance resistive element (for example, table 4X resistive elements in 1) it is used together.

When copper is plated on ruthenium, the current potential applied between chip and negative electrode is depending on the thickness and chip of layer of ruthenium are straight Footpath.For example, for 300 millimeters of chips, when copper is plated in the layer of ruthenium of 3 nanometer thickness, about 75 volts of current potential can be with table 1 In 2X resistive elements be used together, this produce about 0.75 peace plating current.For having on the surface of 300 millimeters of chips The chip of different ruthenium thickness, when copper is plated on ruthenium, about 70 volts to 120 volts of current potential can be with the 2X resistance in table 1 Element is used together, so as to produce about 0.75 peace to the plating current of 1.2 peaces.

The resistance of resistive element is produced by the thickness through the resistive element for low but continuously coupled porosity.In electricity In plating liquor, this can form very high-resistance compact area, and this can be positioned at wafer surface.By contrast, Thick resistive element with relatively low and non-one-dimensional porosity can with resistive element identical resistance disclosed herein, but The electric current steering characteristic of this thick resistive element may differ.Electric current in this thick resistive element can be tended to flow into element Heart district domain and flowed radially outward as it is flowed up.

Another important parameter of one-dimensional resistive element is through-hole diameter (or other major dimensions) and distance of the element away from chip Ratio.Then examined empirically and by microcomputer modelling and found, this ratio should be approximately 1 or smaller (for example, being less than About 0.8 or less than about 0.25).In some embodiments, this ratio is about 0.1, to provide good electroplating evenness performance.Change Sentence is talked about, and the diameter in hole can be equal to or less than the distance from resistive element to workpiece.If bore dia is more than chip to resistance member Part distance, then leave its individual currents image or " trace " in the above on the plated layer that hole can be, cause whereby plated Small-scale inhomogeneities in layer.Open in the hole that bore dia value described above refers to measure on the resistive element face close to chip The diameter of mouth.In some embodiments, the bore dia on both the nearly face of resistive element and remote face is identical, but hole is alternatively gradually Thin.

Although the resistive element shown in Fig. 6 A has uniform pore size distribution, in other embodiments, resistance member Part can have with on-uniform porosity be distributed or with through stop with formed on-uniform porosity distribution hole region.This pore size distribution can incite somebody to action More electric current is directed to the center of workpiece, in order to the high thin-layer electric resistance layer of relatively evenly plating.If however, use on-uniform porosity Distribution, then the very thick film with low sheet resistance can be intended to more unevenly plating.Hole through stopping or lacking can It is uneven in radial direction, azimuth or both direction.

In some embodiments, resistive element is roughly parallel to workpiece surface and anode surface positioning, and one-dimensional Kong Ping Direction orientation of the row between wafer surface and anode surface.In other embodiments, at least some holes in the hole make Its relative angle is changed to change hole length relative to component thickness and change localized contributions of the hole to resistance whereby.

It should be noted that one-dimensional porous resistive element is different from so-called diffuser plate.The major function of diffuser plate is distribution electrolysis The flowing of liquid rather than the notable resistance of offer.Diffuser plate generally there is composition to be enough to realize generally uniform electricity via notable sticky flow resistance Solve the dynamic much bigger net porosity (in the range of from 25% to 80%) of liquid stream and in general to the resistance of electroplating device Opening with less (generally inappreciable) overall contribution.By contrast, one-dimensional resistive element can dramatically increase plating The resistance of equipment, this may be required for improving electroplating evenness.

Experiment

In a kind of technique, the copper of 10 nanometers of plating on Ru backing layers.By similar in No. 7,799,684 U.S. The method of method described in patent carrys out plating layers of copper.Then rinse and dry layers of copper.In forming gas at about 300 DEG C Layers of copper is annealed.Repeat the process three times；That is, four circulations of technological operation are performed.

Scanning electron microscopy (SEM) microphoto of the cross section of chip shows that the technological operation is completely filled with having There are about 30 nanometers of features to 60 nanometers of width.The remaining very less or not residual copper in the field areas near feature of chip, This is attributed to copper and is redistributed in the feature.In the region not comprising any feature of chip, residual copper in field areas.

In another technique, the copper of 10 nanometers of plating on Ru barrier layers.By similar in No. 7,799,684 U.S. The method of method described in patent carrys out plating layers of copper.Then rinse and dry layers of copper.In forming gas at about 200 DEG C Layers of copper is annealed.Repeat the process three times；That is, four circulations of technological operation are performed.

The SEM micrograph of the cross section of chip shows that the technological operation is partially filled with about 60 nanometers of width Feature.Some remaining copper in the field areas of chip.It is remaining in field areas in the region not comprising any feature of chip Copper.

Following embodiment

Device and method described herein may also be combined with lithographic patterning instrument or technique and use, (for example) with Make or manufacture semiconductor device, display, LED, photovoltaic panel etc..Generally, (although need not) this little instrument/technique will be normal See to make in facility and be used together or carry out.The some or all of steps in following steps are generally included to the lithographic patterning of film Suddenly, each step is realized by several possible instruments：(1) using spin coating or Spray painting tool on workpiece (that is, substrate) Apply photoresist；(2) solidify photoresist using hot plate, stove or UV tools of solidifying；(3) by instrument (example Such as, wafer stepper) photoresist is exposed to visible, UV or x-ray light；(4) make the resist development with Just optionally remove resist using instrument (for example, wet corrosion cutting) and be patterned whereby；(5) by using Dry type or plasma asistance etch tool are transferred resist patterns into underlie film or workpiece；And (6) use instrument (example Such as, RF or microwave plasma corrosion inhibitor stripper) remove the resist.

Claims (25)

1. a kind of method for filling interconnection structure, it includes：

(a) wafer substrates being provided to equipment, the wafer substrates include the surface with some field areas and a feature, wherein The width or diameter of the feature are less than 100 nanometers；

(b) layers of copper is conformally electroplated onto on the surface of the wafer substrates；And

(c) layers of copper is annealed at a temperature of 150 DEG C to 400 DEG C, the copper wherein annealing flows back in the layers of copper is simultaneously The copper is set to be redistributed to the bottom of the feature from some field areas tights of the wafer substrates；

(d) repeat (b) and (c), until the aspect ratio of the feature is 2:Untill 1 or smaller.

2. according to the method for claim 1, wherein it is described annealing cause the copper by the wafer substrates field areas without Space is bottom-up to be filled into the feature.

It is 3. according to the method for claim 2, wherein described when layers of copper annealing is carried out into 30 seconds to 180 seconds lasting Between.

4. according to the method for claim 1, described the layers of copper is annealed wherein being performed in reducing atmosphere.

5. according to the method for claim 1, wherein from by the mixture of hydrogen and nitrogen, atomic hydrogen and other electronations The reducing atmosphere is selected in the group of agent composition.

6. according to the method for claim 1, wherein the surface of the chip includes the field areas and the feature The backing layer of top.

7. according to the method for claim 6, it further comprises：

The backing layer is annealed in reducing atmosphere before the layers of copper is electroplated.

8. according to the method for claim 6, wherein from by ruthenium (Ru), cobalt (Co), tungsten (W), osmium (Os), platinum (Pt), palladium (Pd), the backing layer is selected in the group of golden (Au) and rhodium (Rh) composition.

9. according to the method for claim 1, wherein the layers of copper includes copper alloying element.

10. according to the method for claim 1, wherein plating is what is carried out at the higher temperature of the boiling point than water.

11. according to the method for claim 1, wherein the aspect ratio of the feature is more than 15:1.

12. according to the method for claim 1, wherein the thickness of the layers of copper is 2 nanometers to 20 nanometers.

13. according to the method for claim 1, it further comprises：

Copper is redistributed to the feature from some regions of the wafer substrates in the annealing and cause the vertical of the feature Horizontal ratio is 2:After 1 or smaller, copper is electroplated onto in the layers of copper to fill the feature.

14. according to the method for claim 1, it further comprises：

Repeat (b) and (c) 2 times to 8 times.

15. according to the method for claim 1, it further comprises：

After the layers of copper is annealed, copper alloy layer is electroplated onto in the layers of copper.

16. according to the method for claim 1, wherein the layers of copper is continuous.

17. according to the method for claim 1, wherein performing the plating at a temperature of about room temperature.

18. according to the method for claim 1, wherein performing the plating at a temperature of 50 DEG C to 90 DEG C.

19. according to the method for claim 1, it further comprises：

Photoresist is applied to the wafer substrates；

The photoresist is exposed to light；

The photoresist is patterned and transfers the pattern onto the wafer substrates；And

The photoresist is optionally removed from the wafer substrates.

20. according to the method for claim 1, wherein the plating is the plating in the resistivity with higher than 200 Ω-cm Performed in solution.

21. according to the method for claim 20, wherein the plating is the electricity in the resistivity with higher than 1000 Ω-cm Performed in plating liquor.

22. according to the method for claim 6, wherein the backing layer includes ruthenium (Ru).

23. a kind of method for filling interconnection structure, it includes：

(a) wafer substrates are provided to equipment, the wafer substrates include the surface covered with backing layer, if the surface includes Dry field areas and a feature, wherein the width or diameter of the feature are less than 100 nanometers；

(b) layers of copper is conformally plated on the surface of the wafer substrates by electroplating technology；And

(c) layers of copper is annealed, wherein being performed in reducing atmosphere at a temperature of 150 DEG C to 400 DEG C described by the copper Layer annealing was up to duration of 30 seconds to 180 seconds, and wherein described annealing flows back the copper in the layers of copper and makes the copper from institute It is redistributed to the bottom of the feature with stating some field areas tights of wafer substrates；

(d) repeat (b) and (c), until the aspect ratio of the feature is 2:Untill 1 or smaller.

24. according to the method for claim 23, wherein the plating is the electricity in the resistivity with higher than 200 Ω-cm Performed in plating liquor.

25. according to the method for claim 24, wherein the plating is the electricity in the resistivity with higher than 1000 Ω-cm Performed in plating liquor.