JP3150582B2 - Substrate for air rear grid array package and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a substrate for an air rear grid array package.
More specifically, the present invention relates to a substrate structure and a manufacturing method for obtaining an inexpensive and highly reliable air rear grid array.

[0002]

2. Description of the Related Art Recently, an air rear grid array package has rapidly spread as a technique for connecting a semiconductor chip and a printed circuit board. In other words, this technology provides a so-called ball grid array, chip size package, and provides pads on one side of a substrate in the form of lattice points,
By mounting solder balls or solder paste on the pads, the board is connected to a printed board called a motherboard (these are described in Jo.
hn H. Lau, Ball Grid Array Technology (McGraw Hil
See l Company, 1995).

In these substrates, a first layer having a pad with an insulating layer interposed therebetween and a second layer having a semiconductor chip mounted thereon.
The connection with the layer was usually made by a through-hole (through hole) provided on the outer periphery of the air rear grid array (pads arranged in a plane).

For this reason, it is necessary to route the wiring from the pads arranged in a grid pattern to the outer periphery, and when the number of pins is increased, the routing becomes extremely difficult, and the first problem such as a reduction in yield is caused. .

[0005] In addition, a second problem is that a solder resist (liquid register) surrounding the pad is required for routing the wiring to the outer periphery, and the cost is further increased.

Further, since the pad has a planar structure, there is a third problem that the shear strength after mounting the solder ball or the solder paste on the pad is small and the solder is peeled off from the pad due to heat, stress or the like. Was.

In order to solve the first problem, a method is proposed in which a via hole from the second layer to the first layer is provided instead of the through hole, and wiring is performed by plating the second layer and the inside of the via hole. (See, for example,
No. 74281). In this method, wiring is performed directly from the pad to the second layer, so that the first and second problems can be reduced.

[0008] The technique of forming a printed circuit board using a laser is mainly used for drilling a via hole or the like. Laser is carbon dioxide laser, YAG
There are lasers, excimer lasers, etc., but it is excimer lasers or Y
It is an impact laser obtained by improving an AG laser or a carbon dioxide laser (for example, for an excimer laser and its application to a printed circuit board, see, for example, JP-A-5-136650, JP-A-5-152744, No. 5-152748).

[0009]

However, a via hole extending from the second layer to the first layer is provided in place of the above-mentioned through hole, and wiring is performed by plating the second layer and the inside of the via hole (see the above-described method). Japanese Unexamined Patent Publication No. 7-74281) has the following problems.

That is, since the second layer here generally requires routing from the semiconductor chip to each pad, the second layer usually has a higher density than the first layer having only the pads. Although there are various requirements for obtaining high-density wiring, the thickness of the circuit layer is a major factor among them. If the thickness is large, it is difficult to obtain high-density wiring.

However, the above conventional method is based on the premise that a via hole is formed from the second layer to the first layer, and plating is performed from at least the second layer side (see Japanese Patent Application Laid-Open No. 7-74).
281). Therefore, this technique has a fourth problem that the thickness of the second layer is increased, and it is extremely difficult to obtain high-density and fine wiring.

A third problem is that the pad has a planar structure, the shear strength after mounting the solder ball or the solder paste on the pad is small, and the solder peels off the pad due to heat, stress, or the like. Has also not been resolved.

[0013] The present invention provides the first and second techniques of the prior art.
An object of the present invention is to solve the second, third, and fourth problems by simple means, and an object of the present invention is to provide a high-density air rear device capable of mounting a multi-pin semiconductor by simple means. -To provide a substrate for a grid array package and a method for manufacturing the same.

[0014]

Means for Solving the Problems A substrate for an air rear grid array package according to the present invention comprises an insulating layer 3
Between the first layer 1 having the pad 7 and the second layer 2 on which the semiconductor chip 10 is mounted.
In the substrate for the air rear grid array package connected to the layer 2, the pad 7 on the first layer 1 side
Some, and reaches up to the rear surface of the second layer 2 via the insulation layer 3
Both cross-section tapered via 6 as a second layer 2 side as tapered are formed, in which is integrated with a portion 9 of the second layer 2 side of the wiring 8 (see claim 1) .

The via 6 may have a recess formed in the pad 7 without burying the interior, or may have a recess formed in the pad 7 with the interior buried (claims 2 and 3). reference). In the above, the part 9 of the wiring 8 indicates a land.

[0016] B production method of Earia grid array package substrate according to the present invention, the first layer 1 side
The insulating layer 3 is perforated by laser processing, and is formed on the back surface of the second layer 2.
After forming the via hole 4 having a tapered cross section, the via hole 4 is tapered toward the second layer 2 side.
A via 6 is formed by plating a via hole 5 from the side where the opening is formed, and then etching is performed on both sides to form the first layer 1.
In which the pads 7 are arranged in lattice points, the second layer 2 so as to form each wiring 8 land 9 to the semiconductor chip 10 (see claim 4).

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A substrate used in the practice of the present invention has a first layer 1 of copper foil or copper plating on one side with an insulating layer 3 in between, and a first layer 1 of copper foil or copper plating on the other side. It has a three-layer structure in which two layers 2 are formed.

As the resin component of the insulating layer 3, either a thermosetting resin or a thermoplastic resin can be used. Among the thermosetting resins, an epoxy resin, a polyimide resin, a polycyanurate resin, a polysilane resin, a polybenzimidazole resin, a bismaleimide triazine resin, or the like is preferable. The thickness of the insulating layer 3 is several μm to several hundred μm.
Where the typical thickness is 20-100 μm.

The insulating layer 3 can contain a reinforcing material such as an inorganic fiber such as a glass fiber or an organic fiber, but does not need to include it. When the insulating layer 3 does not include a reinforcing material, a film,
It can be in sheet form. Materials include polyester, polyimide, polyetheretherketone,
Polyamides, especially polyparaphenylene terephthalamide in aramid, are preferred.

When the insulating layer 3 contains a reinforcing material, the reinforcing material may be an inorganic fiber such as glass fiber, aramid fiber, Teflon fiber, polyetheretherketone fiber, or the like.
Any organic fiber such as polybenzimidazole fiber may be used. Above all, aramid fiber and Teflon fiber have laser processing easiness and excellent workability and electrical properties, and among the aramid fibers, copolyparaphenylene 3,4 ′ oxydiphenylterephthalamide fiber is particularly low in ionic impurities and low. Suitable for moisture absorption.

As described above, a via hole which penetrates the first layer 1 and the insulating layer 3 on one side but does not penetrate the second layer 2 on the other side, and has a tapered cross-sectional shape is formed in the three-layer laminated substrate. 4 is formed. The diameter of the via hole 4 is 10 to 200 μm,
Preferably, it is about 25 to 100 μm. The taper becomes narrower from the first conductive layer 1 to the second conductive layer 2, and the taper angle is 1 ° to 30 °, preferably 5 ° to
It is about 20 °.

Various means such as mechanical, chemical or optical can be used as the means for forming the via hole 4. However, it is preferable to use a laser because it is simple and high precision can be obtained. As a laser, any of a carbon dioxide laser, a YAG laser, and an excimer laser can be used. However, in order to process the inner wall of the via hole 4 smoothly without roughening, an impact laser, which is a kind of carbon dioxide laser, or YAG laser It is preferable to use a laser, an excimer laser, or the like.

The laser beam is focused to a certain area and the first side
Irradiation is performed from above the layer 1. In order to limit an irradiated portion, masking such as a mask image method, a contact mask method, and a conformal mask method can be used.
A large area may be irradiated at once to form a pattern with a mask, a laser beam narrowed down may be moved along a predetermined pattern, and a laser beam narrowed down may be scanned. Good.

The laminated substrate in which the via hole 4 is formed is then subjected to via hole plating 5 from the opened first layer 1 side, and the opposite side is masked and plated. The substrates may be separated from each other after pasting them back to back and plating on both sides. It is desirable that the plating material be mainly composed of copper.

Since the purpose of this plating is to provide conduction to the via hole 4, the thickness may be smaller than that of a normal through-hole plating, and the thickness may be several μm to several tens μm.
Is preferred. Typical thickness is between 8 and 15 μm.
The plating may be electroless plating or electrolytic plating, or a combination thereof. As a result, a via 6 having an opening and a plating 5 formed therein is formed in the first layer 1.

After the above-mentioned plating, the first substrate
The layer 1 and the second layer 2, the etching is performed in the usual sub subtractive method, Ru is performed circuit processing. At this time, on one side, the first layer 1 and the plating 5 on the upper surface thereof are etched to form the pads 7 arranged in a grid. The pad 7 is partially, preferably in the center, although vias 6 which is opened is kept in the Ku so that the position of the via 6 always
May not be at the center of the pad 7.

In the second layer 2 on the other surface, the second layer 2 is etched to provide a connection to a semiconductor chip 10 to be mounted later, thereby forming a land 9 and a wiring 8 connected to the inner bottom of the via 6. Is done.

At this time, the thickness of the second layer 2 is kept thin by applying the via-hole plating 5 only to the first layer 1 side as described above, and the wiring 8 formed on this surface is formed.
Can be reduced. In addition, 如 via 6 of the above
In addition , since the first layer 1 has a tapered cross section from the first layer 1 side to the back surface of the second layer 2 via the insulating layer 3 , the second layer side has a tapered cross section . The land 9 of the two layers 2 can be made smaller, and the formation of the fine wiring 8 is easier.

The pads 7 formed on the first layer 1 include:
In the case where a substrate for a ball grid array is provided without the via 6 but with the pad 7 having a concave portion without being embedded, the solder ball 11 melts into the concave portion and bites into a wedge shape. Pad 7 of solder ball 11
This increases the close contact with the ball, thereby increasing the shear strength of the ball (see FIG. 8).

The via 6 may be buried with resin, metal, or the like to form a planar shape (see FIG. 7). In this case, the processing of the solder paste or the like is facilitated, and another advantage is obtained when the via is not buried. can get. Whether the recess is to be embedded or not to be embedded may be appropriately selected depending on the mounting method, material, and the like.

When the semiconductor chip 10 is mounted using the substrate for an air rear grid array package of the present invention, the chip 10 is formed by lands 9 and wirings formed on the second layer 2 by wire bonding or bumps 12 or the like. 8
And then sealed with a sealing material 13.
When the solder ball 11 is placed in the recess of the via 6 as described above and is melted, the solder ball 11 is
The solder balls 11 serve to increase the shear strength of the solder balls 11. In FIG. 8, 14 is a motherboard, 1
5 indicates a pad.

The substrate for an air rear grid array of the present invention can be processed in a panel shape or can be continuously processed using a flexible tape.

[0033]

Embodiment 1 An example of manufacturing a substrate for an air rear array package according to the present invention is as follows. The laminated substrate used here has a first surface (a lower surface in the figure) with the insulating layer 3 interposed therebetween.
A first layer 1 and a second layer 2 formed by laminating a copper foil (about 12 μm) are formed on the second surface (upper surface in the figure) and have a three-layer structure (see FIG. 1). The insulating layer 3 is made of an epoxy resin as a resin component and an aramid fiber (copolyparaphenylene / 3,4'oxydiphenylene terephthalamide) as a reinforcing material.
(Thickness: about 0.1 mm).

The copper foil 1 as the first layer of the laminated base is
First, an opening 16 (diameter: about 0.2 mm) is formed at lattice points (pitch: about 1 mm) by etching (see FIG. 2), and then a KrF excimer laser is irradiated from above to pass through the insulating layer 3 to form Perforations are made until the back surface of the copper foil 2 as two layers is reached, and a via hole 4 is formed. The shape of the hole is a tapered cross section (taper angle of about 6 °) tapering toward the second layer 2 as described above (FIG. 3).
reference).

Subsequently, via-hole plating with ordinary copper sulfate is performed on the first layer copper foil 1 in which the via-holes 4 are opened (the thickness of the plating film is about 10 μm). At this time, the copper foil 2 of the second layer was masked with a dry film so as not to be plated. As a result, the via holes 4 are plated with the via holes 5 to form the vias 6, and the plating 5 adheres to the first layer copper foil 1 (see FIG. 4).

Thereafter, a resist is coated on each of the copper foils 1 and 2 as the first and second layers by an electrodeposition method (thickness: about 8 μm), and pattern etching with ferric chloride is performed. At this time, on one side of the first layer, the copper foil 1 and the plating 5 are etched, and the pad 7 is centered on each via 6.
Is formed (diameter about 0.5 mm). On the other side of the second layer, the copper foil 2 is etched to form lands 9 and wirings 8 for connection to the respective leads of the semiconductor chip 10.

On the second layer side, the plating for the via hole did not adhere to this surface, so that the thickness ( about 1
2 μm) is kept thin, and fine wiring 8 is formed (the minimum value of line / space is about 50 μm / 5).
0 μm). Moreover, each via 6 is tapered toward the second layer.
Since the cross section is tapered, the size of the land 9 in the second layer connected to the inner bottom of the via 6 can be extremely reduced (diameter of about 250 μm). As a result, the fine wiring (line) / Minimum value of space is about 5
(0 μm / 50 μm) could be easily formed.

[0038]

According to the present invention, a high-density air rear grid which can mount a multi-pin semiconductor chip by simple means is provided.
An array package substrate can be obtained.

That is, in this kind of conventional technology, it is difficult to route wiring and it is difficult to cope with a multi-pin semiconductor chip.
The cost is high, the second conductive layer is thick, and it is difficult to obtain fine wiring connecting to the semiconductor chip, and the pad has a planar structure, so that the shear strength after mounting solder balls or solder paste attached thereto is low. Or easily peeled off due to heat or stress.

On the other hand, in the present invention, the first layer
By forming a tapered via toward the layer and integrating it with the second layer, the semiconductor chip can be connected to a wiring formed by etching the second layer. Therefore, there is no problem of wiring management, and it is possible to sufficiently cope with a multi-pin semiconductor chip.

Also, by plating via holes only on the first layer where the holes are opened, the thickness of the second layer can be kept thin as it is, and fine wiring can be formed. It can sufficiently cope with a semiconductor chip having pins.

Further, the shape of the via is changed from the first layer to the second layer 2.
Since the cross-section is tapered toward the bottom, the land portion of the second layer connected to the inner bottom of the via can be formed small, and fine wiring can be easily formed from this surface, and the number of pins can be increased. Of semiconductor chips.

Furthermore, if the substrate of the ball grid array package is formed by leaving the pad of the first layer as a recess without embedding a via, the solder ball melts into the recess and bites into a wedge shape, so that the solder ball adheres to the pad. As a result, the shear strength of the ball can be increased, and the resist for preventing the outflow of the solder ball can be eliminated.

In addition, when resin and metal are buried in the via to form a planar shape, connection with solder paste can be facilitated.

[Brief description of the drawings]

FIG. 1 is an enlarged longitudinal sectional view of a part of a laminated substrate used for manufacturing a substrate for a ball grid array package according to the present invention.

FIG. 2 is an enlarged longitudinal sectional view showing a state where an opening is formed in a part of a first layer of the laminated substrate shown in FIG. 1;

FIG. 3 is an enlarged vertical sectional view showing a state in which a via hole is formed in the laminated substrate shown in FIG. 2;

FIG. 4 is an enlarged vertical sectional view showing a state where plating for via holes is applied to the laminated substrate shown in FIG. 3;

FIG. 5 is an enlarged vertical sectional view showing a state where pads, lands and wirings are formed by etching the laminated substrate shown in FIG. 4;

6 is an enlarged vertical sectional view showing a state in which a semiconductor chip is mounted on the laminated substrate shown in FIG. 5 with bumps.

FIG. 7 is a partially enlarged longitudinal sectional view when a via is buried to form a planar pad.

FIG. 8 is an enlarged vertical cross-sectional view of a part of a state in which a solder ball is melted when a via is not embedded and a pad is a concave portion.

[Explanation of symbols]

1-first layer 6-via 11
-Solder ball 2-second layer 7-pad 12
-Bump 3-Insulating layer 8-Wiring 13
-Sealing material 4-via hole 9-land 14
-Motherboard 5-Plating for via hole 10-Semiconductor chip 15
-Pad 16-Opening

Claims (4)

(57) [Claims] An air rear grid comprising a first layer having pads and a second layer on which a semiconductor chip is mounted, with an insulating layer interposed therebetween, wherein the first layer and the second layer are connected to each other. in the substrate for the array package, from a portion of the first layer side pad, the second layer through the insulation layer
And a tapered via tapered toward the second layer side is formed to be integrated with a part of the wiring of the second layer. , Substrate for air rear grid array package. 2. The substrate for an air rear grid array package according to claim 1, wherein the recess is formed in the pad without filling the via. 3. A substrate for an air rear grid array package according to claim 1, wherein the via is buried to form a planar pad. 4. An insulating layer is perforated by laser processing from the first layer side.
To reach the back surface of the second layer and taper toward the second layer.
After the formation of the cross-section tapered via hole becomes Jo,
Plating for via holes is performed from the side where the via holes are opened, and then both sides are etched to form pads arranged in a grid on the first layer, and wiring to the semiconductor chip is formed on the second layer. Characterized in that it is formed
A method for manufacturing a substrate for an air rear grid array package.