JP2021168349A - Component built-in wiring board - Google Patents

Abstract

To improve quality of a component built-in wiring board.SOLUTION: A component built-in wiring board 100 in an embodiment includes: a core substrate 6 having a through-hole 60; an electronic component 5 disposed in the through-hole 60; a resin body 40 filling a space between an inner wall of the through-hole 60 and the electronic component 5; a first insulation layer 41 laminated on a surface of the core substrate 6 and on a surface of the electronic component 5; a first conductor layer 1 formed on a surface of an opposite side to the core substrate 6 of the first insulation layer 41; and a second conductor layer 2 formed on the first insulation layer 41 and the first conductor layer 1 via an insulation layer 42 different from the first insulation layer 41. A residual copper ratio of the first conductor layer 1 in a region overlapping with the through hole 60 in a plan view is smaller than that of the second conductor layer 2 in a region overlapping with the through hole 60 in a plan view.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board with built-in components.

Patent Document 1 discloses a wiring board with a built-in electronic component including an electronic component arranged in a cavity provided in an insulating layer. The space around the electronic component in the cavity is filled with an adhesive layer made of polymer and an insulator made of resin. These adhesive layers and insulators are covered with a conductor pattern formed on the insulating layer at the opening of the cavity.

Japanese Unexamined Patent Publication No. 2012-204831

In the wiring board with built-in electronic components disclosed in Patent Document 1, gas may be generated from the polymer or resin that fills the inside of the cavity as an adhesive layer or an insulator, and the inner wall of the cavity. The gas generated inside the cavity in this way may deteriorate the quality of the wiring board.

The component-embedded wiring board of the present invention includes a core substrate having a through hole, an electronic component arranged in the through hole, a resin body that fills the space between the inner wall of the through hole and the electronic component, and the core. The first insulating layer laminated on the surface of the substrate and the surface of the electronic component, the first conductor layer formed on the surface of the first insulating layer opposite to the core substrate, and the above. It includes the first insulating layer and a second conductor layer formed on the first conductor layer via an insulating layer different from the first insulating layer. The residual copper ratio of the first conductor layer in the region overlapping the through hole in the plan view is smaller than the residual copper ratio of the second conductor layer in the region overlapping the through hole in the plan view.

According to the embodiment of the present invention, it may be possible to suppress the deterioration of the quality of the component-embedded wiring board due to the gas generated around the electronic component.

FIG. 5 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. The plan view which shows an example of the conductor pattern of the 1st conductor layer in the wiring board of one Embodiment of this invention. The plan view which shows an example of the conductor pattern of the 2nd conductor layer in the wiring board of one Embodiment of this invention. The plan view which shows another example of the conductor pattern of the 1st conductor layer in the wiring board of one Embodiment of this invention. The plan view which shows another example of the conductor pattern of the 2nd conductor layer in the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention. The cross-sectional view which shows an example of the manufacturing process of the wiring board of one Embodiment of this invention.

A component-embedded wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross section of a component-embedded wiring board 100 (hereinafter, also simply referred to as “wiring board 100”), which is an example of the component-embedded wiring board of one embodiment. Further, FIGS. 2A and 2B show an example of the conductor pattern of the peripheral portion of the through hole 60 in the component-embedded wiring board of one embodiment. FIG. 2A shows an example of the conductor pattern of the first conductor layer 1, and FIG. 2B shows an example of the conductor pattern of the second conductor layer 2.

As shown in FIG. 1, the wiring board 100 includes a core board 6 having two surfaces (first surface 6a and second surface 6b) facing each other in the thickness direction thereof, an electronic component 5, and a core board 6. An insulating layer (first insulating layer 41, second insulating layer 42, etc.) and a conductor layer (first conductor layer 1, second conductor layer 2, etc.) laminated on each of the first surface 6a and the second surface 6b. And, including. The insulating layer and the conductor layer are laminated alternately. The core substrate 6 includes an insulating layer 61 forming the core thereof and a conductor layer (core substrate conductor layer) 62 formed on both sides of the insulating layer 61. The core substrate 6 has a through hole 60 that penetrates the core substrate 6 in the thickness direction. The electronic component 5 is arranged inside the through hole 60. Since the outer shape of the electronic component 5 is smaller than that of the through hole 60 in a plan view, there is a gap (space) between the electronic component 5 and the inner wall of the through hole 60. The wiring board 100 includes a resin body 40 that fills the space between the electronic component 5 and the inner wall of the through hole 60.

In the above and the following description, "planar view" means to see the component-embedded wiring board 100 so that the line of sight is along the thickness direction of the component-embedded wiring board 100. Further, the side far from the insulating layer 61 in the thickness direction of the wiring board 100 is also referred to as "upper" or "upper", or simply "upper", and the side closer to the insulating layer 61 is "lower" or "lower". Or simply referred to as "below". Further, in each conductor layer and each insulating layer, the surface facing the side opposite to the insulating layer 61 is also referred to as "upper surface", and the surface facing the insulating layer 61 side is also referred to as "lower surface". Further, the thickness direction of the wiring board 100 is also simply referred to as "Z direction".

The first insulating layer 41 is laminated on the surface (first surface 6a) of the core substrate 6 and on the surface of the electronic component 5 on the first surface 6a side. The first conductor layer 1 is formed on the surface of the first insulating layer 41 opposite to the core substrate 6. Further, a second conductor layer 2 is formed on the first insulating layer 41 and the first conductor layer 1 via a second insulating layer 42 which is an insulating layer different from the first insulating layer 41. .. The second insulating layer 42 is an insulating layer laminated on the first insulating layer 41 and the first conductor layer 1. The first surface 6a and the second surface 6b of the core substrate 6 are covered with the conductor layer 62 of the surface of the conductor layer 62 orthogonal to the Z direction and the surface of the insulating layer 61 orthogonal to the Z direction, respectively. It consists of unbroken parts.

The wiring board 100 of FIG. 1 further includes an insulating layer 43 laminated on the second insulating layer 42 and the second conductor layer 2, and a conductor layer 3 formed on the insulating layer 43. The conductor layer 3 is provided with a conductor pad 3a. The conductor pad 3a can be used, for example, as a mounting pad for mounting an external electronic component on the wiring board 100.

The wiring board 100 of the present embodiment further includes a via conductor (first via conductor) 7 that penetrates the first insulating layer 41 and connects the first conductor layer 1 and the electrode 5a of the electronic component 5. The wiring board 100 of FIG. 1 is further provided with a via conductor 71 that penetrates each insulating layer and connects a conductor layer formed on the upper side and a conductor layer formed on the lower side of each insulating layer. Has been done. Further, the core substrate 6 includes a through-hole conductor 63 that connects the conductor layer 62 on the first surface 6a side and the conductor layer 62 on the second surface 6b side.

The wiring board 100 of FIG. 1 also has a plurality of insulating layers and conductor layers alternately laminated on the second surface 6b side of the core board 6. A conductor layer 31, a conductor layer 32, and a conductor layer 33 are formed as conductor layers on the second surface 6b side of the wiring board 100 of FIG. 1 in this order from the second surface 6b side. An insulating layer 44 is interposed between the conductor layers and between the conductor layer 31 and the core substrate 6. The conductor layer 33 includes a conductor pad 33a. The conductor pad 33a is used, for example, as a connection pad for connecting the wiring board 100 and the external wiring board.

The resin body 40 is provided so as to fill the space inside the through hole 60, particularly the space not occupied by the electronic component 5 in the inside of the through hole 60, with resin. The resin body 40 fills the gap (space) between the electronic component 5 and the inner wall of the through hole 60 in the through hole 60. Further, the electronic component 5 is fixed at a predetermined position in the through hole 60.

In the example of FIG. 1, the resin body 40 is integrally formed with the first insulating layer 41. In other words, a part of the first insulating layer 41 fills the space between the inner wall of the through hole 60 and the electronic component 5. It is considered that the resin body 40 is easily formed and the resin body 40 and the first insulating layer 41 are unlikely to be separated from each other.

The first and second insulating layers 41, 42 and the insulating layers 43, 44, 61 are formed of any insulating resin. Examples of the insulating resin include epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. The resin body 40 is also composed of any resin such as these epoxy resins and BT resins. In the example of FIG. 1, the insulating layer 61 includes a core material (reinforcing material) 61a formed of glass fiber or aramid fiber. The first and second insulating layers 41, 42, the insulating layers 43, 44, 61, and the resin body 40 may further contain an inorganic filler. Examples of the inorganic filler contained in each insulating layer and the resin body 40 include _{fine particles made of silica (SiO 2} ), alumina, mullite, and the like.

The first and second conductor layers 1 and 2, the conductor layers 3, 31 to 33, 62, the via conductors 7, 71, and the through-hole conductor 63 are formed by using any metal such as copper or nickel. Each of these conductor layers, each via conductor, and the through-hole conductor 63 may include a plurality of metal layers. For example, each conductor layer, each via conductor, and the through-hole conductor 63 are a metal film layer made of an electroless plating film or a sputtering film, and a plating film layer formed by electrolytic plating using the metal film layer as a feeding layer. May include. Each conductor layer, particularly the conductor layer 62, may be provided with a metal foil layer made of copper foil, nickel foil, or the like under the metal film layer.

The electronic component 5 is an arbitrary component that can be generally mounted on a wiring board. For example, passive components such as resistors and capacitors, active components such as transistors, diodes, or semiconductor integrated circuit devices, or wiring arranged according to rules finer than the wiring rules applied to the wiring board 100 is placed on the base material. Examples of wiring parts and the like prepared for the above.

The electronic component 5 in the example of FIG. 1 includes an electrode 5a used for connecting the electronic component 5 and an external circuit. The electrode 5a and the via pad 11a provided on the first conductor layer 1 are connected by the via conductor 7. The electrode 5a can be electrically connected to any conductor layer, for example, the conductor pad 3a of the conductor layer 3, as in the example of FIG. 1, via the via pad 11a. The electrode 5a and the conductor pad 3a can be connected at the shortest distance. Further, the electrode 5a can be connected to the solid pattern 21b of the second conductor layer 2 which can function as a power source or a ground as described later at the shortest distance.

The wiring board 100 of FIG. 1 further includes a solder resist 8. The solder resist 8 covers the outermost conductor layer and the insulating layer on the first surface 6a side and the second surface 6b side of the core substrate 6 of the wiring board 100, respectively. The solder resist 8 on the first surface 6a side covers the insulating layer 43 and partially covers the conductor layer 3. The solder resist 8 on the second surface 6b side covers the insulating layer 44 on the most surface layer side and partially covers the conductor layer 33. The solder resist 8 is formed by using an arbitrary insulating material such as an epoxy resin or a polyimide resin.

The solder resist 8 on the first surface 6a side is provided with an opening for exposing the conductor pad 3a. Further, the solder resist 8 on the second surface 6b side is provided with an opening for exposing the conductor pad 33a. Bumps 3b are provided in each opening of the solder resist 8. The bumps 3b are used for connecting the conductor pads 3a and 33a to, for example, an external electronic component or a wiring board. The bump 3b can be formed of a metal such as solder, copper, or gold, or a conductive resin containing metal particles.

The wiring board 100 illustrated in FIG. 1 has substantially the same structure on the first surface 6a side and the second surface 6b side of the core substrate 6. In the following, the structure on the first surface 6a side and the actions and effects brought about by the structure will be mainly described. The structures and features described for the first surface 6a side may also apply to the second surface 6b side.

An arbitrary conductor pattern is provided for each of the conductor layers such as the first conductor layer 1 and the second conductor layer 2. The conductor pattern provided in each conductor layer includes a signal wiring pattern that functions as wiring for transmitting various signals, a mounting pad (connection pad) used for connecting to an external element such as a conductor pad 3a, and a via pad 11a. As described above, a via pad or the like provided for a secure connection between each via conductor and each conductor layer is exemplified. Further, each conductor layer may be provided with a power supply pattern and a ground pattern that each function as a power source or ground for power supply.

Each of these conductor patterns is appropriately provided so as to have a desired or predetermined size (length and width, etc.) and shape. In particular, the power supply pattern and / or the ground pattern not only connects the power transmission side and the power reception side with a conductor having a predetermined width, but also spreads in a plane so as to occupy a predetermined area, that is, forms a solid pattern. It may be preferable to be provided in.

In the wiring board 100, as shown in FIG. 2A, only the via pad 11a and the signal wiring pattern 11b are provided in the through hole 60 and the first conductor layer 1 in the peripheral portion thereof in a plan view. On the other hand, as shown in FIG. 2B, a via pad 21a and a solid pattern 21b are provided in the through hole 60 and the second conductor layer 2 in the peripheral portion thereof in a plan view. The solid pattern 21b is provided over the entire region shown in FIG. 2B except for the via pad 21a and the inter-pattern clearance (gap portion 22) around each via pad 21a.

In the present embodiment, as shown in FIGS. 2A and 2B, the residual copper ratio of the first conductor layer 1 in the region overlapping the through hole 60 in the plan view is the second conductor in the region overlapping the through hole 60 in the plan view. It is smaller than the residual copper ratio of layer 2. In each of the first conductor layer 1 and the second conductor layer 2 of the wiring board 100, the "region overlapping with the through hole 60 in a plan view" (hereinafter, also simply referred to as "region A") is provided in FIGS. 2A and 2B, respectively. It is an area surrounded by a broken line indicating the through hole 60 shown. The "residual copper ratio" of each conductor layer is the area of the conductor portion (conductor pattern) in the target region of each conductor layer with respect to the area of a specific target region (for example, the above-mentioned "region overlapping with the through hole 60 in a plan view"). It is the ratio of the total area. The term "residual copper ratio" is used only for convenience, and as described above, the material of each conductor layer is not limited to copper.

In the example of FIG. 2A, the conductor pattern of the first conductor layer 1 provided in the region A is only four via pads 11a. On the other hand, in the example of FIG. 2B, two via pads 21a and a solid pattern 21b surrounding each via pad 21a are provided in the region A. The solid pattern 21b is provided in the entire region A other than the two via pads 21a and the gap 22. That is, in the second conductor layer 2, a conductor pattern is formed in a portion other than the two gap portions 22 in the region A. Therefore, in the wiring board 100, the residual copper ratio of the first conductor layer 1 in the region A is smaller than the residual copper ratio of the second conductor layer 2 in the region A.

In the wiring board 100 of the present embodiment, the residual copper ratio of the entire first conductor layer 1 may be smaller than the residual copper ratio of the entire second conductor layer 2. The "total residual copper ratio" of each of the first conductor layer 1 and the second conductor layer 2 is the surface of each of the insulating layers in which each conductor layer is formed (the first insulating layer 41 facing the first conductor layer 1). This is the residual copper ratio when the entire surface (the surface and the surface of the second insulating layer 42 facing the second conductor layer 2) is the above-mentioned “target region”.

The advantage that the residual copper ratio of the first conductor layer 1 is lower than the residual copper ratio of the second conductor layer 2 will be described below. As described above, the resin body 40 that fills the through hole 60 of the core substrate 6, the insulating layer 61 of the core substrate 6, and the first insulating layer 41 that covers the electronic component 5 are made of any resin such as epoxy resin. Can be done. A resin such as an epoxy resin may generate gas, for example, due to a change in ambient temperature during the manufacturing stage or use of the wiring board 100. Further, the inside of the through hole 60 may not be filled to every corner by the resin body 40, and as a result, air bubbles (voids) may be present in the through hole 60. Even on the surface of the electronic component 5, recesses and the like that may exist on the surface of the electronic component 5 are not completely filled by the first insulating layer 41, and as a result, on the surface of the electronic component 5 and inside the first insulating layer 41. Voids may occur.

The gas generated inside the through hole 60 or in the first insulating layer 41 goes to the second insulating layer 42 from the inside of the through hole 60 or on the surface of the electronic component 5 so as to flow out to the outside of the wiring board 100. There is. Further, the voids existing inside the resin body 40 and the first insulating layer 41 in the through hole 60 may expand as the ambient temperature rises, for example. When gas is generated or voids are expanded in this way, a force that pushes the first conductor layer 1 toward the second insulating layer 42 may be applied by the gas or voids that come into contact with the first conductor layer 1. .. If a large conductor pattern is provided in the region of the first conductor layer 1 that overlaps the through hole 60 in a plan view, it is considered that such a force due to gas or void is likely to be widely applied to the conductor pattern. .. As a result, the first conductor layer 1 may be peeled off from the surface of the first insulating layer 41, and the conductor pattern may be broken due to the peeling.

However, in the present embodiment, the residual copper ratio of the first conductor layer 1 in the region (region A) overlapping the through hole 60 in a plan view is smaller than the residual copper ratio of the second conductor layer 2 in the region A. That is, the first and second conductor layers 1 and 2 include the gap portions 12 and 22 other than the conductor portion and the conductor portion, respectively, and in the region A, the gap portion 22 provided in the second conductor layer 2 The void portion 12 is provided in the first conductor layer 1 with a larger area. Therefore, it is considered that the above-mentioned gas easily moves from the first insulating layer 41 to the second insulating layer 42, and the voids that expand in the first insulating layer 41 easily spread to the second insulating layer 42.

In other words, in the wiring board 100 of the present embodiment, each conductor pattern of the first conductor layer 1 is wider than that of the case where the first conductor layer 1 has a higher residual copper ratio than the second conductor layer 2. It is thought that it is unlikely to receive the force of gas or voids over it. That is, in the present embodiment, it is considered that an excessive force enough to peel off from the first insulating layer 41 is unlikely to be applied to each conductor pattern of the first conductor layer 1. Therefore, it is considered that the wiring board 100 of the present embodiment has less peeling and disconnection of the conductor pattern of the first conductor layer 1, and the quality can be improved as compared with the conventional wiring board with built-in components.

When the gas generated in the through hole 60 or the like moves in the first insulating layer 41 and the second insulating layer 42 and reaches the second conductor layer 2, the gas is more likely to reach the first conductor layer 1 than when it reaches the first conductor layer 1. It is considered that many are dispersed in the direction orthogonal to the Z direction. Therefore, it is considered that a larger force due to the gas is less likely to be locally applied to the second conductor layer 2 than to the first conductor layer 1. Therefore, even if the residual copper ratio of the second conductor layer 2 is higher than the residual copper ratio of the first conductor layer 1, there is less peeling or disconnection of the conductor pattern of the entire wiring board 100 as compared with the opposite case. Conceivable.

As described above, in the region shown in FIG. 2A, the first conductor layer 1 is provided with only the via pad 11a and the signal wiring pattern 11b as conductor patterns. In addition, the first conductor layer 1 does not include a solid pattern in the region (region A) that overlaps the through hole 60 in a plan view. It is considered that the conductor pattern of the first conductor layer 1 is not widely affected by gases and voids that are likely to be generated in the through hole 60. The first conductor layer 1 does not have to include a solid pattern at all not only in the region A but also in the entire first conductor layer 1. The first conductor layer 1 may be a signal layer in which a signal wiring pattern is mainly provided on the wiring board 100.

On the other hand, as described above, the second conductor layer 2 includes a solid pattern 21b, which is a conductor pattern provided so as to occupy a predetermined region and spreads in a plane shape. The solid pattern 21b can function well as a power source or ground. The second conductor layer 2 may be a power supply layer mainly provided with a power supply pattern on the wiring board 100, or a ground layer mainly provided with a ground pattern. Therefore, in the second conductor layer 2, the area of the solid pattern 21b may be larger than the area of a conductor pattern other than the solid pattern 21b (for example, a conductor pattern that functions as a wiring for transmitting a signal). When the first conductor layer 1 does not include many power supply patterns and ground patterns, the second conductor layer 2 including the solid pattern 21b that functions as a power supply and ground may improve the electrical characteristics of the component-embedded wiring board 100. .. In the example shown in FIG. 2B, the solid pattern 21b of the second conductor layer 2 overlaps the through hole 60 in a plan view. When the first conductor layer 1 does not include a solid pattern in the region A, the second conductor layer 2 including the solid pattern 21b that overlaps the through hole 60 in a plan view is considered to be particularly preferable for the stable operation of the electronic component 5.

Further, in the wiring board 100 of the present embodiment, the area of the conductor pattern in which at least a part of the first conductor layer 1 is arranged in the area A is such that at least a part of the area of the conductor pattern is arranged in the area A in the second conductor layer 2. It may be smaller than the area of the conductor pattern (hereinafter, "a conductor pattern in which at least a part is arranged in the region A" in each conductor layer is also simply referred to as an "intra-region conductor"). Even if it is an intra-regional conductor of the first conductor layer 1, it is considered that the intra-regional conductor having a relatively small area is not widely subjected to the force due to the gas or void inside the through hole 60. Therefore, it is considered that problems such as peeling of the conductor pattern of the first conductor layer 1 are unlikely to occur. Further, by making the area of the conductor in the region of the first conductor layer 1 smaller than that of the conductor in the region of the second conductor layer 2, in the region A of the first conductor layer 1, in the region A of the second conductor layer 2. A residual copper ratio smaller than the residual copper ratio may be realized.

In addition, a plurality of in-region conductors may be provided in each of the first and second conductor layers 1 and 2. In that case, the largest in-region conductor in the first conductor layer 1 may be smaller than the largest in-region conductor in the second conductor layer 2. That is, the area of each of the one or more conductor patterns that at least partially overlap the through hole 60 in the first conductor layer 1 in the plan view is the conductor pattern that at least partially overlaps the through hole 60 in the second conductor layer 2 in the plan view. It may be smaller than the area of the largest conductor pattern. Problems such as peeling of the conductor pattern of the first conductor layer 1 may be unlikely to occur.

In FIGS. 2A and 2B, the space 64 between the outer edge of the electronic component 5 and the inner wall of the through hole 60 is filled with the resin body 40 as shown in FIG. The resin body 40 has substantially the same length as the thickness of the core substrate 6 in the Z direction. Therefore, in the Z direction, the amount of shrinkage of the resin body 40 due to, for example, a temperature change may be larger than the amount of shrinkage of the first insulating layer 41. Therefore, it is considered that a concave portion or a convex portion may be formed on the surface of the first insulating layer 41 directly above the space 64. Further, it is considered that the above-mentioned gas and voids are likely to be generated in the space 64 containing a large amount of resin. Therefore, when the conductor pattern of the first conductor layer 1 is provided in the region overlapping the space 64 in a plan view, the conductor pattern is affected by the above-mentioned gas and voids and the unevenness of the surface of the first insulating layer 1. It is considered to be easily affected.

In this regard, in the example shown in FIG. 2A, the void portion 12 of the first conductor layer 1 includes the entire space 64 in a plan view. That is, the first conductor layer 1 is not provided with a conductor pattern in a region overlapping the space 64 in a plan view. Therefore, in the region overlapping the space 64, a defect related to the conductor pattern of the first conductor layer 1 cannot occur. As will be described later with reference to FIG. 3, the gap portion 12 does not necessarily include the entire space 64 in a plan view.

On the other hand, the second conductor layer 2 exemplified in FIG. 2B includes a conductor pattern (solid pattern 21b) that overlaps with the space 64 in a plan view. Even if the conductor pattern is not provided in the region of the first conductor layer 1 that overlaps with the space 64 in a plan view, the desired electric power or signal can be supplied to the electronic component 5. In particular, in the example of FIG. 2, the solid pattern 21b overlaps the entire space 64 in a plan view. For example, it may be possible to supply stable electric power to the electronic component 5.

FIG. 3 shows another example of the conductor pattern of the peripheral portion of the through hole 60 in the first conductor layer 1. In the example of FIG. 3, the gap portion 12 does not include the entire space 64 in a plan view, but partially includes the space 64. That is, the first conductor layer 1 in the example of FIG. 3 is provided with a signal wiring pattern 11c that overlaps with the space 64 in a plan view. However, even in the example of FIG. 3, the entire space 64 is not covered by the conductor pattern of the first conductor layer 1. Therefore, for example, the gas generated in the through hole 60 or the first insulating layer 41 can move from the portion not covered by the signal wiring pattern 11c to the second insulating layer 42 (see FIG. 1). Therefore, even in the example of FIG. 3, it is considered that the disconnection of the conductor pattern of the first conductor layer 1 is reduced as compared with the case where the space 64 is completely covered by the conductor pattern of the first conductor layer 1. .. As in the example of FIG. 3, the gap portion 12 of the first conductor layer 1 may include the space 64 at least partially in a plan view.

Even when the signal wiring pattern 11c is provided on the first conductor layer 1 as in the example of FIG. 3, the solid pattern 21b may be provided on the second conductor layer 2 as in the example of FIG. 2B, for example. In that case, the second conductor layer 2 may include a conductor pattern (solid pattern 21b) that overlaps in a plan view with a region included in the gap portion 12 of the first conductor layer 1 in the space 64 in a plan view. That is, the second conductor layer 2 may have a conductor pattern (solid pattern 21b) even in a region where the conductor pattern is not provided on the first conductor layer 1 in a plan view. For example, it is considered that stable electric power can be supplied to the electronic component 5 via the solid pattern 21b.

In the example of FIG. 3, the signal wiring pattern 11c is the largest in-region conductor in the first conductor layer 1. Even in the combination of the first conductor layer 1 in the example of FIG. 3 and the second conductor layer 2 in the example of FIG. 2B, the largest in-region conductor (signal wiring pattern 11c) in the first conductor layer 1 is the second conductor layer. It is smaller than the largest in-region conductor (solid pattern 21b) in 2.

Further, in the example of FIG. 3, the first conductor layer 1 includes a solid pattern 11d which is provided outside the region A in a plan view so as to occupy a predetermined region and spreads in a plane shape. However, since the solid pattern 11d does not overlap with the region A, peeling of the solid pattern 11d is unlikely to occur in the first conductor layer 1.

When the first conductor layer 1 includes the solid pattern 11d as in the example of FIG. 3, the solid pattern 11d and the solid pattern 21b of the second conductor layer 2 (see FIG. 2B) are conductor patterns to which different potentials are applied. There may be. For example, one of the solid pattern 11d and the solid pattern 21b may be a conductor pattern to which the highest potential of the potentials applied to the wiring board 100 should be applied. The other of them may be a conductor pattern to which the lowest potential of the potentials applied to the wiring board 100 should be applied. For example, one of the solid pattern 11d and the solid pattern 21b may be a conductor pattern that functions as a power supply plane, and the other may be a conductor pattern that functions as a ground plane.

FIG. 4 shows another example of the conductor pattern of the peripheral portion of the through hole 60 in the second conductor layer 2. In the example of FIG. 4, the solid pattern 21b of the second conductor layer 2 is provided with a penetrating portion 21c penetrating the solid pattern 21b. The penetrating portion 21c is a portion other than the conductor portion like the gap portion 22, and the second insulating layer 42 and the insulating layer 43 (see FIG. 1) can come into contact with each other through the penetrating portion 21c. However, unlike the gap portion 22 around the via pad 21a, the penetrating portion 21c does not include the conductor pattern of the second conductor layer 2 like the via pad 21a.

As described above, even if the second conductor layer 2 contains the solid pattern 21b in the region A and its peripheral portion, the conductor pattern is less likely to be broken as compared with the case where the first conductor layer 1 contains the solid pattern. .. However, if the gas generated in the second insulating layer 42 and / or the gas transferred from the first insulating layer 41 into the second insulating layer 42 can easily move to the insulating layer 43, the second conductor layer In 2, it is considered that disconnection of the conductor pattern is less likely to occur. It is considered that the provision of the penetrating portion 21c in the solid pattern 21b of the second conductor layer 2 facilitates the movement of the gas in the second insulating layer 42 to the insulating layer 43 through the penetrating portion 21c. Therefore, it is considered that defects related to the second conductor layer 2 are less likely to occur, and the quality of the wiring board 100 is further improved. The shape, size, arrangement density, and the like of the penetrating portion 21c in the example of FIG. 4 are only examples. The penetration 21c can be provided in any shape, size and placement density.

Next, an example of a method of manufacturing the component-embedded wiring board of one embodiment will be described with reference to FIGS. 5A to 5H, using the case where the wiring board 100 of FIG. 1 is manufactured as an example.

As shown in FIG. 5A, a starting substrate 600 including an insulating layer 61 and metal foils 620 laminated on both surfaces of the insulating layer 61 is prepared. For example, a double-sided copper-clad laminate in which copper foils are pressure-bonded to both sides of a glass epoxy substrate containing a reinforcing material 61a is prepared as a starting substrate 600.

As shown in FIG. 5B, the core substrate 6 is formed. For example, a through hole is formed at a position where the through hole conductor 63 is formed on the starting substrate 600 by drilling or irradiation with a carbon dioxide laser beam, and a metal film is formed in the through hole and on the metal foil 620 by electroless plating or sputtering. It is formed. Then, a plating film is formed by electrolytic plating using this metal film as a feeding layer. As a result, the conductor layer 62 and the through-hole conductor 63 are formed. Then, by patterning the conductor layer 62 by the subtractive method, a core substrate 6 having a predetermined conductor pattern on the first surface 6a and the second surface 6b can be obtained. In the example of FIG. 5B, on each of the first surface 6a side and the second surface 6b side, the conductor layer 62 in the region where the through hole 60 is formed in the subsequent process and the region around the region is gradually removed by patterning.

As shown in FIG. 5C, a through hole 60 is formed in the core substrate 6. For example, the insulating layer 61 is irradiated with a laser beam such as a carbon dioxide gas laser or a YAG laser along the contour of the through hole 60 to be formed, and the region corresponding to the through hole 60 is removed from the core substrate 6. As a result, the through hole 60 is formed. The through hole 60 is not limited to irradiation with laser light, and may be formed by any method such as drilling.

Subsequently, as shown in FIG. 5D, the electronic component 5 is arranged in the through hole 60. Specifically, for example, a carrier C made of PET (polyethylene terephthalate) is provided on the second surface 6b side of the core substrate 6. As a result, as shown in FIG. 5D, the opening on the second surface 6b side of the through hole 60 is closed. The carrier C is made of, for example, an adhesive sheet having adhesiveness on at least one surface, and the adhesive surface is adhered to the core substrate 6. Then, the electronic component 5 is placed on one surface of the carrier C exposed in the through hole 60 by using, for example, a chip mounter.

As shown in FIG. 5E, the resin formed into a film in a semi-cured state is placed on the first surface 6a of the core substrate 6 and on the surface of the electronic component 5 and pressed toward the core substrate 6. And heated. As a result, the first insulating layer 41 is formed on the first surface 6a. Further, by this pressurization and heating, the semi-cured resin formed in a film shape is softened, and a part thereof is inside the through hole 60, specifically, the inner wall of the electronic component 5 and the through hole 60. It flows into the gap with. The space between the electronic component 5 and the inner wall of the through hole 60 is filled with the resin constituting the first insulating layer 41, and the resin body 40 made of the resin is formed. Further, the electronic component 5 is supported by the resin body 40 in the through hole 60. After that, the carrier C is removed.

As shown in FIG. 5F, the insulating layer 44 is formed on the second surface 6b of the core substrate 6. For example, as in the case of forming the first insulating layer 41, the resin formed in a film shape in a semi-cured state is placed on the second surface 6b, and is heated and pressurized. The film-like resin placed on the second surface 6b is cured, and the insulating layer 44 made of the resin is formed. At that time, the insulating layer 44 and the resin body 40 may be fused. The first insulating layer 41 and the resin body 40 may not be completely cured in the state of FIG. 5E, or may be completely cured by heating during the formation of the insulating layer 44.

As shown in FIG. 5G, the first conductor layer 1 is formed on the first insulating layer 41, and the via conductor 7 and the via conductor 71 are formed. For example, by irradiating carbon dioxide laser light, a via hole 70 for arranging the via conductors 7 and 71 is formed in the first insulating layer 41. Subsequently, for example, by electroless plating or sputtering, a metal film made of copper, for example, is formed on the first insulating layer 41 and in the via hole 70. Then, a plating resist (not shown) having an appropriate opening is formed on the metal film by using, for example, a photolithography technique. Then, the plating film is formed in the opening of the plating resist by electrolytic plating using the metal film under the plating resist as a feeding layer. A via conductor 7 and a via conductor 71 are formed in the via hole 70.

After that, the plating resist is removed, and the metal film exposed by the removal is removed by, for example, etching. As a result, the first conductor layer 1 including a desired conductor pattern such as the via pad 11a is formed. The first conductor layer 1 is formed so as to have a smaller residual copper ratio at least in a region overlapping the through hole 60 in a plan view than the second conductor layer 2 formed in the subsequent step.

A conductor layer 31 and a via conductor 71 are formed on the second surface 6b side of the core substrate 6 in the same manner as the via conductor 71 on the first conductor layer 1 and the first surface 6a side, preferably at the same time. ..

As shown in FIG. 5H, the second insulating layer 42 and the second conductor layer 2 are formed, and further, the insulating layer 43 and the conductor layer 3 are formed. An insulating layer 44 covering the conductor layer 31 and a conductor layer 32 are formed on the second surface 6b side of the core substrate 6, and further, an insulating layer 44 covering the conductor layer 32 and a conductor layer 33 are formed. Further, along with the formation of each conductor layer, a via conductor 71 penetrating the insulating layer on the lower layer side of each conductor layer is formed. The second insulating layer 42 and the insulating layers 43 and 44 are formed by thermocompression bonding of a resin formed in a film shape, as in the case of forming the first insulating layer 41. The second conductor layer 2, the conductor layer 3, and the conductor layers 31 to 33 are formed by, for example, a semi-additive method, similarly to the first conductor layer 1.

After forming the conductor layer 3 and the conductor layer 33, the solder resist 8 is formed on the exposed surfaces of the conductor layer 3 and the insulating layer 43. Similarly, on the second surface 6b side, the solder resist 8 is formed on the exposed surfaces of the conductor layer 33 and the outermost insulating layer 44. The solder resist 8 is provided with an opening for exposing the conductor pad 3a of the conductor layer 3 or the conductor pad 33a of the conductor layer 33. The solder resist 8 and its openings are formed by forming a resin layer containing a photosensitive epoxy resin, a polyimide resin, or the like, and exposing and developing with a mask having an appropriate opening pattern.

Bumps 3b are formed on the conductor pads 3a and 33a exposed to the openings of the solder resist 8. The bump 3b can be formed, for example, by heating by reflow after arranging the solder balls or by precipitation of an arbitrary metal by electroplating. The conductor pads 3a and 33a may be subjected to Au, Ni / Au, Ni / Pd / Au, solder, or by electroless plating, solder leveler, spray coating, etc. instead of the bumps 3b or before the bumps 3b are formed. A surface protective film (not shown) made of heat-resistant preflux or the like may be formed. By going through the above steps, the component-embedded wiring board 100 of the example of FIG. 1 is completed.

The component-embedded wiring board of the embodiment is not limited to the structure exemplified in each drawing and the structure, shape, and material exemplified in this specification. For example, the first conductor layer 1 and the second conductor layer 2 having the above-mentioned magnitude relationship with respect to the residual copper ratio in the region A may be provided on the second surface 6b side of the core substrate 6. That is, in the example of FIG. 1, the residual copper ratio in the region A of the conductor layer 31 may be smaller than the residual copper ratio in the region A of the conductor layer 32. Further, the conductor layer 31 may be a signal layer, and the conductor layer 32 may be a power supply layer or a ground layer. Further, the thickness of the electronic component 5 may be different from the thickness of the insulating layer 61 of the core substrate 6. In that case, the recess that may be formed by the step between the surface of the electronic component 5 and the first surface 6a and / or the second surface 6b of the core substrate 6 is the insulating layer 44 on the first insulating layer 41 or the second surface 6b. Filled with. Further, the resin body 40 may be formed separately from the first insulating layer 41. Further, the component-embedded wiring board of the embodiment may include at least two or more arbitrary number of conductor layers including the first and second conductor layers. Further, the component-embedded wiring board of the embodiment may have an asymmetric structure on both sides of the core board.

100 Wiring board 1 First conductor layer 12, 22 Air gap 2 Second conductor layer 21b Solid pattern 21c Penetration part 3, 31-3 Conductor layer 40 Resin body 41 First insulation layer 42 Second insulation layer 43, 44 Insulation layer 5 Electronic component 6 Core substrate 60 Through hole 64 Space 7, 71 Via conductor A Area that overlaps with the through hole in plan view

Claims (12)

A core substrate with through holes and
Electronic components arranged in the through hole and
A resin body that fills the space between the inner wall of the through hole and the electronic component,
A first insulating layer laminated on the surface of the core substrate and the surface of the electronic component,
A first conductor layer formed on the surface of the first insulating layer opposite to the core substrate, and
A component-embedded wiring board including the first insulating layer and the second conductor layer formed on the first conductor layer via an insulating layer different from the first insulating layer.
The residual copper ratio of the first conductor layer in the region overlapping the through hole in a plan view is smaller than the residual copper ratio of the second conductor layer in the region overlapping the through hole in a plan view. The component-embedded wiring board according to claim 1.
The area of the largest conductor pattern among the conductor patterns that at least partially overlap the through hole in the first conductor layer in a plan view is the conductor that at least partially overlaps the through hole in the second conductor layer in a plan view. It is smaller than the area of the largest conductor pattern of the patterns. The component-embedded wiring board according to claim 1.
The first conductor layer includes a conductor portion formed of a conductor pattern and a void portion other than the conductor portion.
The gap portion at least partially includes the space between the inner wall of the through hole and the electronic component in a plan view. The component-embedded wiring board according to claim 3, wherein the gap portion of the first conductor layer includes the entire space in a plan view. The component-embedded wiring board according to claim 3 or 4, wherein the second conductor layer includes a conductor pattern that overlaps with the space in a plan view. The component-embedded wiring board according to claim 3 or 4, wherein the second conductor layer includes a region of the space that is included in the gap in a plan view and a conductor pattern that overlaps in a plan view. There is. The component-embedded wiring board according to claim 3 or 4.
The second conductor layer includes a solid pattern which is a conductor pattern which is provided so as to occupy a predetermined region and spreads in a plane shape, and the solid pattern overlaps the entire space in a plan view. The component-embedded wiring board according to claim 1.
The first conductor layer does not include a conductor pattern that is provided so as to occupy a predetermined region in a region that overlaps the through hole in a plan view and spreads in a plane shape.
The second conductor layer includes a solid pattern which is a conductor pattern which is provided so as to occupy a predetermined region and spreads in a plane shape. The component-embedded wiring board according to claim 8.
The first conductor layer is provided so as to occupy a predetermined region and does not include a conductor pattern that spreads in a plane shape.
The solid pattern of the second conductor layer overlaps the through hole in a plan view. The component-embedded wiring board according to claim 8, wherein the solid pattern is provided with a penetrating portion that penetrates the solid pattern without including the conductor pattern of the second conductor layer. In the component-embedded wiring board according to claim 8, the area of the solid pattern is larger than the area of the conductor patterns other than the solid pattern included in the second conductor layer. The component-embedded wiring board according to claim 1, wherein the resin body is integrally formed with the first insulating layer.

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