JP2022179156A

JP2022179156A - Wiring board and manufacturing method for wiring board

Info

Publication number: JP2022179156A
Application number: JP2021086439A
Authority: JP
Inventors: 朋博二木; Tomohiro Niki; 直樹高崎; Naoki Takasaki
Original assignee: Ibiden Co Ltd
Current assignee: Ibiden Co Ltd
Priority date: 2021-05-21
Filing date: 2021-05-21
Publication date: 2022-12-02

Abstract

To improve the quality of a wiring board.SOLUTION: A wiring board 100 includes an insulating layer 21 having a first surface 210, a conductive layer 11 formed on the first surface 210 and including a component mount region A, and an insulating layer 22 covering the first surface 210 and the conductive layer 11 and including a penetration hole 221 exposing the component mount region A. The conductive layer 11 includes a conductive pad 1 including the component mount region A and partially covered with the insulating layer 22. The first surface 210 includes a first region 211 overlapping with the penetration hole 221 in a plan view in a region 213 in contact with the conductive pad 1, and a second region 212 other than the first region 211. An interface between the first surface 210 and the conductive pad 1 includes a separation part 5 corresponding to a part where the insulating layer 21 and the conductive pad 1 are separated.SELECTED DRAWING: Figure 2

Description

本発明は、配線基板及び配線基板の製造方法に関する。 The present invention relates to a wiring board and a method for manufacturing the wiring board.

特許文献１には、電子部品が収容されるキャビティを有する電子部品内蔵用キャビティ付き配線板（以下、単に「配線板」と称される）が開示されている。配線板は、プレーン層を含むビルドアップ導体層を含んでいる。キャビティは、プレーン層上のビルドアップ絶縁層を貫通してプレーン層を露出させている。プレーン層はキャビティの底面全体を構成している。 Patent Literature 1 discloses a wiring board with a cavity for housing an electronic component (hereinafter simply referred to as a "wiring board") having a cavity in which the electronic component is housed. The wiring board includes build-up conductor layers including plane layers. The cavity penetrates the build-up insulating layer on the plane layer to expose the plane layer. A plane layer forms the entire bottom surface of the cavity.

特開２０１６－３９２１４号公報JP 2016-39214 A

特許文献１に開示の配線板では、電子部品やプレーン層自身の収縮などによる応力がプレーン層と下地のビルドアップ絶縁層との界面に発生し、プレーン層が下地のビルドアップ絶縁層から剥離することがある。 In the wiring board disclosed in Patent Document 1, stress due to shrinkage of the electronic component and the plane layer itself occurs at the interface between the plane layer and the underlying buildup insulating layer, and the plane layer separates from the underlying buildup insulating layer. Sometimes.

本発明の配線基板は、第１面を有する第１絶縁層と、前記第１面上に形成されていて部品搭載領域を含む導体層と、前記第１面及び前記導体層を覆っていて前記部品搭載領域を露出させる貫通孔を有する第２絶縁層と、を備えている。そして、前記導体層は、前記部品搭載領域を含んでいて前記第２絶縁層に部分的に覆われている導体パッドを含み、前記第１面は、前記導体パッドと接している領域において、前記貫通孔と平面視で重なる第１領域と前記第１領域以外の第２領域とを含み、前記第１面と前記導体パッドとの界面は、前記第１絶縁層と前記導体パッドとが離れている部分である離間部を含んでいる。 A wiring board of the present invention comprises a first insulating layer having a first surface, a conductor layer formed on the first surface and including a component mounting region, and covering the first surface and the conductor layer and covering the and a second insulating layer having a through hole exposing the component mounting area. The conductor layer includes a conductor pad that includes the component mounting region and is partially covered with the second insulating layer, and the first surface has a region in contact with the conductor pad, the The interface between the first surface and the conductor pad includes a first area that overlaps the through hole in a plan view and a second area other than the first area, and the interface between the first surface and the conductor pad is separated from the first insulating layer and the conductor pad. It includes a spaced portion, which is the portion where the

本発明の配線基板の製造方法は、第１面を有する第１絶縁層を用意することと、前記第１面上に、導体パッドを含む導体層を形成することと、前記導体層及び前記第１面を覆う第２絶縁層を形成することと、前記導体パッド上の前記第２絶縁層に貫通孔を形成することによって、底面に前記導体パッドを備える部品収容部を形成することと、を含んでいる。そして、前記貫通孔を形成することは、前記第１面と前記導体パッドとの界面に、前記第１絶縁層と前記導体パッドとの離間部を形成することを含んでいる。 A method of manufacturing a wiring board according to the present invention includes preparing a first insulating layer having a first surface, forming a conductor layer including a conductor pad on the first surface, forming a second insulating layer covering one surface; and forming a through hole in the second insulating layer on the conductive pad to form a component housing portion having the conductive pad on the bottom surface. contains. Forming the through hole includes forming a separation portion between the first insulating layer and the conductor pad at the interface between the first surface and the conductor pad.

本発明の実施形態によれば、絶縁層の貫通孔内に露出する部品搭載領域を含む導体パッドとその下層の絶縁層との剥離が抑制されると考えられる。 According to the embodiment of the present invention, it is considered that the separation between the conductor pad including the component mounting region exposed in the through-hole of the insulating layer and the underlying insulating layer is suppressed.

本発明の一実施形態の配線基板の一例を示す断面図。1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention; FIG. 図１のII部の拡大図。The enlarged view of the II section of FIG. 図２に示される貫通孔及びその周辺部分の平面図。FIG. 3 is a plan view of the through hole shown in FIG. 2 and its peripheral portion; 図２の導体パッドとその下層の絶縁層との界面部分の拡大図。FIG. 3 is an enlarged view of an interface portion between the conductor pad of FIG. 2 and an insulating layer therebelow; 本発明の一実施形態の配線基板における導体パッド及びその周辺部の他の例を示す断面図。FIG. 4 is a cross-sectional view showing another example of a conductor pad and its peripheral portion in a wiring board according to one embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す平面図。FIG. 4 is a plan view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す斜視図。FIG. 2 is a perspective view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 本発明の実施形態の配線基板の製造方法の一例を示す断面図。FIG. 4 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention;

本発明の一実施形態の配線基板が図面を参照しながら説明される。図１には、本実施形態の配線基板の一例である配線基板１００の断面図が示されており、図２は、図１のII部の拡大図を示している。図２では、図１に示される貫通孔２２１の明確化のために絶縁層２４及びビア導体４３が省略されると共に、部品Ｅ及び接着剤６についてそれぞれの輪郭だけが二点鎖線で示されている。図３には、図２に示される貫通孔２２１及びその周辺部の平面図が示されている。なお、図１～図３に例示される配線基板１００は本実施形態の配線基板の一例に過ぎない。実施形態の配線基板の積層構造、並びに、導体層及び絶縁層それぞれの数は、配線基板１００の積層構造、並びに、配線基板１００に含まれる導体層及び絶縁層それぞれの数に限定されない。 A wiring board according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 100, which is an example of the wiring board of the present embodiment, and FIG. 2 shows an enlarged view of part II of FIG. In FIG. 2, the insulating layer 24 and via conductors 43 are omitted for clarity of the through holes 221 shown in FIG. there is FIG. 3 shows a plan view of the through hole 221 shown in FIG. 2 and its surroundings. Note that the wiring board 100 illustrated in FIGS. 1 to 3 is merely an example of the wiring board of the present embodiment. The laminated structure of the wiring board of the embodiment and the number of conductor layers and insulating layers are not limited to the laminated structure of the wiring board 100 and the number of conductor layers and insulating layers included in the wiring board 100 .

図１に示されるように、配線基板１００は、コア基板３と、コア基板３におけるその厚さ方向において対向する２つの主面（表面３ａ及び表面３ｂ）それぞれの上に交互に積層されている絶縁層及び導体層とを含んでいる。コア基板３は、絶縁層３２と、絶縁層３２の両面それぞれの上に形成されている導体層３１とを含んでいる。コア基板３は、さらに、絶縁層３２を貫通して絶縁層３２の両面の導体層３１同士を接続するスルーホール導体３３を含んでいる。 As shown in FIG. 1, the wiring substrate 100 is alternately laminated on the core substrate 3 and two main surfaces (surfaces 3a and 3b) of the core substrate 3 that face each other in the thickness direction. It includes an insulating layer and a conductor layer. The core substrate 3 includes an insulating layer 32 and conductor layers 31 formed on both surfaces of the insulating layer 32 . The core substrate 3 further includes through-hole conductors 33 that penetrate the insulating layer 32 and connect the conductor layers 31 on both sides of the insulating layer 32 .

コア基板３の表面３ａの上には、表面３ａ側から順に、２つの絶縁層２０それぞれと２つの導体層１０それぞれとが交互に積層されている。そして、それら絶縁層２０及び導体層１０の上に、絶縁層２１、導体層１１、絶縁層２２が順に積層されている。すなわち配線基板１００は、絶縁層２１（第１絶縁層）と、導体層１１（第１導体層）と、絶縁層２２（第２絶縁層）と、を含んでいる。絶縁層２１は、コア基板３側と反対側の表面として第１面２１０を有している。導体層１１は、絶縁層２１の第１面２１０の上に形成されている。絶縁層２２は、絶縁層２１の第１面２１０及び導体層１１を覆っている。絶縁層２２の上には、さらに、導体層１２、導体層１２を保護する絶縁層２３、絶縁層２４（封止層）、及び導体層１３が順に積層されている。 On the surface 3a of the core substrate 3, two insulating layers 20 and two conductor layers 10 are alternately laminated from the surface 3a side. An insulating layer 21 , a conductive layer 11 and an insulating layer 22 are laminated in this order on the insulating layer 20 and the conductive layer 10 . That is, the wiring board 100 includes an insulating layer 21 (first insulating layer), a conductor layer 11 (first conductor layer), and an insulating layer 22 (second insulating layer). The insulating layer 21 has a first surface 210 as a surface opposite to the core substrate 3 side. Conductive layer 11 is formed on first surface 210 of insulating layer 21 . The insulating layer 22 covers the first surface 210 of the insulating layer 21 and the conductor layer 11 . Further, on the insulating layer 22, the conductor layer 12, the insulating layer 23 for protecting the conductor layer 12, the insulating layer 24 (sealing layer), and the conductor layer 13 are laminated in this order.

一方、コア基板３の表面３ｂ上には、４つの絶縁層２０のそれぞれと４つの導体層１０のそれぞれとが交互に積層され、さらに絶縁層２５及び絶縁層２６が積層された上に導体層１４が形成されている。 On the other hand, on the surface 3b of the core substrate 3, four insulating layers 20 and four conductor layers 10 are alternately laminated, and an insulating layer 25 and an insulating layer 26 are laminated on top of the conductor layer. 14 are formed.

なお、実施形態の説明では、配線基板１００の厚さ方向において絶縁層３２から遠い側は「上側」若しくは「外側」、「上方」、又は単に「上」とも称され、絶縁層３２に近い側は「下側」若しくは「内側」、「下方」、又は単に「下」とも称される。さらに、各導体層及び各絶縁層において、絶縁層３２と反対側を向く表面は「上面」とも称され、絶縁層３２側を向く表面は「下面」とも称される。 In the description of the embodiments, the side farther from the insulating layer 32 in the thickness direction of the wiring board 100 is also referred to as "upper", "outer", "upper", or simply "upper", and the side closer to the insulating layer 32 is also referred to as "lower side" or "inner side", "lower side" or simply "lower side". Furthermore, in each conductor layer and each insulating layer, the surface facing away from the insulating layer 32 is also referred to as the "upper surface", and the surface facing the insulating layer 32 is also referred to as the "lower surface".

絶縁層２０～２２それぞれには、各絶縁層を貫通し、各絶縁層を介して隣接する導体層同士を接続するビア導体４０が形成されている。絶縁層２３及び絶縁層２４には、導体層１２と導体層１３とを接続するビア導体４１が形成され、絶縁層２５及び絶縁層２６には、導体層１０と導体層１４とを接続するビア導体４２が形成されている。 Via conductors 40 are formed in each of the insulating layers 20 to 22 so as to pass through each insulating layer and connect adjacent conductor layers via each insulating layer. Via conductors 41 connecting the conductor layers 12 and 13 are formed in the insulating layers 23 and 24, and vias connecting the conductor layers 10 and 14 are formed in the insulating layers 25 and 26. A conductor 42 is formed.

図１の配線基板１００は、さらに、ソルダーレジスト７を備えている。ソルダーレジスト７は、コア基板３の表面３ａ側及び表面３ｂ側それぞれにおいて配線基板１００の表面に形成されている。ソルダーレジスト７は、導体層１３又は導体層１４の一部を露出させる開口を備えている。ソルダーレジスト７は、例えばエポキシ樹脂やポリイミド樹脂などの任意の絶縁性材料を用いて形成される。 The wiring board 100 of FIG. 1 further includes a solder resist 7. As shown in FIG. The solder resist 7 is formed on the surface of the wiring substrate 100 on the surface 3a side and the surface 3b side of the core substrate 3 respectively. The solder resist 7 has an opening that exposes part of the conductor layer 13 or the conductor layer 14 . The solder resist 7 is formed using any insulating material such as epoxy resin or polyimide resin.

各絶縁層２０、絶縁層２１～２６、及び絶縁層３２は、それぞれ、主に任意の絶縁性樹脂によって形成される。絶縁性樹脂としては、エポキシ樹脂、ビスマレイミドトリアジン樹脂（ＢＴ樹脂）又はフェノール樹脂などが例示される。図１の例では、絶縁層３２は、ガラス繊維やアラミド繊維などで形成される芯材（補強材）３２ａを含んでいる。図１には示されていないが、絶縁層３２以外の各絶縁層も、ガラス繊維などからなる芯材を含み得る。絶縁層２０～２６及び絶縁層３２は、さらに、後述されるように、エポキシ樹脂などの絶縁性樹脂に添加されているフィラー２１ａ（図４参照）を含み得る。 Each insulating layer 20, insulating layers 21 to 26, and insulating layer 32 are mainly formed of any insulating resin. Examples of the insulating resin include epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. In the example of FIG. 1, the insulating layer 32 includes a core material (reinforcing material) 32a made of glass fiber, aramid fiber, or the like. Although not shown in FIG. 1, each insulating layer other than insulating layer 32 may also include a core material made of glass fiber or the like. Insulating layers 20-26 and insulating layer 32 may further include fillers 21a (see FIG. 4) added to an insulating resin such as epoxy resin, as will be described later.

各導体層１０、導体層１１～１４、及び導体層３１、並びに、スルーホール導体３３及びビア導体４０～４２は、それぞれ、銅又はニッケルなどの任意の金属を用いて形成される。図１では、各導体層が１つの層で構成されるように描かれているが、各導体層は多層構造を有し得る。導体層３１は、例えば、金属箔、無電解めっき膜、及び電解めっき膜を含む３層構造を有し得る。その場合、スルーホール導体３３は、導体層３１を構成する各めっき膜と一体的に形成され得る。 Each conductor layer 10, conductor layers 11-14, conductor layer 31, through-hole conductor 33 and via conductors 40-42 are each formed using any metal such as copper or nickel. Although FIG. 1 depicts each conductor layer as consisting of one layer, each conductor layer may have a multi-layer structure. The conductor layer 31 can have, for example, a three-layer structure including a metal foil, an electroless plated film, and an electrolytic plated film. In that case, the through-hole conductor 33 can be formed integrally with each plated film forming the conductor layer 31 .

一方、導体層１０～１４、及びビア導体４０～４２は、それぞれ、図２に示される導体層１１のように、電解めっき膜層１０ｂ、及び電解めっき膜層１０ｂの形成時に給電層として機能する金属被膜層１０ａによって構成され得る。金属被膜層１０ａは、例えば無電解めっき膜又はスパッタリング膜である。ビア導体４０～４２は、ビア導体４０～４２それぞれの上に形成されている導体層（導体層１０～１４のいずれか）と一体的に形成されている。 On the other hand, the conductor layers 10 to 14 and the via conductors 40 to 42, like the conductor layer 11 shown in FIG. It may be constituted by a metallization layer 10a. The metal coating layer 10a is, for example, an electroless plating film or a sputtering film. Via conductors 40-42 are formed integrally with conductor layers (any of conductor layers 10-14) formed on via conductors 40-42, respectively.

導体層１０～１４及び導体層３１は、それぞれ、所定の導体パターンを含んでいる。例えば導体層１３は、外部回路との接続に用いられる接続パッド１３１、１３２を含んでいる。そして導体層１１は、導体パッド１（第１導体パッド）を含んでいる。図１の例では、導体層１１は、導体パッド１の他に、配線パターン１１１及び導体パッド１１２（第２導体パッド）を含んでいる。配線パターン１１１は、任意の電気信号の伝送や電力の供給に用いられる導電路として機能する導体パターンである。導体パッド１１２は、絶縁層２１を貫通するビア導体４０の所謂ビアパッドであって絶縁層２２を貫通するビア導体４０のための所謂受けパッドである。 Each of the conductor layers 10-14 and the conductor layer 31 includes a predetermined conductor pattern. For example, the conductor layer 13 includes connection pads 131, 132 used for connection with an external circuit. The conductor layer 11 includes a conductor pad 1 (first conductor pad). In the example of FIG. 1, the conductor layer 11 includes, in addition to the conductor pad 1, a wiring pattern 111 and a conductor pad 112 (second conductor pad). The wiring pattern 111 is a conductor pattern that functions as a conductive path used for transmitting arbitrary electrical signals and supplying power. The conductor pads 112 are so-called via pads for the via conductors 40 penetrating the insulating layer 21 and are so-called receiving pads for the via conductors 40 penetrating the insulating layer 22 .

導体パッド１は、配線基板１００に内蔵又は搭載される部品の載置に用いられる部品搭載パッドである。すなわち導体層１１は、配線基板１００に内蔵又は搭載される部品が載置されるべき領域である部品搭載領域Ａを含んでいる。具体的には導体パッド１が、導体パッド１における絶縁層２１と反対側の表面（導体パッド１の搭載面）１ａ上に部品搭載領域Ａを含んでいる。 The conductor pads 1 are component mounting pads used for mounting components to be built in or mounted on the wiring board 100 . That is, the conductor layer 11 includes a component mounting area A, which is an area on which components to be built in or mounted on the wiring board 100 are to be mounted. Specifically, the conductive pad 1 includes a component mounting area A on the surface (mounting surface of the conductive pad 1) 1a opposite to the insulating layer 21 of the conductive pad 1. As shown in FIG.

図１～図３に示されるように、絶縁層２２は、絶縁層２２を貫通する貫通孔２２１を有している。図１～図３の貫通孔２２１は絶縁層２３も貫通している。貫通孔２２１は部品搭載領域Ａを絶縁層２２から露出させている。しかし貫通孔２２１の周囲では、導体パッド１における部品搭載領域Ａ以外の部分を絶縁層２２が覆っていて導体パッド１は絶縁層２２に部分的に覆われている。具体的には、絶縁層２２は、導体パッド１の周縁部を覆っている。 As shown in FIGS. 1 to 3, the insulating layer 22 has through holes 221 penetrating through the insulating layer 22 . The through holes 221 in FIGS. 1 to 3 also penetrate the insulating layer 23 . The through hole 221 exposes the component mounting area A from the insulating layer 22 . However, around the through hole 221 , the insulating layer 22 covers the portion of the conductor pad 1 other than the component mounting area A, and the conductor pad 1 is partially covered with the insulating layer 22 . Specifically, the insulating layer 22 covers the periphery of the conductor pad 1 .

導体パッド１は、絶縁層２１の第１面２１０における平面視で貫通孔２２１と重なる領域を全体的に覆うと共に、部品搭載領域Ａを貫通孔２２１内に露出させている。なお「平面視」は、実施形態の配線基板をその厚さ方向に沿った視線で見ることを意味する。また貫通孔２２１が図１～図３の例のようにテーパー形状を有している場合、「貫通孔２２１と重なる領域」は、貫通孔２２１における導体層１１側の開口と重なる領域を意味している。貫通孔２２１と導体パッド１とによって、配線基板１００に内蔵される部品が内部に収容される部品収容部（凹部又はキャビティ）Ｈが形成されている。導体パッド１の表面１ａによって部品収容部Ｈの底面全体が構成されている。 The conductor pad 1 entirely covers the region of the first surface 210 of the insulating layer 21 that overlaps the through hole 221 in plan view, and exposes the component mounting region A inside the through hole 221 . Note that "planar view" means viewing the wiring board of the embodiment with a line of sight along its thickness direction. Further, when the through hole 221 has a tapered shape as in the examples of FIGS. 1 to 3, the “region overlapping the through hole 221” means the region overlapping the opening of the through hole 221 on the conductor layer 11 side. ing. The through hole 221 and the conductor pad 1 form a component housing portion (recess or cavity) H in which a component built into the wiring board 100 is housed. The entire bottom surface of the component housing portion H is formed by the surface 1a of the conductive pad 1. As shown in FIG.

図１の例では、部品Ｅが部品収容部Ｈに収容されている。部品Ｅは、導体パッド１の部品搭載領域Ａに載置されている。部品Ｅは、部品Ｅと外部回路との接続に用いられる電極Ｅ１を含んでいる。部品Ｅとしては、例えば、半導体集積回路装置やトランジスタなどの能動部品、又は電気抵抗などの受動部品などの電子部品が例示される。部品Ｅは、半導体基板上に形成された微細配線を含む配線材（例えばインターポーザ）であってもよい。部品Ｅは、はんだ若しくは金などの金属、導電性接着剤、又は、エポキシ樹脂などで構成される絶縁性接着剤などの任意の材料からなる接着剤６を用いて導体パッド１に接合されている。 In the example of FIG. 1, the component E is accommodated in the component accommodation part H. As shown in FIG. A component E is mounted on a component mounting area A of the conductor pad 1 . The component E includes an electrode E1 used for connection between the component E and an external circuit. Examples of the component E include active components such as semiconductor integrated circuit devices and transistors, and electronic components such as passive components such as electrical resistors. The component E may be a wiring material (for example, an interposer) including fine wiring formed on a semiconductor substrate. The component E is bonded to the conductor pad 1 using an adhesive 6 made of any material such as a metal such as solder or gold, a conductive adhesive, or an insulating adhesive made of epoxy resin or the like. .

貫通孔２２１の内部は絶縁層２４の構成材料で充填されている。絶縁層２４は部品Ｅを覆っている。絶縁層２４によって、貫通孔２２１内に部品Ｅが封止されている。従って図１の配線基板１００は部品内蔵配線基板である。部品Ｅ上にはビア導体４３が設けられている。ビア導体４３は部品Ｅ上の絶縁層２４を貫通して部品Ｅの電極Ｅ１と接続パッド１３２とを接続している。ビア導体４３は、導体層１３と一体的に形成されており、ビア導体４０～４２と同様の構造を有し得る。 The inside of the through-hole 221 is filled with the constituent material of the insulating layer 24 . An insulating layer 24 covers the part E. The part E is sealed in the through hole 221 by the insulating layer 24 . Therefore, the wiring board 100 in FIG. 1 is a component built-in wiring board. A via conductor 43 is provided on the component E. FIG. The via conductor 43 penetrates the insulating layer 24 on the component E and connects the electrode E1 of the component E and the connection pad 132 . Via conductor 43 is integrally formed with conductor layer 13 and may have the same structure as via conductors 40-42.

図２及び図３に示されるように、絶縁層２１の第１面２１０は、導体パッド１と接している領域２１３を含んでいる。第１面２１０は、領域２１３において、貫通孔２２１と平面視で重なる第１領域２１１と、第１領域２１１以外の領域である第２領域２１２とを含んでいる。図２及び図３の例では、領域２１３は第１領域２１１及び第２領域２１２からなる。図３に示されるように、第２領域２１２は第１領域２１１を囲んでおり、平面視で絶縁層２２と重なっている。 As shown in FIGS. 2 and 3 , the first surface 210 of the insulating layer 21 includes regions 213 in contact with the contact pads 1 . The first surface 210 includes a first region 211 that overlaps the through hole 221 in plan view, and a second region 212 that is a region other than the first region 211 in the region 213 . In the example of FIGS. 2 and 3, region 213 consists of first region 211 and second region 212 . As shown in FIG. 3, the second region 212 surrounds the first region 211 and overlaps the insulating layer 22 in plan view.

そして、絶縁層２１の第１面２１０と導体パッド１との界面は、図１では視認され得ない大きさのため省略されているが、図２に示されるように１以上の離間部５を含んでいる。離間部５は、絶縁層２１と導体パッド１との界面において絶縁層２１と導体パッド１とが離れている部分である。 The interface between the first surface 210 of the insulating layer 21 and the conductor pad 1 is omitted in FIG. 1 because it is too large to be visually recognized. contains. The spaced portion 5 is a portion where the insulating layer 21 and the conductive pad 1 are separated from each other at the interface between the insulating layer 21 and the conductive pad 1 .

導体パッド１のように配線基板に含まれる所謂部品搭載パッドでは、部品Ｅのような搭載部品の搭載時から配線基板の使用時まで、搭載部品に由来する歪みが、部品搭載パッドと部品搭載パッドの下層の絶縁層との界面に生じ得る。例えば、多くの場合、搭載部品及び部品搭載パッドと、部品搭載パッドの下層の絶縁層２１のような絶縁層とは、互いに異なる熱膨張率を有し得る。そのため、部品搭載時における接着剤６のような接着剤に対する加熱時やその後の除熱時、及び、配線基板の使用中の周囲温度の変化時には、搭載部品及び部品搭載パッドと絶縁層との間の伸縮量の違いによって、部品搭載パッドと絶縁層との界面付近に歪みが生じ得る。そして、部品搭載パッドと絶縁層とが界面の全面で接合していると、界面の各部に生じる歪みが界面に沿って蓄積し、結果として部品搭載パッド及び絶縁層の一方が他方よりも撓むことによって広範な界面剥離が生じることがある。 In a so-called component mounting pad included in the wiring board, such as the conductor pad 1, distortion derived from the mounted component occurs between the component mounting pad and the component mounting pad from the time of mounting the mounted component such as the component E to the time of use of the wiring board. can occur at the interface with the underlying insulating layer. For example, in many cases, the mounting component and component mounting pad and the insulating layer, such as insulating layer 21, underlying the component mounting pad may have different coefficients of thermal expansion. Therefore, when the adhesive such as the adhesive 6 is heated during component mounting, when the heat is removed after that, and when the ambient temperature changes during use of the wiring board, there is no heat between the mounted components and the component mounting pads and the insulating layer. Due to the difference in the amount of expansion and contraction, strain may occur in the vicinity of the interface between the component mounting pad and the insulating layer. When the component mounting pad and the insulating layer are bonded over the entire interface, the strain generated at each part of the interface accumulates along the interface, and as a result, one of the component mounting pad and the insulating layer bends more than the other. This can result in extensive interfacial delamination.

このような界面剥離の懸念に対して本実施形態では、前述したように絶縁層２１の第１面２１０と導体パッド１との界面は離間部５を含んでいる。そのため、部品Ｅの搭載時や配線基板１００の使用中の温度変化などによって部品Ｅに由来して導体パッド１と絶縁層２１との界面に生じる歪みが、離間部５によって吸収若しくは緩和されると推察される。換言すると、歪みの逃げ場が離間部５によって提供される。従って、部品Ｅ由来の歪みの蓄積などによる導体パッド１と絶縁層２１との界面剥離が抑制される。 In this embodiment, as described above, the interface between the first surface 210 of the insulating layer 21 and the conductor pad 1 includes the separation portion 5 in order to deal with the concern of such interfacial peeling. Therefore, when the component E is mounted or when the wiring board 100 is in use, the strain generated at the interface between the conductive pad 1 and the insulating layer 21 due to temperature changes or the like originating from the component E can be absorbed or alleviated by the separating portion 5 . guessed. In other words, the strain relief is provided by the spacing portion 5 . Therefore, interfacial peeling between the conductor pad 1 and the insulating layer 21 due to accumulation of strain derived from the component E is suppressed.

加えて本実施形態では、図２の例のように、貫通孔２２１と平面視で重なる領域であって、部品搭載領域Ａと重なる領域を含む第１面２１０の第１領域２１１における離間部５の占有率は、第２領域２１２における離間部５の占有率よりも高くてもよい。図２の例の第２領域２１２は、絶縁層２１と導体パッド１とが離れている離間部５を含んでいない。すなわち、離間部５の占有率に関して一方の領域が他方の領域よりも「高い」には、一方の領域（例えば第１領域２１１）に少なくとも１つの離間部５が存在していて他方の領域（例えば第２領域２１２）に離間部５が存在しない状態も含まれる。なお、実施形態において第２領域２１２は、離間部５を含んでいてもよい。ここで離間部５の「占有率」は、第１領域２１１及び第２領域２１２それぞれの面積に対する、各領域に含まれる１又は複数の離間部５の平面視での面積の総和の比率である。 In addition, in the present embodiment, as in the example of FIG. 2, the spaced portion 5 in the first area 211 of the first surface 210 including the area overlapping the through hole 221 in plan view and overlapping the component mounting area A may be higher than that of the spacing portion 5 in the second region 212 . The second region 212 in the example of FIG. 2 does not include the separation portion 5 where the insulating layer 21 and the conductor pad 1 are separated. That is, if one area is "higher" than the other with respect to the occupancy rate of the spaced portions 5, at least one spaced portion 5 exists in one region (for example, the first region 211) and the other region ( For example, a state in which the separation portion 5 does not exist in the second region 212) is also included. In addition, in the embodiment, the second region 212 may include the spacing portion 5 . Here, the “occupancy ratio” of the spacing portions 5 is the ratio of the total area of one or more spacing portions 5 included in each region in plan view to the area of each of the first region 211 and the second region 212. .

このように、第２領域２１２は、図１～図３の例では離間部５を含んでいない。離間部５が含まれる場合でも、第２領域２１２は、好ましくは、第１領域２１１よりも低い占有率で離間部５を含み得る。平面視で貫通孔２２１と重ならずに絶縁層２２に覆われている第２領域２１２には、部品Ｅ由来の歪みが比較的生じ難い。そのため第２領域２１２では、導体パッド１と絶縁層２１との界面に離間部５が存在するよりも、導体パッド１と絶縁層２１とがより大きな面積で接合している方が、界面剥離の防止の面で有利なことがある。 Thus, the second region 212 does not include the spacing portion 5 in the examples of FIGS. 1-3. Even when the spacing portion 5 is included, the second region 212 preferably includes the spacing portion 5 at a lower occupation rate than the first region 211 . In the second region 212 that is covered with the insulating layer 22 without overlapping with the through hole 221 in a plan view, distortion due to the component E is relatively unlikely to occur. Therefore, in the second region 212, the bonding area between the conductor pad 1 and the insulating layer 21 is larger than that where the separation portion 5 exists at the interface between the conductor pad 1 and the insulating layer 21, so that the interface delamination is more likely to occur. It can be beneficial in terms of prevention.

第１領域２１１においても、離間部５の占有率が高過ぎると、導体パッド１と絶縁層２１との基本的な密着強度が不足したり、隣接する離間部５同士が比較的弱い機械的ストレスによって連結して密着強度が低下したりすることがある。そのため、第１領域２１１における離間部５の占有率の好ましい値としては、５％以上、２０％以下が例示される。この程度の占有率で離間部５を第１領域２１１に含む導体パッド１では、絶縁層２１との間に適切な密着強度が確保され、しかも、部品Ｅ由来の歪みによる界面剥離も抑制され易いと考えられる。 Also in the first region 211, if the occupation ratio of the spacing portions 5 is too high, the basic adhesion strength between the conductor pad 1 and the insulating layer 21 is insufficient, or the adjacent spacing portions 5 are subjected to relatively weak mechanical stress. may be connected due to the adhesion strength may be lowered. Therefore, a preferable value of the occupying ratio of the spacing portion 5 in the first region 211 is 5% or more and 20% or less. In the conductor pad 1 including the spacing portion 5 in the first region 211 with such an occupation ratio, an appropriate adhesion strength is ensured with the insulating layer 21, and interfacial peeling due to strain derived from the component E is easily suppressed. it is conceivable that.

離間部５は、後述されるように、例えば、貫通孔２２１の形成時のレーザー光の照射条件を調整することによって形成され得る。例えば、レーザー光の照射による局所的且つ瞬間的な発熱に伴って、絶縁層２１と導体パッド１との界面が両者の熱膨張率の違いによって局所的に分離する。その結果離間部５が形成され得る。しかし本実施形態における離間部５の形成方法は、貫通孔２２１の形成時のレーザー光の照射による方法に限定されない。 The spacing portion 5 can be formed, for example, by adjusting the irradiation conditions of the laser light when the through holes 221 are formed, as will be described later. For example, the interface between the insulating layer 21 and the conductor pad 1 is locally separated due to the difference in coefficient of thermal expansion between the insulating layer 21 and the conductor pad 1 due to local and instantaneous heat generation due to laser light irradiation. As a result, the separation portion 5 can be formed. However, the method of forming the separation portion 5 in this embodiment is not limited to the method of irradiating the laser light when forming the through hole 221 .

図２に示される絶縁層２１は第１面２１０に凹凸を有している。第１面２１０は、絶縁層２１の形成工程において凹凸を伴うように形成された粗面であってもよく、絶縁層２１の形成後の粗化工程によって面粗度を高められた被粗化面であってもよい。図２の例では、第１面２１０のうちの第１領域２１１は、第２領域２１２よりも低い面粗度を有している。第１領域２１１の面粗度が比較的低いため、部品Ｅ由来の歪みが生じても凹凸の頂部や最深部を起点とする絶縁層２１のクラックが発生し難いと考えられる。一方、部品Ｅ由来の歪みが比較的生じ難い第２領域２１２では、比較的高い面粗度によって所謂アンカー効果が十分に得られるので、むしろ、導体パッド１と絶縁層２１との剥離がさらに抑制されると推察される。 The insulating layer 21 shown in FIG. 2 has unevenness on the first surface 210 . The first surface 210 may be a rough surface formed with unevenness in the process of forming the insulating layer 21, or may be a roughened surface whose surface roughness is increased by a roughening process after the insulating layer 21 is formed. It can be a face. In the example of FIG. 2, the first area 211 of the first surface 210 has a surface roughness lower than that of the second area 212 . Since the surface roughness of the first region 211 is relatively low, even if distortion originating from the component E occurs, cracks are less likely to occur in the insulating layer 21 starting from the peaks and deepest portions of the unevenness. On the other hand, in the second region 212 where strain originating from the component E is relatively less likely to occur, a so-called anchor effect can be sufficiently obtained due to the relatively high surface roughness. It is assumed that

なお図２の例では導体パッド１も、表面１ａに凹凸を有している。表面１ａ上に供給される接着剤６は、前述したように、はんだや金などの金属であり得るため、接着剤６では絶縁層２１と比べてクラックのような不具合が生じ難い。むしろ、表面１ａが平坦面でなく所定の面粗度を有する粗面（被粗化面）であると、所謂アンカー効果によって、導体パッド１と、接着剤６及び部品Ｅとの強固な接合が得られることがある。また、一定の凹凸を有する表面１ａは、表面１ａが平坦な場合に比べて高い放射率を有し得る。換言すると、一定の凹凸を有する表面１ａを備える導体パッド１は、レーザー光のような電磁波から高度に吸熱する。そのため、絶縁層２１と導体パッド１との界面への離間部５の形成において、より高い離間部５の占有率が望まれる場合に有利なことがある。 In the example of FIG. 2, the conductor pad 1 also has unevenness on the surface 1a. Since the adhesive 6 supplied onto the surface 1 a can be metal such as solder or gold as described above, the adhesive 6 is less prone to problems such as cracks than the insulating layer 21 . Rather, if the surface 1a is not a flat surface but a rough surface (surface to be roughened) having a predetermined surface roughness, a so-called anchor effect will result in strong bonding between the conductor pad 1, the adhesive 6, and the component E. can be obtained. In addition, the surface 1a having constant unevenness can have a higher emissivity than the case where the surface 1a is flat. In other words, the conductor pad 1 having the surface 1a having a certain unevenness absorbs heat to a high degree from electromagnetic waves such as laser light. Therefore, in forming the separation portion 5 at the interface between the insulating layer 21 and the conductor pad 1, it may be advantageous when a higher occupancy rate of the separation portion 5 is desired.

図４には、図２に示される絶縁層２１の第１領域２１１における導体パッド１との界面付近の拡大図が示されている。前述したように、図４に示される絶縁層２１は、フィラー２１ａを含んでいる。従って絶縁層２１は、前述したエポキシなどの絶縁性樹脂２１ｂと絶縁性樹脂２１ｂに添加されているフィラー２１ａとを含んでいる。フィラー２１ａとしては、シリカ（ＳｉＯ₂）、アルミナ、又はムライトなどの無機物の粒体からなる無機フィラーが例示される。またフィラー２１ａは、シリコーン又はポリイミドなどの有機物の粒体からなる有機フィラーであってもよい。 FIG. 4 shows an enlarged view of the vicinity of the interface with the conductor pad 1 in the first region 211 of the insulating layer 21 shown in FIG. As described above, the insulating layer 21 shown in FIG. 4 contains fillers 21a. Therefore, the insulating layer 21 contains the insulating resin 21b such as the aforementioned epoxy and the filler 21a added to the insulating resin 21b. Examples of the filler 21a include inorganic fillers made of inorganic particles such as silica (SiO ₂ ), alumina, or mullite. Further, the filler 21a may be an organic filler composed of particles of an organic substance such as silicone or polyimide.

図４に示されるように、導体パッド１（金属被膜層１０ａ）と絶縁層２１との界面に複数の離間部５（離間部５１～５３）が形成されている。具体的には、離間部５１はフィラー２１ａと導体パッド１との界面に形成され、離間部５２は、フィラー２１ａを覆っている導体パッド１（金属被膜層１０ａ）と絶縁性樹脂２１ｂとの界面に形成されている。離間部５３は、導体パッド１と接合しているフィラー２１ａと絶縁性樹脂２１ｂとの界面に形成されている。このように、複数の離間部５それぞれは、フィラー２１ａと絶縁性樹脂２１ｂとの間に介在していてもよく、フィラー２１ａ又は絶縁性樹脂２１ｂと、導体パッド１との間に介在していてもよい。互いに異なる熱膨張率を有し得るフィラー２１ａ、絶縁性樹脂２１ｂ、及び導体パッド１は、例えば前述したレーザー光の照射によって、互いに異なる量で瞬間的に膨張すると推察される。その結果、微小な離間部５が各界面に形成され得る。 As shown in FIG. 4, a plurality of separation portions 5 (separation portions 51 to 53) are formed at the interface between the conductor pad 1 (metal film layer 10a) and the insulating layer 21. As shown in FIG. Specifically, the separation portion 51 is formed at the interface between the filler 21a and the conductor pad 1, and the separation portion 52 is formed at the interface between the conductor pad 1 (metal film layer 10a) covering the filler 21a and the insulating resin 21b. is formed in The spacing portion 53 is formed at the interface between the filler 21a and the insulating resin 21b, which are joined to the conductor pad 1. As shown in FIG. Thus, each of the plurality of spacing portions 5 may be interposed between the filler 21a and the insulating resin 21b, or may be interposed between the filler 21a or the insulating resin 21b and the conductor pad 1. good too. It is presumed that the filler 21a, the insulating resin 21b, and the conductor pad 1, which can have different coefficients of thermal expansion, instantaneously expand by different amounts due to, for example, the aforementioned laser light irradiation. As a result, minute separation portions 5 can be formed at each interface.

絶縁層２１におけるフィラー２１ａの体積含有率は、例えば、３０％以上、８０％以下である。絶縁層２１に求められる機械的特性、電気的特性、及び熱的特性が満たされると共に、前述した適度な占有率で離間部５が形成され得ることがある。 The volume content of the fillers 21a in the insulating layer 21 is, for example, 30% or more and 80% or less. In some cases, the insulating layer 21 satisfies the mechanical, electrical, and thermal properties required for the insulation layer 21, and the spaced portion 5 can be formed with the above-described moderate occupation ratio.

図５には、図１の配線基板１００の導体パッド１の他の例である導体パッド１α（第１導体パッド）及びその周辺部が、図２に相当する範囲で示されている。図５の例においても、絶縁層２１の第１面２１０と導体パッド１αとの界面は離間部５を含んでいる。また、第１面２１０のうちの貫通孔２２１と平面視で重なる第１領域２１１における離間部５の占有率は、第２領域２１２における離間部５の占有率よりも高い。なお図５の例においても、第２領域２１２は離間部５を含んでいない。 FIG. 5 shows a conductor pad 1α (first conductor pad), which is another example of the conductor pad 1 of the wiring board 100 of FIG. 1, and its peripheral portion in a range corresponding to FIG. In the example of FIG. 5 as well, the interface between the first surface 210 of the insulating layer 21 and the conductor pad 1α includes the spaced portion 5 . Also, the occupancy rate of the spacing portions 5 in the first region 211 overlapping the through holes 221 in plan view in the first surface 210 is higher than the occupancy rate of the spacing portions 5 in the second region 212 . Note that the second region 212 does not include the separation portion 5 in the example of FIG. 5 as well.

図５の例において、導体パッド１αにおける絶縁層２１と反対側の表面１ａは、貫通孔２２１と平面視で重なる領域１ａａ（第３領域）と、貫通孔２２１に露出せずに絶縁層２２に覆われている領域１ａｂ（第４領域）とを有している。領域１ａａは貫通孔２２１に露出している。一方、領域１ａｂは、図２の例の導体パッド１の表面１ａと同様に、凹凸を有している。他方、領域１ａａは、領域１ａｂの面粗度よりも低い面粗度を有する部分である低粗度部１ａｃと、領域１ａｂの面粗度と略同じ面粗度を有していて低粗度部１ａｃを囲む粗面部１ａｄとを含んでいる。低粗度部１ａｃは、図５では領域１ａｂの面粗度との違いが分かりやすいように平坦に描かれているが、領域１ａｂの面粗度よりも低い任意の面粗度で凹凸を有していてもよい。 In the example of FIG. 5, the surface 1a of the conductor pad 1α on the side opposite to the insulating layer 21 includes a region 1aa (third region) overlapping the through hole 221 in a plan view, and the insulating layer 22 without being exposed through the through hole 221. and a covered region 1ab (fourth region). Region 1aa is exposed to through hole 221 . On the other hand, the region 1ab has unevenness like the surface 1a of the conductor pad 1 in the example of FIG. On the other hand, the region 1aa has a low-roughness portion 1ac, which is a portion having a surface roughness lower than that of the region 1ab, and a low-roughness portion 1ac having a surface roughness substantially the same as that of the region 1ab. and a rough surface portion 1ad surrounding the portion 1ac. The low-roughness part 1ac is drawn flat in FIG. You may have

図５の例の低粗度部１ａｃは、粗面部１ａｄ及び領域１ａｂと比べて低い放射率を有し得る。そのため、低粗度部１ａｃを備える導体パッド１αは、レーザー光のような電磁波からの吸熱性が比較的低い。そのため、前述した離間部５の形成においてより低い離間部５の占有率が望まれる場合に有利なことがある。実施形態の配線基板において部品搭載領域を含む導体パッドは、図５の例の低粗度部１ａｃのような、貫通孔に露出しない領域よりも低い面粗度を有する部分を貫通孔への露出面に有していてもよい。 The low-roughness portion 1ac in the example of FIG. 5 may have a lower emissivity than the rough surface portion 1ad and the regions 1ab. Therefore, the conductive pad 1α including the low-roughness portion 1ac has relatively low heat absorption from electromagnetic waves such as laser light. Therefore, it may be advantageous when a lower occupancy rate of the spacing portion 5 is desired in the formation of the spacing portion 5 described above. In the wiring board of the embodiment, the conductor pad including the component mounting area exposes to the through hole a portion having surface roughness lower than the area not exposed to the through hole, such as the low roughness portion 1ac in the example of FIG. You may have it on your face.

なお図５の例では、絶縁層２１の第１面２１０のうちの第１領域２１１と第２領域２１２とは、略同じ面粗度を有している。このように、絶縁層２１は、導体パッド１αとの界面において略一定の面粗度を有していてもよい。 In the example of FIG. 5, the first region 211 and the second region 212 of the first surface 210 of the insulating layer 21 have approximately the same surface roughness. Thus, the insulating layer 21 may have substantially constant surface roughness at the interface with the conductor pad 1α.

つぎに、一実施形態の配線基板の製造方法が、図１の配線基板１００を例に用いて図６Ａ～図６Ｋを参照して説明される。 Next, a method of manufacturing a wiring board according to one embodiment will be described with reference to FIGS. 6A to 6K using the wiring board 100 of FIG. 1 as an example.

図６Ａに示されるように、コア基板３が形成される。例えば、コア基板３の絶縁層３２となる絶縁層と、この絶縁層の両表面にそれぞれ積層された金属箔を含む出発基板（例えば両面銅張積層板）が用意される。そして、貫通孔の形成及びパネルめっきに続くサブトラクティブ法を用いたパターニングによって、所望の導体パターンを有する導体層３１と、スルーホール導体３３が形成される。 As shown in FIG. 6A, core substrate 3 is formed. For example, a starting substrate (for example, a double-sided copper-clad laminate) is prepared which includes an insulating layer to be the insulating layer 32 of the core substrate 3 and metal foil laminated on both surfaces of the insulating layer. A conductor layer 31 having a desired conductor pattern and through-hole conductors 33 are formed by patterning using a subtractive method following the formation of through-holes and panel plating.

図６Ｂに示されるように、コア基板３の表面３ａ上及び表面３ｂ上それぞれに、絶縁層２０及び導体層１０が交互に形成される。表面３ａ及び表面３ｂの上にそれぞれ２組の絶縁層２０及び導体層１０が形成された後、表面３ａ側にさらに絶縁層２１が形成され、表面３ｂ側にもさらに絶縁層２０が形成される。絶縁層２１は、コア基板３と反対側の表面として第１面２１０を有している。このように本実施形態の配線基板の製造方法は、第１面２１０を有する絶縁層２１（第１絶縁層）を用意することを含んでいる。 As shown in FIG. 6B, insulating layers 20 and conductor layers 10 are alternately formed on the surfaces 3a and 3b of the core substrate 3, respectively. After two pairs of insulating layers 20 and conductor layers 10 are formed on the surface 3a and the surface 3b respectively, an insulating layer 21 is further formed on the surface 3a side, and an insulating layer 20 is further formed on the surface 3b side. . The insulating layer 21 has a first surface 210 as the surface opposite to the core substrate 3 . As described above, the wiring board manufacturing method of the present embodiment includes preparing the insulating layer 21 (first insulating layer) having the first surface 210 .

各絶縁層２０及び絶縁層２１の形成では、例えばフィルム状のエポキシ樹脂が、コア基板３の上、又は先に形成された絶縁層２０及び導体層１０の上に積層され、加熱及び加圧される。その結果、絶縁層２１又は各絶縁層２０が形成される。各絶縁層２０には、ビア導体４０を形成するための貫通孔が、例えば炭酸ガスレーザー光の照射などによって形成される。 In the formation of each insulating layer 20 and insulating layer 21, for example, a film-like epoxy resin is laminated on the core substrate 3 or on the previously formed insulating layer 20 and conductor layer 10, and heated and pressurized. be. As a result, the insulating layer 21 or each insulating layer 20 is formed. Through holes for forming via conductors 40 are formed in each insulating layer 20 by, for example, carbon dioxide laser light irradiation.

各導体層１０は、それぞれ、例えばセミアディティブ法によって形成される。すなわち、各導体層１０の下地となる絶縁層２０上の全面、及びその絶縁層２０に形成された貫通孔内に無電解めっきやスパッタリングによって金属膜が形成される。その金属膜を給電層として用いる電解めっきを含むパターンめっきによってめっき膜が形成される。各絶縁層２０に形成された貫通孔内にはビア導体４０が形成される。その後、金属膜の不要部分が例えばエッチングなどで除去される。その結果、所定の導体パターンを含む２層構造の各導体層１０が形成される。各導体層１０は、銅又はニッケルなどの任意の金属を用いて形成される。 Each conductor layer 10 is formed by, for example, a semi-additive method. That is, a metal film is formed by electroless plating or sputtering on the entire surface of the insulating layer 20 serving as the base of each conductor layer 10 and in the through holes formed in the insulating layer 20 . A plated film is formed by pattern plating including electrolytic plating using the metal film as a power supply layer. Via conductors 40 are formed in the through holes formed in each insulating layer 20 . Thereafter, unnecessary portions of the metal film are removed by, for example, etching. As a result, each conductor layer 10 having a two-layer structure including a predetermined conductor pattern is formed. Each conductor layer 10 is formed using any metal such as copper or nickel.

図６Ｂに示されるように、絶縁層２１、及びコア基板３の表面３ｂ側の最も外側の絶縁層２０にも、ビア導体を形成するための貫通孔４０ａが、例えば炭酸ガスレーザー光の照射などによって形成される。貫通孔４０ａの形成後、必要に応じて、貫通孔４０ａの形成によって生じた樹脂残渣（スミア）を除去するデスミア処理が行われる。例えばアルカリ性過マンガン酸溶液などの処理液に貫通孔４０ａの内壁を晒すことによって貫通孔４０ａ内のスミアが除去される。 As shown in FIG. 6B, the insulating layer 21 and the outermost insulating layer 20 on the surface 3b side of the core substrate 3 are also provided with through holes 40a for forming via conductors. formed by After forming the through-holes 40a, desmear treatment is performed as necessary to remove resin residue (smear) generated by the formation of the through-holes 40a. Smear in the through-holes 40a is removed by exposing the inner walls of the through-holes 40a to a treatment liquid such as an alkaline permanganate solution.

図１の配線基板１００が製造される場合は、図６Ｃに示されるように、絶縁層２１の第１面２１０が粗化される。図６Ｃには、図６ＢのVIＣ部の拡大図が示されている。図６Ｃには示されていないが、絶縁層２１の第１面２１０の粗化の際には、コア基板３の表面３ｂ側の最も外側の絶縁層２０（図６Ｂ参照）の表面、及び貫通孔４０ａ（図６Ｂ参照）の内壁の表面も粗化され得る。絶縁層２１の第１面２１０は、好ましくは所定の表面粗さを有するように粗化され得る。第１面２１０の粗化によって、絶縁層２１と、絶縁層２１上に形成される導体層１１（図６Ｄ参照）との密着強度が一定程度向上する。このように本実施形態の配線基板の製造方法は、導体層１１の形成の前に絶縁層２１の第１面２１０を粗化することを含み得る。 When the wiring substrate 100 of FIG. 1 is manufactured, the first surface 210 of the insulating layer 21 is roughened as shown in FIG. 6C. FIG. 6C shows an enlarged view of the VIC portion of FIG. 6B. Although not shown in FIG. 6C, when the first surface 210 of the insulating layer 21 is roughened, the surface of the outermost insulating layer 20 (see FIG. 6B) on the surface 3b side of the core substrate 3 and the through holes The inner wall surfaces of the holes 40a (see FIG. 6B) may also be roughened. A first surface 210 of the insulating layer 21 may preferably be roughened to have a predetermined surface roughness. By roughening the first surface 210, the adhesion strength between the insulating layer 21 and the conductor layer 11 (see FIG. 6D) formed on the insulating layer 21 is improved to some extent. As described above, the wiring board manufacturing method of the present embodiment can include roughening the first surface 210 of the insulating layer 21 before forming the conductor layer 11 .

第１面２１０は、例えば、前述したデスミア処理で用いられる処理液と同様の処理液を用いる過マンガン酸アルカリ溶液処理によって処理される。その結果、第１面２１０が、所望の表面粗さを有するように粗化される。絶縁層２０の第１面２１０は、前述したデスミア処理によって、所定の表面粗さが得られるまで粗化されてもよい。 The first surface 210 is treated, for example, by an alkali permanganate solution treatment using a treatment liquid similar to the treatment liquid used in the desmear treatment described above. As a result, the first surface 210 is roughened to have a desired surface roughness. The first surface 210 of the insulating layer 20 may be roughened by the desmearing process described above until a predetermined surface roughness is obtained.

図６Ｄに示されるように、本実施形態の配線基板の製造方法は、さらに、絶縁層２１の第１面２１０上に、導体パッド１（第１導体パッド）を含む導体層１１（第１導体層）を形成することを含んでいる。導体層１１は、前述した導体層１０の形成方法と同様に、例えばセミアディティブ法を用いて形成される。セミアディティブ法による導体層１０の形成では、少なくとも導体パッド１の形成に適した開口を有するめっきレジストを用いてパターンめっきが行われる。図６Ｄの例では、導体パッド１に加えて、配線パターン１１１及び導体パッド１１２を含む導体層１１が形成されている。絶縁層２１の貫通孔４０ａ内にはビア導体４０が形成される。コア基板３の表面３ｂ側の最も外側の絶縁層２０の上には、導体層１１の形成方法と同様の方法で、さらに導体層１０が形成される。 As shown in FIG. 6D, the wiring board manufacturing method of the present embodiment further includes forming a conductor layer 11 (first conductor) including the conductor pad 1 (first conductor pad) on the first surface 210 of the insulating layer 21 . layer). The conductor layer 11 is formed using, for example, a semi-additive method in the same manner as the method for forming the conductor layer 10 described above. In forming the conductor layer 10 by the semi-additive method, pattern plating is performed using a plating resist having openings suitable for forming at least the conductor pads 1 . In the example of FIG. 6D, in addition to the conductor pad 1, a conductor layer 11 including a wiring pattern 111 and a conductor pad 112 is formed. Via conductors 40 are formed in through holes 40 a of insulating layer 21 . A conductor layer 10 is further formed on the outermost insulating layer 20 on the surface 3 b side of the core substrate 3 by the same method as the method for forming the conductor layer 11 .

図１の配線基板１００が製造される場合は、図６Ｅに示されるように、導体パッド１の表面１ａのような導体層１１の各導体パターンの露出面が粗化される。なお図６Ｅは、図６ＤのVIＥ部の拡大図を示している。導体層１１の露出面の粗化は任意の方法で行われ得る。例えば、黒化処理又はブラウン処理と呼ばれる表面酸化処理や、酸性の溶剤を用いたマイクロエッチング処理によって、導体層１１の露出面が粗化される。導体層１１の露出面は、例えば、算術平均粗さ（Ｒａ）で、０．３μｍ以上、０．６μｍ以下の面粗度を有するように粗化される。なお、導体層１１の粗化工程において、配線パターン１１１（図６Ｄ参照）の表面が粗化されないように、配線パターン１１１の表面を覆うレジスト膜（図示せず）が設けられてもよい。高周波信号の伝送特性に優れた配線パターン１１１が得られることがある。 When the wiring board 100 of FIG. 1 is manufactured, the exposed surface of each conductor pattern of the conductor layer 11, such as the surface 1a of the conductor pad 1, is roughened as shown in FIG. 6E. Note that FIG. 6E shows an enlarged view of the VIE portion of FIG. 6D. Roughening of the exposed surface of conductor layer 11 can be performed by any method. For example, the exposed surface of the conductor layer 11 is roughened by surface oxidation treatment called blackening treatment or browning treatment, or micro-etching treatment using an acidic solvent. The exposed surface of the conductor layer 11 is roughened so as to have a surface roughness of, for example, 0.3 μm or more and 0.6 μm or less in arithmetic mean roughness (Ra). In the step of roughening the conductor layer 11, a resist film (not shown) covering the surface of the wiring pattern 111 (see FIG. 6D) may be provided so that the surface of the wiring pattern 111 (see FIG. 6D) is not roughened. A wiring pattern 111 having excellent high-frequency signal transmission characteristics may be obtained.

図６Ｆに示されるように、本実施形態の配線基板の製造方法は、さらに、導体層１１、及び絶縁層２１の第１面２１０を覆う絶縁層２２（第２絶縁層）を形成することを含んでいる。コア基板３の表面３ｂ側には、さらに絶縁層２０が形成される。絶縁層２２及びさらに形成される絶縁層２０は、絶縁層２１と同様に、例えば、フィルム状のエポキシ樹脂の積層、並びに加熱及び加圧によって形成される。 As shown in FIG. 6F, the wiring board manufacturing method of the present embodiment further comprises forming an insulating layer 22 (second insulating layer) covering the conductor layer 11 and the first surface 210 of the insulating layer 21. As shown in FIG. contains. An insulating layer 20 is further formed on the surface 3 b side of the core substrate 3 . The insulating layer 22 and the further formed insulating layer 20 are formed, for example, by laminating a film-like epoxy resin, heating and pressing, similarly to the insulating layer 21 .

図６Ｆの例では、絶縁層２２上に、例えば導体層１１の形成方法と同様の方法で、導体層１２が形成されている。絶縁層２２には、導体層１２と一体的にビア導体４０が形成されている。また、コア基板３の表面３ｂ側には、さらに導体層１０が導体層１１の形成方法と同様の方法で形成されている。 In the example of FIG. 6F, the conductor layer 12 is formed on the insulating layer 22 by the same method as the method of forming the conductor layer 11, for example. A via conductor 40 is formed integrally with the conductor layer 12 in the insulating layer 22 . A conductor layer 10 is further formed on the surface 3 b side of the core substrate 3 by the same method as the formation method of the conductor layer 11 .

さらに、絶縁層２２及び導体層１２の上に絶縁層２３が形成され、コア基板３の表面３ｂ側の最も外側の絶縁層２０及び導体層１０の上には絶縁層２５が形成されている。絶縁層２３及び絶縁層２５は、例えば、前述した絶縁層２１の形成方法と同様の方法で形成される。そして、本実施形態の配線基板の製造方法では、絶縁層２２を貫通する貫通孔２２１が形成される。図６Ｆの例では、絶縁層２２と共に絶縁層２３も貫く貫通孔２２１が形成される。貫通孔２２１は、例えば、絶縁層２２及び絶縁層２３へのレーザー光の照射によって形成される。例えば、炭酸ガスレーザー光が照射される。導体パッド１は、レーザー光のストッパーとして機能し得る。 Furthermore, an insulating layer 23 is formed on the insulating layer 22 and the conductor layer 12 , and an insulating layer 25 is formed on the outermost insulating layer 20 and the conductor layer 10 on the surface 3 b side of the core substrate 3 . The insulating layer 23 and the insulating layer 25 are formed, for example, by a method similar to the method for forming the insulating layer 21 described above. In the wiring board manufacturing method of the present embodiment, the through holes 221 that penetrate the insulating layer 22 are formed. In the example of FIG. 6F, a through hole 221 is formed that penetrates the insulating layer 23 as well as the insulating layer 22 . The through-holes 221 are formed, for example, by irradiating the insulating layers 22 and 23 with laser light. For example, carbon dioxide laser light is applied. The conductor pad 1 can function as a laser light stopper.

図６Ｇには、図６ＦのVIＧ部における貫通孔２２１の形成後の状態が拡大して示されている。貫通孔２２１の形成によって、部品搭載領域を含む導体パッド１の表面１ａを底面に有する部品収容部Ｈが形成されている。このように本実施形態の配線基板の製造方法は、導体パッド１上の絶縁層２２に貫通孔２２１を形成することによって、底面に導体パッド１を備える部品収容部Ｈを形成することを含んでいる。 FIG. 6G shows an enlarged view of the VIG portion of FIG. 6F after the through holes 221 are formed. Formation of the through hole 221 forms a component housing portion H having a bottom surface 1a of the conductor pad 1 including the component mounting area. As described above, the wiring board manufacturing method of the present embodiment includes forming the component housing portion H having the conductor pad 1 on the bottom surface thereof by forming the through hole 221 in the insulating layer 22 on the conductor pad 1 . there is

図６Ｇに示されるように、貫通孔２２１の形成後の絶縁層２１の第１面２１０と導体パッド１との界面には、第１面２１０と導体パッド１とが離れている部分である１以上の離間部５が形成されている。すなわち、本実施形態の配線基板の製造方法において貫通孔２２１を形成することは、絶縁層２１の第１面２１０と導体パッド１との界面に、絶縁層２１と導体パッド１との離間部５を形成することを含んでいる。そのため、前述したように、導体パッド１に搭載される部品Ｅ（図６Ｊ参照）由来の歪みの蓄積などによる導体パッド１と絶縁層２１との界面剥離が抑制される。 As shown in FIG. 6G, at the interface between the first surface 210 of the insulating layer 21 and the conductor pad 1 after the formation of the through hole 221, there is a portion 1 where the first surface 210 and the conductor pad 1 are separated. The separation portion 5 described above is formed. That is, the formation of the through holes 221 in the wiring board manufacturing method of the present embodiment means that the separation portions 5 includes forming Therefore, as described above, interfacial peeling between the conductor pad 1 and the insulating layer 21 due to accumulation of strain derived from the component E (see FIG. 6J) mounted on the conductor pad 1 is suppressed.

離間部５は、例えば、後に詳述されるレーザー光の照射による貫通孔２２１の形成方法の一例におけるレーザー光からの受熱によって形成され得る。すなわち、レーザー光からの受熱による局所的で瞬間的な温度上昇によって、互いに異なる熱膨張率を有し得る導体パッド１及び絶縁層２１の構成材料が互いに異なる量で膨張し、各構成材料同士がその界面において局所的に分離する。その結果、離間部５が形成される。離間部５は、例えば、レーザー光が照射される貫通孔２２１の形成領域の真下の領域全体に渡って散在する第１面２１０の凹凸の頂部及び／又は底部において形成され得る。 The spacing portion 5 can be formed, for example, by receiving heat from a laser beam in an example of a method of forming the through holes 221 by laser beam irradiation, which will be described in detail later. That is, due to a local and instantaneous temperature rise due to the heat received from the laser beam, the constituent materials of the conductor pad 1 and the insulating layer 21, which may have different coefficients of thermal expansion, expand by different amounts. Separate locally at the interface. As a result, the separation portion 5 is formed. The spacing portions 5 can be formed, for example, at the tops and/or bottoms of the unevenness of the first surface 210 scattered over the entire area immediately below the formation area of the through holes 221 irradiated with laser light.

そして、本実施形態の配線基板の製造方法では、離間部５は、絶縁層２１の第１面２１０のうちの貫通孔２２１と平面視で重なる第１領域２１１における離間部５の占有率が、第２領域２１２における離間部５の占有率よりも高くなるように形成されてもよい。その場合、前述したように、第２領域２１２においては、絶縁層２１と導体パッド１とが大きな面積で接合し得ると共に、部品Ｅ（図６Ｊ参照）由来の歪みの蓄積などによる導体パッド１と絶縁層２１との間の広範な剥離が抑制される。すなわち、導体パッド１と絶縁層２１との界面剥離による不具合が防止され得る。なお、第２領域２１２は、前述したように第１面２１０における導体パッド１と接している領域２１３のうちの第１領域２１１以外の領域である。 In the wiring board manufacturing method of the present embodiment, the spaced portion 5 in the first region 211 overlapping the through hole 221 in plan view on the first surface 210 of the insulating layer 21 has a ratio of It may be formed so as to be higher than the occupancy rate of the spacing portion 5 in the second region 212 . In that case, as described above, in the second region 212, the insulating layer 21 and the conductor pad 1 can be bonded over a large area, and the distortion caused by the component E (see FIG. 6J) is accumulated. Extensive peeling from the insulating layer 21 is suppressed. In other words, problems due to interfacial peeling between the conductor pad 1 and the insulating layer 21 can be prevented. The second region 212 is a region other than the first region 211 among the regions 213 in contact with the conductor pads 1 on the first surface 210 as described above.

また図６Ｇに示される例では、第１領域２１１の面粗度が、先に参照した図６Ｅに示される第１面２１０の面粗度よりも低下している。その結果、第１領域２１１の面粗度が第２領域２１２の面粗度よりも低下している。このように本実施形態の配線基板の製造方法において貫通孔２２１を形成することは、絶縁層２１の第１面２１０の第１領域２１１の面粗度を低下させることを含み得る。 Also, in the example shown in FIG. 6G, the surface roughness of the first region 211 is lower than the surface roughness of the first surface 210 shown in FIG. 6E referred to above. As a result, the surface roughness of the first region 211 is lower than that of the second region 212 . Thus, forming the through holes 221 in the wiring board manufacturing method of the present embodiment can include reducing the surface roughness of the first region 211 of the first surface 210 of the insulating layer 21 .

図６Ｈ及び図６Ｉには、レーザー光Ｌの照射による貫通孔２２１の形成方法の一例が示されている。図６Ｈ及び図６Ｉの例では、レーザー光Ｌの照射位置Ｐを開始位置Ｐ１から終了位置Ｐｎまでピッチ送りしながら、貫通孔２２１が形成されるべき領域２２０全体に渡ってレーザー光Ｌを照射することによって貫通孔２２１が形成される。このように、貫通孔２２１を形成することは、絶縁層２２及び絶縁層２３における領域２２０全体に、照射位置Ｐを移動させながらレーザー光Ｌを照射することを含み得る。 6H and 6I show an example of a method of forming the through-holes 221 by irradiating the laser light L. As shown in FIG. In the example of FIGS. 6H and 6I, the laser beam L is irradiated over the entire region 220 where the through-hole 221 is to be formed, while pitch-feeding the irradiation position P of the laser beam L from the start position P1 to the end position Pn. A through hole 221 is thereby formed. Forming the through holes 221 in this way can include irradiating the entire region 220 in the insulating layer 22 and the insulating layer 23 with the laser light L while the irradiation position P is being moved.

開始位置Ｐ１から終了位置Ｐｎに至る照射位置Ｐの一連の移動中に、レーザー光Ｌは、照射位置Ｐ毎に任意の回数だけ照射される。また、照射位置Ｐの一連の移動と共に行われるレーザー光Ｌの照射は、１以上の任意の回数行われてもよい。例えば、照射位置Ｐの一連の移動毎の各照射位置Ｐにおけるレーザー光Ｌの照射回数（ショット数）は１回であってもよく、複数回であってもよい。また、レーザー光Ｌの照射を伴うレーザー光Ｌの照射位置Ｐの一連の移動は、１回だけ行われてもよく、複数回行われてもよい。例えば図６Ｉに示されるように、レーザー光Ｌの照射を伴うレーザー光Ｌの照射位置Ｐの一連の移動は３回行われてもよい。このように貫通孔２２１を形成すべくレーザー光Ｌを照射することは、開始位置Ｐ１から終了位置Ｐｎに至るレーザー光Ｌの照射位置Ｐの一連の移動を複数回行うことを含み得る。各照射位置Ｐでの照射回数や、一連の移動の回数などのレーザー光Ｌの照射条件を調整することによって、前述したような適度な占有率で離間部５を形成し得ることがある。 During a series of movement of the irradiation position P from the start position P1 to the end position Pn, the laser light L is irradiated for each irradiation position P an arbitrary number of times. Moreover, the irradiation of the laser beam L performed with a series of movement of the irradiation position P may be performed 1 or more arbitrary times. For example, the number of irradiations (the number of shots) of the laser light L at each irradiation position P for each series of movement of the irradiation position P may be one or more. Moreover, a series of movement of the irradiation position P of the laser light L accompanying the irradiation of the laser light L may be performed only once or may be performed multiple times. For example, as shown in FIG. 6I, a series of movements of the irradiation position P of the laser light L accompanied by the irradiation of the laser light L may be performed three times. Irradiating the laser light L to form the through hole 221 in this way can include performing a series of movement of the irradiation position P of the laser light L from the start position P1 to the end position Pn a plurality of times. By adjusting the irradiation conditions of the laser light L, such as the number of times of irradiation at each irradiation position P and the number of times of a series of movements, it may be possible to form the spaced portion 5 with an appropriate occupation rate as described above.

貫通孔２２１の形成後、好ましくは、前述した貫通孔４０ａ（図６Ｂ参照）のデスミア処理と同様にデスミア処理が行われる。 After forming the through-holes 221, desmearing is preferably performed in the same manner as the above-described desmearing of the through-holes 40a (see FIG. 6B).

図６Ｊに示されるように、導体パッド１に部品Ｅが載置される。例えば、はんだ若しくは銅などの金属ペレット、又は、導電性若しくは絶縁性のペーストが接着剤６として導体パッド１上に供給され、さらに、部品Ｅが載置される。接着剤６によって部品Ｅが導体パッド１に接合される。 A component E is placed on the contact pad 1 as shown in FIG. 6J. For example, a metal pellet such as solder or copper, or a conductive or insulating paste is applied as an adhesive 6 onto the conductor pads 1, and a component E is placed thereon. A component E is joined to the conductor pad 1 by an adhesive 6 .

そして、部品Ｅを覆う絶縁層２４（封止層）が、絶縁層２３の上に形成される。コア基板３の表面３ｂ側の絶縁層２５上には絶縁層２６が形成される。絶縁層２４及び絶縁層２６は、例えば、前述した絶縁層２１などの形成方法と同様の方法で形成される。その絶縁層２４の形成時に、絶縁層２４を構成するエポキシ樹脂などが、加熱及び加圧によって軟化して貫通孔２２１内に流入する。そして、貫通孔２２１内が、絶縁層２４を構成する樹脂で充填され、絶縁層２４を構成する樹脂で部品Ｅが貫通孔２２１内に封止される。 An insulating layer 24 (sealing layer) covering the component E is formed on the insulating layer 23 . An insulating layer 26 is formed on the insulating layer 25 on the surface 3 b side of the core substrate 3 . The insulating layer 24 and the insulating layer 26 are formed, for example, by a method similar to the method of forming the insulating layer 21 and the like described above. When the insulating layer 24 is formed, the epoxy resin or the like forming the insulating layer 24 is softened by heat and pressure and flows into the through hole 221 . Then, the inside of the through hole 221 is filled with the resin forming the insulating layer 24 , and the component E is sealed inside the through hole 221 with the resin forming the insulating layer 24 .

図６Ｋに示されるように、導体層１３、１４、並びに、ビア導体４１～４３が形成される。導体層１３には、外部回路との接続に用いられる接続パッド１３１、１３２が設けられる。導体層１３は、絶縁層２４及び絶縁層２３を貫通するビア導体４１によって導体層１２と接続される。導体層１４は、絶縁層２６及び絶縁層２５を貫通するビア導体４２によって導体層１０と接続される。そして接続パッド１３２は、部品Ｅ上の絶縁層２４を貫通するビア導体４３によって部品Ｅの電極Ｅ１と接続される。 As shown in FIG. 6K, conductor layers 13, 14 and via conductors 41-43 are formed. The conductor layer 13 is provided with connection pads 131 and 132 used for connection with an external circuit. The conductor layer 13 is connected to the conductor layer 12 by the insulating layer 24 and via conductors 41 penetrating the insulating layer 23 . The conductor layer 14 is connected to the conductor layer 10 by via conductors 42 penetrating the insulating layers 26 and 25 . The connection pad 132 is connected to the electrode E1 of the component E by a via conductor 43 penetrating the insulating layer 24 on the component E. As shown in FIG.

導体層１３、１４、ビア導体４１、４２は、前述した、導体層１１及びビア導体４０の形成方法と同様の方法及び同様の材料を用いて形成され得る。ビア導体４３の形成では、部品Ｅの電極Ｅ１に向かって、絶縁層２４の表面から例えば紫外線（ＵＶ）レーザー光を照射することによって電極Ｅ１を露出させる貫通孔が形成される。その貫通孔内に、導体層１３の形成と共にめっき膜を充填することによってビア導体４３が形成される。 Conductor layers 13 and 14 and via conductors 41 and 42 can be formed using the same method and material as the method for forming conductor layer 11 and via conductor 40 described above. In forming the via conductors 43 , through holes are formed to expose the electrodes E<b>1 of the component E by irradiating, for example, ultraviolet (UV) laser light from the surface of the insulating layer 24 toward the electrodes E<b>1 . A via conductor 43 is formed by filling the through-hole with a plating film while forming the conductor layer 13 .

その後、導体層１３及び絶縁層２４上にソルダーレジスト７が形成されると共に、導体層１４及び絶縁層２６上にもソルダーレジスト７が形成される。導体層１３上のソルダーレジスト７には接続パッド１３１、１３２を露出させる開口が設けられ、導体層１４上のソルダーレジスト７にも適宜開口が設けられる。ソルダーレジスト７及びその開口は、感光性のエポキシ樹脂又はポリイミド樹脂などを含む樹脂層の形成と、適切な開口パターンを有するマスクを用いた露光及び現像とによって形成される。以上の工程を経る事によって図１の例の配線基板１００が完成する。 After that, the solder resist 7 is formed on the conductor layer 13 and the insulating layer 24 , and the solder resist 7 is also formed on the conductor layer 14 and the insulating layer 26 . The solder resist 7 on the conductor layer 13 is provided with openings for exposing the connection pads 131 and 132, and the solder resist 7 on the conductor layer 14 is also appropriately provided with openings. The solder resist 7 and its openings are formed by forming a resin layer containing a photosensitive epoxy resin, polyimide resin, or the like, and exposing and developing using a mask having an appropriate opening pattern. The wiring substrate 100 shown in FIG. 1 is completed through the above steps.

なお、図５に例示される導体パッド１αが形成される場合は、例えば、図６Ｅを参照して説明された導体層１１の露出面の粗化において、導体パッド１αの低粗度部１ａｃ（図５参照）上にレジスト膜（図示せず）が設けられる。そうすることによって、周囲よりも低い面粗度を有する低粗度部１ａｃを設けることができる。 When the conductor pad 1α illustrated in FIG. 5 is formed, for example, in the roughening of the exposed surface of the conductor layer 11 described with reference to FIG. 5) is provided with a resist film (not shown). By doing so, it is possible to provide the low-roughness portion 1ac having a surface roughness lower than that of the surroundings.

実施形態の配線基板は、各図面に例示される構造、並びに、本明細書において例示される構造、形状、及び材料を備えるものに限定されない。例えば、導体パッド１の表面１ａ及び絶縁層２１の第１面２１０は、いずれも、凹凸を有していなくてもよい。前述したように、実施形態の配線基板は任意の積層構造を有し得る。例えば実施形態の配線基板はコア基板を含まないコアレス基板であってもよい。実施形態の配線基板は、任意の数の導体層及び絶縁層を有し得る。導体層１１は、外層側に１つ以上の絶縁層が積層されている任意の階層の導体層であり得る。貫通孔２２１は、図１などの例のようなテーパー形状を有していなくてもよい。 The wiring substrates of the embodiments are not limited to those having the structures illustrated in each drawing, and the structures, shapes, and materials illustrated in this specification. For example, neither the surface 1a of the conductor pad 1 nor the first surface 210 of the insulating layer 21 may have unevenness. As described above, the wiring board of the embodiment can have any laminated structure. For example, the wiring board of the embodiment may be a coreless board that does not include a core board. A wiring board of embodiments may have any number of conductor layers and insulating layers. The conductor layer 11 may be a conductor layer of any hierarchy in which one or more insulating layers are laminated on the outer layer side. The through-hole 221 does not have to have a tapered shape like the example shown in FIG.

実施形態の配線基板の製造方法は、各図面を参照して説明された方法に限定されない。例えば貫通孔２２１は、レーザー光の照射以外の発熱を伴う任意の方法で形成され得る。また貫通孔２２１は、発熱を伴わない、例えば適度な機械的衝撃によって離間部５が形成され得る任意の方法で形成されてもよい。導体層１０～１４はフルアディティブ法によって形成されてもよい。絶縁層２０～２６は、フィルム状の樹脂に限らず、任意の形態の樹脂を用いて形成され得る。実施形態の配線基板の製造方法には、前述された各工程以外に任意の工程が追加されてもよく、前述された工程のうちの一部が省略されてもよい。 The method for manufacturing the wiring board of the embodiment is not limited to the method described with reference to each drawing. For example, the through-holes 221 can be formed by any method involving heat generation other than laser light irradiation. Also, the through-holes 221 may be formed by any method that does not generate heat, for example, the separation portion 5 can be formed by moderate mechanical impact. The conductor layers 10-14 may be formed by a full additive method. The insulating layers 20 to 26 are not limited to film-shaped resin, and can be formed using any form of resin. Arbitrary steps may be added to the wiring board manufacturing method of the embodiment in addition to the steps described above, and some of the steps described above may be omitted.

１００配線基板
１、１α 導体パッド
１ａ導体パッドにおける絶縁層２１と反対側の表面
１ａａ貫通孔と重なる領域
１ａｂ絶縁層２２と重なる領域
１ａｃ低粗度部
１０～１４導体層
２１絶縁層（第１絶縁層）
２１ａフィラー
２１ｂ絶縁性樹脂
２１０第１面
２１１第１領域
２１２第２領域
２１３導体パッドと接している領域
２２絶縁層（第２絶縁層）
２２０貫通孔が形成されるべき領域
２２１貫通孔
５、５１～５３離間部
Ａ部品搭載領域
Ｌレーザー光
Ｈ部品収容部 100 Wiring substrate 1, 1α Conductive pad 1a Surface 1aa opposite to insulating layer 21 of conductive pad Region 1ab overlapping with through hole Region 1ac overlapping insulating layer 22 Low roughness portions 10 to 14 Conductive layer 21 Insulating layer (first insulation layer)
21a filler 21b insulating resin 210 first surface 211 first region 212 second region 213 region in contact with the conductor pad 22 insulating layer (second insulating layer)
220 area where through-holes are to be formed 221 through-holes 5, 51 to 53 spacing part A component mounting area L laser beam H component accommodating part

Claims

a first insulating layer having a first surface;
a conductor layer formed on the first surface and including a component mounting area;
a second insulating layer covering the first surface and the conductor layer and having a through hole exposing the component mounting area;
A wiring board comprising
the conductor layer includes a conductor pad that includes the component mounting area and is partially covered with the second insulating layer;
the first surface includes a first area overlapping the through hole in plan view and a second area other than the first area in the area in contact with the conductor pad;
The interface between the first surface and the conductor pad includes a separation portion, which is the portion where the first insulating layer and the conductor pad are separated.

2. The wiring board according to claim 1, wherein the occupancy of the spacing portion in the first region is higher than the occupancy of the spacing portion in the second region.

2. The wiring board according to claim 1, wherein the occupying ratio of said spacing portion in said first region is 5% or more and 20% or less.

2. The wiring board according to claim 1, wherein said first region has a surface roughness lower than that of said second region.

The wiring board according to claim 1,
The first insulating layer includes an insulating resin and a filler added to the insulating resin,
The volume content of the filler in the first insulating layer is 30% or more and 80% or less.

6. The wiring board according to claim 5, wherein said spacing portion is interposed between said filler and said insulating resin.

6. The wiring board according to claim 5, wherein the spacing portion is interposed between the filler or the insulating resin and the conductor pad.

2. The wiring board according to claim 1, wherein a region of the surface of the conductor pad opposite to the first insulating layer, which overlaps with the through hole, is covered with the second insulating layer of the surface. It includes a portion having a surface roughness lower than that of the region in which it is located.

providing a first insulating layer having a first surface;
forming a conductor layer including a conductor pad on the first surface;
forming a second insulating layer covering the conductor layer and the first surface;
forming a component housing portion having the conductor pad on its bottom surface by forming a through hole in the second insulating layer on the conductor pad;
A wiring board manufacturing method comprising
Forming the through hole includes forming a separation portion between the first insulating layer and the conductor pad at the interface between the first surface and the conductor pad.

10. The method of manufacturing a wiring board according to claim 9, wherein the spaced portion has a occupancy ratio of the spaced portion in a first region overlapping the through hole in plan view on the first surface. It is formed so as to have a higher occupancy than the spaced portion in a region other than the first region in contact with the conductor pad.

10. The method of manufacturing a wiring board according to claim 9, wherein the formation of the through-hole includes applying a laser beam to the entire region of the second insulating layer where the through-hole is to be formed while moving the irradiation position. Including irradiating.

12. The method of manufacturing a wiring board according to claim 11, wherein the irradiation with the laser light includes performing a series of movements of the irradiation position of the laser light from a start position to an end position a plurality of times.

13. The method of manufacturing a wiring board according to claim 12, wherein the number of times of irradiation with the laser light at each irradiation position is one for each of the series of movements of the irradiation position.

10. The method of manufacturing a wiring board according to claim 9, further comprising roughening the first surface of the first insulating layer before forming the conductor layer,
Forming the through-hole includes reducing the surface roughness of a region of the first surface that overlaps the through-hole in plan view.