JP3142912B2 - Solder material - Google Patents

Solder material

Info

Publication number
JP3142912B2
JP3142912B2 JP23793491A JP23793491A JP3142912B2 JP 3142912 B2 JP3142912 B2 JP 3142912B2 JP 23793491 A JP23793491 A JP 23793491A JP 23793491 A JP23793491 A JP 23793491A JP 3142912 B2 JP3142912 B2 JP 3142912B2
Authority
JP
Japan
Prior art keywords
layer
solder material
solder
bump
base metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23793491A
Other languages
Japanese (ja)
Other versions
JPH0577083A (en
Inventor
俊典 小柏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK filed Critical Tanaka Denshi Kogyo KK
Priority to JP23793491A priority Critical patent/JP3142912B2/en
Publication of JPH0577083A publication Critical patent/JPH0577083A/en
Application granted granted Critical
Publication of JP3142912B2 publication Critical patent/JP3142912B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明ははんだ材料、詳しくは半
導体装置などAu 被膜が施された電極部のはんだ付け用
に使用されるPb-Sn 系はんだ材料に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder material, and more particularly to a Pb-Sn solder material used for soldering an Au-coated electrode portion such as a semiconductor device.

【0002】[0002]

【従来技術とその課題】従来、半導体装置の接続、詳し
くはワイヤレスボンディング法、特にフリップチップボ
ンディング法またはテープキャリアボンディング法によ
り半導体チップを基板に接続する場合、図1に示すよう
にチップ1上に形成されたTi 層、Ni層、Au 層から
なる下地金属2上にPb-Sn 系のはんだバンプ3を圧着
して設け(図1A)、それをフラックス中所定温度でリ
フロー処理をすることによって、前記バンプ3上に基板
4のNi 層を溶着して接続している(図1B)。
2. Description of the Related Art Conventionally, when a semiconductor chip is connected to a substrate by a semiconductor device connection, more specifically, a wireless bonding method, in particular, a flip chip bonding method or a tape carrier bonding method, as shown in FIG. A Pb-Sn solder bump 3 is provided by pressing on a base metal 2 formed of a Ti layer, a Ni layer, and an Au layer (FIG. 1A), and is subjected to a reflow treatment at a predetermined temperature in a flux. The Ni layer of the substrate 4 is welded and connected to the bumps 3 (FIG. 1B).

【0003】上記下地金属2のAu 層は、高濃度であっ
てNi 層の酸化防止用として必要であるが、このAu 層
にはんだ材料であるバンプ3が接合するため、その接合
界面領域のはんだ材料中にAu が溶出し該領域にAu-S
n 化合物が析出して脆化し、疲労寿命低下の原因となる
など半導体装置の信頼性を損なうことが問題点となって
いた。
The Au layer of the base metal 2 has a high concentration and is necessary for preventing the Ni layer from being oxidized. However, since the bump 3 which is a solder material is bonded to the Au layer, the solder layer in the bonding interface region is formed. Au elutes into the material and Au-S
There has been a problem in that the reliability of the semiconductor device is impaired, for example, the precipitation of the n-compounds, embrittlement and reduction in fatigue life.

【0004】その問題点を解消せんとして従来は、200
〜300 nm(ナノメ−タ)程度のAu層の膜厚を、100 nm
程度(接合界面領域のAu 濃度は約0.3 wt%)に薄くす
る改良が施されているが、その場合の蒸着法、メッキ法
など膜形成手段では膜厚にバラツキが生じたり、均一な
膜厚分布が得られないことから、Au 膜の厚い部分がで
きてしまい結果として装置の故障発生を防止し得なかっ
た。
In order to solve the problem, conventionally, 200
The thickness of the Au layer of about 300 nm (nanometer) is
Improvements have been made to reduce the film thickness to about the same level (the Au concentration in the bonding interface region is about 0.3 wt%). Since no distribution was obtained, a thick portion of the Au film was formed, and as a result, failure of the device could not be prevented.

【0005】本発明は斯る従来事情に鑑み、Au 被膜が
施された電極部のAu 層とはんだ材料との接合に伴う脆
化を防止して疲労寿命を改善するPb-Sn 系はんだ材料
を提供することを目的とする。
In view of the above-mentioned circumstances, the present invention provides a Pb-Sn-based solder material which prevents embrittlement due to joining between an Au layer of an Au-coated electrode portion and a solder material and improves fatigue life. The purpose is to provide.

【0006】[0006]

【課題を解決するための手段】斯る本発明のはんだ材料
は、Pb-Sn はんだ中に、0.0001〜0.5 wt%のP、また
は0.0001〜1.0 wt%のSb を添加せしめたことを特徴と
する。
The solder material of the present invention is characterized in that 0.0001 to 0.5 wt% of P or 0.0001 to 1.0 wt% of Sb is added to Pb-Sn solder. .

【0007】[0007]

【作用】本発明によれば、Pb-Sn はんだ中に、P(リ
ン)またはSb (アンチモン)が添加されることによっ
て、該はんだ材料をAu 層に接合させたときに、はんだ
材料中に析出するAu-Sn 化合物の結晶粒が微細化さ
れ、かつ均一な分散状態が得られ、従ってAu-Sn化合
物の析出に伴う脆化を防止することができる。
According to the present invention, when P (phosphorus) or Sb (antimony) is added to Pb-Sn solder, when the solder material is bonded to the Au layer, it is deposited in the solder material. Thus, the crystal grains of the Au-Sn compound are refined and a uniform dispersion state is obtained, so that embrittlement accompanying precipitation of the Au-Sn compound can be prevented.

【0008】上記P,Sb は、それぞれの添加量が0.00
01wt%未満では前述した作用が得られず、Pの添加量が
0.5 wt%を越える場合、Sb の添加量が1.0 wt%を越え
る場合では、はんだ材料自体が硬くなって脆化し接合強
度、疲労寿命が低下する。従って、P,Sb の添加量は
Pが0.0001〜0.5 wt%、Sb が0.0001〜1.0 wt%とす
る。
The above P and Sb are added in an amount of 0.00
If the content is less than 01 wt%, the above-mentioned effects cannot be obtained, and the amount of P added is
If the amount exceeds 0.5 wt%, and if the added amount of Sb exceeds 1.0 wt%, the solder material itself becomes hard and brittle, and the bonding strength and fatigue life decrease. Therefore, the addition amounts of P and Sb are set to 0.0001 to 0.5 wt% for P and 0.0001 to 1.0 wt% for Sb.

【0009】[0009]

【実施例】一般的に使用されているPb-Sn 系はんだ材
料(Snを2〜5wt%含有)の中からPb-2Sn はんだ
(Sn を2wt%含有)およびPb-5Sn はんだ(Sn を
5wt%含有)を選択し、それらはんだ材料にPを0〜0.
6 wt%、Sb を0〜2.0 wt%の範囲で所定量添加して表
に記載したNo.1〜21の試料を作製した。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Pb-2Sn solder (containing 2 wt% Sn) and Pb-5Sn solder (containing 5 wt% Sn) from among Pb-Sn based solder materials (containing 2 to 5 wt% Sn) which are generally used. Containing), and set P to 0 to 0.
Samples of Nos. 1 to 21 shown in the table were prepared by adding a predetermined amount of 6 wt% and Sb in a range of 0 to 2.0 wt%.

【0010】各試料を用いて、それぞれ図1(A)
(B)で説明した通りバンプ3を前記下地金属2のAu
層上に形成した後、該バンプ3上に基板4のNi 層を溶
着し、各試料度にそれぞれ熱サイクル数を測定し疲労強
度(寿命)をみた。
Using each sample, FIG. 1 (A)
As described in (B), the bump 3 is made of Au of the base metal 2.
After forming on the layer, the Ni layer of the substrate 4 was welded on the bump 3, and the number of thermal cycles was measured for each sample to check the fatigue strength (life).

【0011】上記各試料は、それぞれの組成からなるは
んだ材料を急冷凝固法により細いワイヤー状に作製され
たもので、その各試料のワイヤー先端を加熱してボール
を形成し、該ボールを下地金属2のAu 層上に圧着させ
た状態で試料ワイヤーを引張ることにより切断して前記
バンプ3を形成したものである。又、下地金属2のAu
層は、Au が及ぼす影響を顕著にするために,従来一般
的な膜厚200 〜300 nmより若干大きい330 nm程度(接合
界面領域のAu 濃度は約1wt%)とした。
Each of the above-mentioned samples is prepared by thinning a solder material having the respective composition into a thin wire by a rapid solidification method. The tip of the wire of each of the samples is heated to form a ball. The bump 3 was formed by cutting the sample wire while pulling it on the Au layer 2 by pulling. Also, Au of the base metal 2
The thickness of the layer is set to about 330 nm (the Au concentration in the bonding interface region is about 1 wt%), which is slightly larger than the conventional general film thickness of 200 to 300 nm in order to make the effect of Au remarkable.

【0012】熱サイクル数の測定は、各試料を図1
(B)に示す組付け状態で、室温・5分→−55℃・3
0分→室温・5分→−150℃・30分を一サイクルと
し、電気抵抗がバンプ当たり10Ωに達したサイクル数
を測定した。その測定結果は表の通りであった。
For the measurement of the number of heat cycles, each sample was measured as shown in FIG.
In the assembled state shown in (B), at room temperature, 5 minutes → -55 ° C, 3
One cycle was defined as 0 minutes → room temperature · 5 minutes → −150 ° C. · 30 minutes, and the number of cycles at which the electric resistance reached 10Ω per bump was measured. The measurement results are as shown in the table.

【表1】 [Table 1]

【0013】この技術分野においては、熱サイクル数に
関し1000サイクル前後が判断基準となっていることか
ら、それを考慮して表をみれば、Pの添加については
(試料2〜6,14〜17)、添加量 0.0001 wt%が下
限であり、0.5 wt%が上限であることが確認された。
又、Sb の添加については(試料7〜12,18〜2
1)、添加量 0.0001 wt%が下限であり、1.0 wt%が上
限であることが確認された。尚、上記P,Sn の上限値
0.5wt%,1.0 wt%は該値を微少量越える場合でも熱サ
イクルが1000サイクル前後ではあるが、前記上限値で熱
サイクル数が下降傾向にあること、および増量に応じた
効果が得られないことを考慮して前記上限値とした。
[0013] In this technical field, the number of thermal cycles is around 1000 cycles as a criterion. Therefore, considering the table, the addition of P (samples 2 to 6, 14 to 17 ), The lower limit was 0.0001 wt%, and the upper limit was 0.5 wt%.
Regarding the addition of Sb, see (Samples 7 to 12, 18 to 2
1) It was confirmed that 0.0001 wt% was the lower limit and 1.0 wt% was the upper limit. In addition, the upper limit of the above P and Sn
Although the thermal cycle is about 1000 cycles even when the amount slightly exceeds 0.5 wt% and 1.0 wt%, the number of thermal cycles tends to decrease at the above upper limit, and the effect according to the increase cannot be obtained. In consideration of this, the upper limit was set.

【0014】上記実施例においては、半導体装置の接続
用はんだ材料として説明したが、その用途に制限されな
いことは容易に理解されよう。又、チップ1上に形成さ
れた下地金属2は、Ti 層、Ni 層、Au 層からなる多
層膜の場合を説明したが、それに代えて Cr 層、Cu
層、Au 層の多層膜についても同様の効果が得られる。
さらに、上記はんだ材料は、急冷凝固法により細いワイ
ヤー状に作製された場合を示したが、それに限定される
ものではなく一般的な製造法によることも自由である。
In the above embodiment, the solder material for connection of the semiconductor device has been described, but it is easily understood that the use is not limited. Also, the case where the base metal 2 formed on the chip 1 is a multilayer film composed of a Ti layer, a Ni layer, and an Au layer has been described.
The same effect can be obtained with a multilayer film including a Au layer and an Au layer.
Furthermore, although the case where the above-mentioned solder material is manufactured in a thin wire shape by the rapid solidification method has been described, the present invention is not limited thereto, and a general manufacturing method may be freely used.

【0015】[0015]

【効果】本発明によれば、PまたはSb の添加によっ
て、はんだ材料をAu 濃度の高い層に接合させたとき
に、はんだ材料中にAu-Sn 化合物が析出することに伴
う脆化を防止して疲労寿命を改善することができ、この
はんだ材料を使用した製品の信頼性を向上させることが
できる。
According to the present invention, by adding P or Sb, when a solder material is joined to a layer having a high Au concentration, embrittlement due to precipitation of an Au-Sn compound in the solder material is prevented. As a result, the fatigue life can be improved, and the reliability of a product using this solder material can be improved.

【0016】又、Au 層の膜厚を薄化する従来技術の不
具合もなく、膜形成手段が容易となる等の副次的効果も
ある。
Further, there are no disadvantages of the prior art for thinning the thickness of the Au layer, and there are secondary effects such as easy film forming means.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明はんだ材料の使用例を説明する断面図FIG. 1 is a cross-sectional view illustrating an example of use of a solder material of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 下地金属 3 はんだバンプ 4 基板 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Base metal 3 Solder bump 4 Substrate

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) B23K 35/26 C22C 11/00 - 11/10 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 7 , DB name) B23K 35/26 C22C 11/00-11/10

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】Au 被膜が施された電極部のはんだ付け用
はんだ材料において、Sn を2〜5wt%含有したPb 基
はんだ中に、0.0001〜0.5 wt%のP、または0.0001〜1.
0 wt%のSb を添加せしめたことを特徴とするはんだ材
料。
In a solder material for soldering an electrode portion provided with an Au coating, a Pb-based solder containing 2 to 5 wt% of Sn contains 0.0001 to 0.5 wt% of P or 0.0001 to 1.
A solder material to which 0 wt% of Sb has been added.
JP23793491A 1991-09-18 1991-09-18 Solder material Expired - Fee Related JP3142912B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23793491A JP3142912B2 (en) 1991-09-18 1991-09-18 Solder material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23793491A JP3142912B2 (en) 1991-09-18 1991-09-18 Solder material

Publications (2)

Publication Number Publication Date
JPH0577083A JPH0577083A (en) 1993-03-30
JP3142912B2 true JP3142912B2 (en) 2001-03-07

Family

ID=17022626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23793491A Expired - Fee Related JP3142912B2 (en) 1991-09-18 1991-09-18 Solder material

Country Status (1)

Country Link
JP (1) JP3142912B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3160583B2 (en) 1999-01-27 2001-04-25 日本特殊陶業株式会社 Resin substrate

Also Published As

Publication number Publication date
JPH0577083A (en) 1993-03-30

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