JPH08148496A - Semiconductor device and bump therefor - Google Patents
Semiconductor device and bump thereforInfo
- Publication number
- JPH08148496A JPH08148496A JP30996794A JP30996794A JPH08148496A JP H08148496 A JPH08148496 A JP H08148496A JP 30996794 A JP30996794 A JP 30996794A JP 30996794 A JP30996794 A JP 30996794A JP H08148496 A JPH08148496 A JP H08148496A
- Authority
- JP
- Japan
- Prior art keywords
- platinum
- electrode
- alloy
- bump
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、所謂バンプを用い
て、半導体回路チップを基板もしくはリード電極に接続
することにより実装されるようにした半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is mounted by connecting a semiconductor circuit chip to a substrate or lead electrodes by using so-called bumps.
【０００２】[0002]
【従来の技術】近年、電子機器の小型・軽量化及び薄型
化に伴い、集積回路化した半導体チップの実装におい
て、薄型で高密度のものが要求されてきている。これら
の半導体チップを実装する技術としては、ワイヤボンデ
ィング、ＴＡＢのフィルムキャリア、フリップチップ等
が実用化されている。このうちフリップチップ方式で
は、半導体チップの電極上にバンプを固着し、この面を
プリント基板やガラス基板に対向させて、バンプと基板
電極とを半田等の低融点金属によって接続する。またＴ
ＡＢ方式では、リード先端が錫メッキされたＴＡＢテー
プにバンプを介してチップを接続するが、これらの方式
は、高密度化が要求される実装において多用されてい
る。2. Description of the Related Art In recent years, as electronic devices have become smaller, lighter and thinner, there has been a demand for thin and high-density packaging of semiconductor chips integrated into an integrated circuit. As techniques for mounting these semiconductor chips, wire bonding, TAB film carriers, flip chips, etc. have been put into practical use. Among them, in the flip-chip method, bumps are fixed on the electrodes of the semiconductor chip, this surface is made to face a printed circuit board or a glass substrate, and the bumps and the substrate electrodes are connected by a low melting point metal such as solder. See also T
In the AB method, a chip is connected to a TAB tape having lead tips tin-plated via bumps, but these methods are often used in packaging where high density is required.
【０００３】図１は、バンプ用金ワイヤを用いたフリッ
プチップ法による半導体チップの実装例を示している。
図１（ａ）において、半導体チップ１０のアルミニウム
電極１１上に、金ワイヤ１２の先端にて放電による溶融
により形成したボール１３が熱圧着もしくは超音波を併
用した熱圧着により接合される。更に、ボール１３の直
上部でワイヤ１２を切断して、図１（ｂ）に示すように
金バンプ１４を電極１１上に形成する。FIG. 1 shows an example of mounting a semiconductor chip by a flip chip method using a bump gold wire.
In FIG. 1A, a ball 13 formed by melting by electric discharge at the tip of a gold wire 12 is bonded onto an aluminum electrode 11 of a semiconductor chip 10 by thermocompression bonding or thermocompression bonding using ultrasonic waves. Further, the wire 12 is cut just above the ball 13 to form a gold bump 14 on the electrode 11 as shown in FIG.
【０００４】次に、図１（ｃ）に示すようにプリント基
板等の基板１５上で銅により形成された配線パターンの
電極部１６に、スクリーン印刷法等により半田ペースト
層１７を形成する。図１（ｄ）に示すように半導体チッ
プ１０上に形成された金バンプ１４と基板１５の電極部
１６とを位置合わせしてマウントする。そして、図１
（ｅ）に示すようにリフロー半田付けにより、半導体チ
ップ１０と基板１５とが接続されるというものである。Next, as shown in FIG. 1C, a solder paste layer 17 is formed on the electrode portion 16 of the wiring pattern formed of copper on the substrate 15 such as a printed circuit board by a screen printing method or the like. As shown in FIG. 1D, the gold bumps 14 formed on the semiconductor chip 10 and the electrode portions 16 of the substrate 15 are aligned and mounted. And FIG.
As shown in (e), the semiconductor chip 10 and the substrate 15 are connected by reflow soldering.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述の
例のように実装される半導体装置において、特に金バン
プ１４のリフロー半田付け時や高温保管試験時に、該金
バンプ１４の金が所謂、半田くわれを起こし、接続不良
が生じるという問題があった。However, in the semiconductor device mounted as in the above-mentioned example, the gold of the gold bumps 14 is so-called solder when the reflow soldering of the gold bumps 14 or the high temperature storage test is performed. There was a problem of causing breakage and poor connection.
【０００６】この発明はかかる実情に鑑み、半田くわれ
を有効に減少し得る半導体装置及び半導体装置用バンプ
等を提供するものである。In view of the above situation, the present invention provides a semiconductor device, a bump for a semiconductor device, etc. which can effectively reduce solder shaving.
【０００７】[0007]
【課題を解決するための手段】本発明による半導体装置
は、半導体チップ上に形成したアルミニウム電極もしく
はアルミニウム合金電極上に、純白金もしくは白金合金
から成るバンプが接続され、基板電極又はリード電極に
対して錫もしくは錫鉛合金等の低融点金属を介して、前
記バンプを接続するようにしたものである。In a semiconductor device according to the present invention, a bump made of pure platinum or a platinum alloy is connected to an aluminum electrode or an aluminum alloy electrode formed on a semiconductor chip, and a bump is formed on the substrate electrode or a lead electrode. The bumps are connected via a low melting point metal such as tin or a tin-lead alloy.
【０００８】本発明の半導体装置において、前記アルミ
ニウム電極もしくはアルミニウム合金電極上に、チタ
ン，ニッケル，チタン−タングステン合金，クロム及び
銅等の少なくとも１種から成り、その膜厚が０．００１
ミクロン以上、１ミクロン以下の薄膜が形成され、この
薄膜上に前記バンプが形成される。In the semiconductor device of the present invention, at least one of titanium, nickel, titanium-tungsten alloy, chromium, copper and the like is formed on the aluminum electrode or aluminum alloy electrode, and the thickness thereof is 0.001.
A thin film having a thickness of not less than 1 micron and not more than 1 micron is formed, and the bump is formed on the thin film.
【０００９】また、本発明の半導体装置用バンプは、半
導体チップ上に形成した電極に接続されるべきバンプで
あって、白金又は白金合金から成り、直径が１０ミクロ
ン以上、５００ミクロン以下としたものである。The semiconductor device bump of the present invention is a bump to be connected to an electrode formed on a semiconductor chip, and is made of platinum or a platinum alloy and has a diameter of 10 microns or more and 500 microns or less. Is.
【００１０】また、本発明のバンプ形成用の白金極細線
は、白金の純度が９５％以上であり、線径が１０ミクロ
ン以上、７０ミクロン以下としたものである。本発明の
バンプ形成用の白金極細線において、金，パラジウム及
びインジウム等の少なくとも１種が、５重量％未満であ
り、その残部が白金から成ることを特徴とする。The platinum fine wire for bump formation of the present invention has a purity of platinum of 95% or more and a wire diameter of 10 microns or more and 70 microns or less. The platinum ultrafine wire for bump formation of the present invention is characterized in that at least one kind of gold, palladium, indium, etc. is less than 5% by weight, and the balance is platinum.
【００１１】また、本発明の半導体装置の製造方法は、
ワイヤボンディング装置におけるキャピラリに白金又は
白金合金の極細線を挿通し、該キャピラリ先端から引き
出した前記白金又は白金合金の極細線の先端を、放電に
より溶融することによりボール状に形成し、前記ボール
状の前記極細線を、前記キャピラリによってチップ電極
上に熱圧着させ、前記ボール状の直上部にて前記極細線
を切断し、前記チップ電極に対してバンプが形成・接続
されるようにしたものである。The semiconductor device manufacturing method of the present invention is
An ultrafine wire of platinum or a platinum alloy is inserted into a capillary in a wire bonding device, and the tip of the platinum or platinum alloy ultrafine wire pulled out from the tip of the capillary is formed into a ball shape by melting it by electric discharge. The ultrafine wire is thermocompression bonded onto the chip electrode by the capillary, and the ultrafine wire is cut right above the ball shape so that bumps are formed and connected to the chip electrode. is there.
【００１２】[0012]
【作用】この発明は、半導体チップ上に形成したアルミ
ニウム電極もしくはアルミニウム合金電極上に、純白金
もしくは白金合金から成るバンプを接続すると共に、基
板電極もしくはＴＡＢにおけるリード電極に、錫もしく
は錫鉛合金等の低融点金属を介して該バンプを接続した
半導体装置を提供する。白金は、金と比較して融点が高
く、また、接合後や高温での動作試験中に接合部にて相
互拡散する。これにより錫，鉛との合金が形成されて
も、金の場合と比較して熱的に安定であり、接合信頼性
が高く、半田くわれの少ないバンプ接続構造を実現す
る。According to the present invention, bumps made of pure platinum or a platinum alloy are connected to an aluminum electrode or an aluminum alloy electrode formed on a semiconductor chip, and tin or a tin-lead alloy is used as a substrate electrode or a lead electrode in a TAB. There is provided a semiconductor device in which the bumps are connected via the low melting point metal. Platinum has a higher melting point than gold and also interdiffuses at the joint after joining and during operation test at high temperature. As a result, even if an alloy of tin and lead is formed, it is possible to realize a bump connection structure that is more thermally stable, has higher bonding reliability, and less solder leaching than gold.
【００１３】バンプ金属として、白金以外の高融点金属
は、アルミニウム電極側への接合性が十分でなく、また
酸化傾向が強いものでも、接合が問題となる。アルミニ
ウム電極は、その表面が一般には酸化膜で覆われてい
る。従って、バンプを接続するためには、その酸化膜を
破壊して接続する必要があり、バンプの密着性や、バン
プとアルミニウム金属の相互拡散後の信頼性を高めるた
めには、半導体チップ上に形成したアルミニウム電極も
しくはアルミニウム合金電極上に、Ｔｉ，Ｎｉ，ＴｉＷ
合金，Ｃｒ，Ｃｕ等の１種または２種以上で成り、合計
厚みが０．００１μｍ以上、１μｍ以下の薄膜を形成
し、該薄膜上に純白金もしくは白金合金から成るバンプ
を接続することが有効である。As a bump metal, a refractory metal other than platinum has a problem in bonding even if it has insufficient bondability to the aluminum electrode side and has a strong oxidation tendency. The surface of the aluminum electrode is generally covered with an oxide film. Therefore, in order to connect the bumps, it is necessary to break the oxide film to connect the bumps, and in order to improve the adhesion of the bumps and the reliability after the mutual diffusion of the bumps and the aluminum metal, the bumps should be formed on the semiconductor chip. Ti, Ni, TiW is formed on the formed aluminum electrode or aluminum alloy electrode.
It is effective to form a thin film of one kind or two or more kinds of alloys, Cr, Cu, etc., with a total thickness of 0.001 μm or more and 1 μm or less, and connect bumps made of pure platinum or platinum alloy on the thin film. Is.
【００１４】薄膜が０．００１μｍ以下の厚みでは、ア
ルミニウム表面を均一に覆うことが困難で、薄膜形成の
効果が少なく、また、１μｍ以上の薄膜を形成しても、
効果はほぼ一定であり、コスト高となる。If the thin film has a thickness of 0.001 μm or less, it is difficult to uniformly cover the aluminum surface, the effect of thin film formation is small, and even if a thin film of 1 μm or more is formed,
The effect is almost constant and the cost is high.
【００１５】バンプの接続方法としては、白金又は白金
合金から成り、直径が１０μｍ以上５０μｍ以下である
球形バンプを用い、チップの各電極に位置合わせし、配
列して接続することが好ましい。この接合は、熱圧着又
は超音波を併用して熱圧着する。直径１０μｍ以下で
は、接合時の変形量を十分にとれず、すべてのバンプを
安定して接続することが困難であり、また、５００μｍ
以上では、狭ピッチの要求に有効に対応することが困難
となる。As a method of connecting the bumps, it is preferable to use spherical bumps made of platinum or a platinum alloy and having a diameter of 10 μm or more and 50 μm or less, and aligning and arranging with each electrode of the chip for connection. This joining is performed by thermocompression bonding or ultrasonic bonding together. If the diameter is 10 μm or less, the amount of deformation at the time of joining cannot be sufficiently taken, and it is difficult to stably connect all the bumps.
As described above, it becomes difficult to effectively meet the demand for a narrow pitch.
【００１６】また、本発明のバンプ形成用の白金極細線
は、白金バンプの純度９５％以上が好ましい。白金純度
９５％未満では、硬度が高く、このため接合時にチップ
へのダメージを与える危険性が高まる。ボールの形成
は、極細線にした白金又は白金合金を一定寸法に切断
し、溶解させることにより、球形で精度の高いボールが
得られる。一定の球形を得るためには、極細線の線径が
細い程、一定寸法に切断する長さが長くなり、球形寸法
精度が高くなるが、通常の伸線では、直径１０μｍ未満
の伸線が困難であること、また取扱いが容易でなくな
る。また、７０μｍを超える径では、切断精度が悪く、
特に球形寸法精度の点で好ましくない。アルミニウム電
極側への接続は前述したようにボールを事前に形成し
て、配列接合する方法の他に、通常のワイヤボンディン
グ装置により、ボールボンディングを行って、バンプを
形成するスタッドバンプ方式を採用することもできる。The platinum ultrafine wire for bump formation of the present invention preferably has a platinum bump purity of 95% or more. If the platinum purity is less than 95%, the hardness is high, and therefore the risk of damaging the chip during bonding increases. The balls are formed by cutting platinum or a platinum alloy formed into an ultrafine wire into a predetermined size and melting the platinum or platinum alloy to obtain spherical balls with high accuracy. In order to obtain a constant spherical shape, the finer the wire diameter, the longer the length for cutting into a certain dimension, and the higher the dimensional accuracy of the spherical shape. However, in ordinary wire drawing, wire drawing with a diameter of less than 10 μm It is difficult and difficult to handle. Further, when the diameter exceeds 70 μm, the cutting accuracy is poor,
In particular, it is not preferable in terms of spherical dimensional accuracy. As the connection to the aluminum electrode side, in addition to the method of forming the balls in advance and array-bonding as described above, the stud bump method of forming the bumps by ball-bonding with a normal wire bonding device is adopted. You can also
【００１７】本発明の白金極細線によれば、放電によっ
て真球度が高く、且つ表面に酸化膜のないボールを容易
に形成することができる。また、アルミニウム電極膜へ
の接合は、上述したように、表面の酸化膜を破壊して接
合することが必要であり、特に酸化膜厚が厚くて接合性
が劣化する場合には、白金を合金化して、ボール硬度を
上げる対策が有効である。金，パラジウム，インジウム
の５％以下の添加で、かなりの改善効果を得ることがで
きる。また、その添加量が５％を超えると、ボールが硬
くなると同時に、ボール形成性も不安定である。また他
の合金元素添加では、ボールの真球度が劣化してしまう
ため好ましくない。According to the platinum ultrafine wire of the present invention, it is possible to easily form a ball having a high sphericity and no oxide film on the surface by discharge. Further, as described above, the bonding to the aluminum electrode film requires that the oxide film on the surface be destroyed and bonded. Especially, when the oxide film thickness is large and the bondability is deteriorated, platinum alloy is used. It is effective to take measures to increase the ball hardness. A significant improvement effect can be obtained by adding 5% or less of gold, palladium and indium. Further, if the addition amount exceeds 5%, the ball becomes hard and, at the same time, the ball forming property becomes unstable. Further, addition of other alloy elements is not preferable because the sphericity of the ball deteriorates.
【００１８】このように本発明によれば、半田接合性が
良好で、熱的安定性が高く、しかも長期間高い信頼性を
保証し得る半導体実装が可能となる。本発明は半田接合
以外に、錫合金，鉛合金，錫−インジウム合金，鉛−イ
ンジウム合金等の低融点金属での接合にも応用できる。As described above, according to the present invention, it is possible to perform semiconductor mounting which has good solder jointability, high thermal stability, and high reliability for a long period of time. The present invention can be applied to joining with a low melting point metal such as a tin alloy, a lead alloy, a tin-indium alloy, and a lead-indium alloy, in addition to the solder joining.
【００１９】[0019]
【実施例】次に、本発明の実施例を詳細に説明する。こ
の実施例において、図１で既に説明したようにボールボ
ンディング方式を採用して、白金バンプを形成するもの
とする。本実施例では、半導体チップ上に形成されてい
る電極上に白金ワイヤ（白金極細線）を用いて、ボール
ボンディング法によりバンプを形成すべきボールを接続
した。EXAMPLES Next, examples of the present invention will be described in detail. In this embodiment, the platinum bumps are formed by using the ball bonding method as already described in FIG. In the present example, a platinum wire (platinum ultrafine wire) was used on the electrode formed on the semiconductor chip to connect the ball for forming the bump by the ball bonding method.
【００２０】この場合、ワイヤボンディング装置を用
い、キャピラリより白金（又は白金合金）の極細線を挿
通し、該キャピラリ先端から引き出した白金又は白金合
金の極細線の先端を、放電によって溶融することによ
り、ボール状に形成し、このボール状の極細線を、キャ
ピラリによってチップ電極上に熱圧着させ、ボール状の
直上部にて極細線を切断し、チップ電極に対してバンプ
が形成・接続される。In this case, by using a wire bonding device, an extra fine wire of platinum (or platinum alloy) is inserted from the capillary, and the tip of the extra fine wire of platinum or platinum alloy drawn from the tip of the capillary is melted by electric discharge. , The ball-shaped ultrafine wire is thermocompression-bonded onto the chip electrode by the capillary, and the ultrafine wire is cut right above the ball-shape, and the bump is formed and connected to the chip electrode. .
【００２１】更に、プリント基板等の基板上に形成され
ている配線薄膜と接続され且つチップ電極に対向して形
成された電極部に対して、スクリーン印刷法によって半
田ペースト層を形成しする。半導体チップ上の白金バン
プと基板電極部と位置合わせして固定し、リフロー半田
付けによって両者の接続を行った。Further, a solder paste layer is formed by a screen printing method on an electrode portion connected to a wiring thin film formed on a substrate such as a printed circuit board and facing the chip electrode. The platinum bumps on the semiconductor chip and the substrate electrodes were aligned and fixed, and both were connected by reflow soldering.
【００２２】[0022]
【表１】 [Table 1]
【００２３】表１において、本実施例で使用した白金ワ
イヤの線径，成分及びボールの直径が示されている。接
合評価は、バンプ接合後の接合強度（シェア強度）が２
０ｇ以下のもの又は、チップにクラッチを生じたものを
不良（×印）とした。また半田接合後、信頼性の試験で
は、１２５℃で５０時間加熱の後、接合部の電気抵抗が
１０Ω以上上昇したものを不良（×）とした。なお、表
１において、Ｎｏ．１〜１０は、上述のワイヤボンディ
ング方式によるものであり、そのうちＮｏ．９及び１０
はこれに対する比較例を示している。また、この比較例
（Ｎｏ．１０）において、金ワイヤも使用した。Table 1 shows the wire diameter, components and ball diameter of the platinum wire used in this example. The bond evaluation shows that the bond strength (shear strength) after bump bonding is 2
Those having a weight of 0 g or less, or those having a clutch on the chip were regarded as defective (marked with x). In addition, in the reliability test after soldering, the one in which the electrical resistance of the joint portion increased by 10Ω or more after heating at 125 ° C. for 50 hours was determined to be defective (x). In Table 1, No. Nos. 1 to 10 are based on the wire bonding method described above. 9 and 10
Shows a comparative example for this. In addition, a gold wire was also used in this comparative example (No. 10).
【００２４】また、この実施例では、ボール配列方式で
もバンプ形成を行った（Ｎｏ．１１〜１４）。この場
合、直径２５μｍのを白金ワイヤを用いて、これを事前
に切断し、その切断片を２０００℃に加熱された炉中に
て落下溶解させることによりボールを形成した。そし
て、そのボールをチップ電極上に配列接合し、上記と同
様の評価を行った結果も示す。なお、Ｎｏ．１４は、こ
れに対する比較例を示している。Further, in this embodiment, bump formation was also performed by the ball array method (Nos. 11 to 14). In this case, a platinum wire having a diameter of 25 μm was cut in advance, and the cut piece was dropped and melted in a furnace heated to 2000 ° C. to form a ball. Then, the balls are arrayed and bonded on the chip electrode, and the same evaluation as above is performed. In addition, No. 14 shows a comparative example for this.
【００２５】次に、更に別の実施例においては、高温で
の信頼性試験を目的として、半導体チップのアルミニウ
ム電極膜（膜厚１μｍ）上にＴｉＷの合金膜（Ｔｉ１０
％，Ｗ９０％）を５００Åに形成し、これに白金バンプ
を接続した。この場合、白金バンプは、事前にボール状
に形成して熱圧着で接合したものと（試料）、ワイヤ
ボンディング装置と白金ワイヤ（径３０μｍ）を用いて
ボールバンプを形成したもの（試料）の両方を作成し
た。Next, in still another embodiment, for the purpose of reliability test at high temperature, a TiW alloy film (Ti10) is formed on the aluminum electrode film (film thickness 1 μm) of the semiconductor chip.
%, W90%) was formed to 500Å, and platinum bumps were connected thereto. In this case, the platinum bumps are both preliminarily formed into a ball shape and joined by thermocompression bonding (sample), and the ball bumps are formed using a wire bonding device and a platinum wire (diameter 30 μm) (sample). It was created.
【００２６】バンプの接合性を向上させるために、事前
にＴｉＷ膜上にＡｕ膜２０００Åを形成したものをチッ
プ電極として用いた。ボールはいずれも径７５μｍと
し、接合後の圧着径は平均で９０μｍであった。比較の
ために、Ａｌ上に直接白金ボールを接合したものも作成
した（試料）。そして基板と半田接続し、加熱試験を
行なった。In order to improve the bondability of the bumps, a TiW film on which an Au film 2000Å was previously formed was used as a chip electrode. Each ball had a diameter of 75 μm, and the pressure bonding diameter after joining was 90 μm on average. For comparison, a sample in which a platinum ball was directly bonded onto Al was also prepared (sample). Then, it was soldered to the substrate and a heating test was performed.
【００２７】この場合、半田の量は、ボールの体積とほ
ぼ同等とした。また、加熱試験温度は、２２０℃とし、
各試料とも１０Ω以上の電気抵抗の上昇が生じた時間
（限界時間）を調査した。この限界時間は、試料では
６５０時間であり、試料では７００時間、そして試料
では１５０時間であった。この結果、ＴｉＷ合金薄膜
の形成は、高温での長期信頼性に優れた特性を示すこと
が明らかとなった。In this case, the amount of solder was almost equal to the volume of the ball. The heating test temperature is 220 ° C.,
For each sample, the time (limit time) when the electrical resistance increased by 10Ω or more was investigated. This time limit was 650 hours for the sample, 700 hours for the sample, and 150 hours for the sample. As a result, it became clear that the formation of the TiW alloy thin film exhibits excellent long-term reliability at high temperatures.
【００２８】[0028]
【発明の効果】以上説明したように本発明によれば、バ
ンプにおける半田くわれを有効に防止することにより、
半田くわれの少ないバンプ接続構造を実現し、半導体の
実装において高い信頼性を保証することができる等の利
点を有している。As described above, according to the present invention, by effectively preventing the solder shaving in the bumps,
It has advantages such as realizing a bump connection structure with less soldering and ensuring high reliability in semiconductor mounting.
【図１】バンプ用金ワイヤを用いたフリップチップ法に
よる半導体チップの実装例を示す図である。FIG. 1 is a diagram showing an example of mounting a semiconductor chip by a flip chip method using a bump gold wire.
１０ 半導体チップ １１ アルミニウム電極 １２ 金ワイヤ １３ ボール １４ 金バンプ １５ 基板 １６ 電極部 10 semiconductor chip 11 aluminum electrode 12 gold wire 13 ball 14 gold bump 15 substrate 16 electrode part
Claims (6)
電極もしくはアルミニウム合金電極上に、純白金もしく
は白金合金から成るバンプが接続され、基板電極又はリ
ード電極に対して錫もしくは錫鉛合金の低融点金属を介
して、前記バンプを接続するようにしたことを特徴とす
る半導体装置。1. A bump made of pure platinum or a platinum alloy is connected to an aluminum electrode or an aluminum alloy electrode formed on a semiconductor chip, and a low melting point metal of tin or tin-lead alloy is applied to a substrate electrode or a lead electrode. A semiconductor device, characterized in that the bumps are connected to each other via the bumps.
ウム合金電極上に、チタン，ニッケル，チタン−タング
ステン合金，クロム及び銅の少なくとも１種から成り、
その膜厚が０．００１ミクロン以上、１ミクロン以下の
薄膜が形成され、この薄膜上に前記バンプが形成される
ことを特徴とする請求項１に記載の半導体装置。2. On the aluminum electrode or aluminum alloy electrode, at least one of titanium, nickel, titanium-tungsten alloy, chromium and copper is formed,
2. The semiconductor device according to claim 1, wherein a thin film having a thickness of 0.001 micron or more and 1 micron or less is formed, and the bump is formed on the thin film.
れるべき球形バンプであって、白金又は白金合金から成
り、直径が１０ミクロン以上、５００ミクロン以下であ
ることを特徴とする半導体装置用バンプ。3. A bump for a semiconductor device, which is a spherical bump to be connected to an electrode formed on a semiconductor chip, the bump being made of platinum or a platinum alloy and having a diameter of 10 microns or more and 500 microns or less. .
１０ミクロン以上、７０ミクロン以下であることを特徴
とするバンプ形成用の白金極細線。4. A platinum ultrafine wire for bump formation, wherein the purity of platinum is 95% or more and the wire diameter is 10 μm or more and 70 μm or less.
とも１種が、５重量％未満であり、その残部が白金から
成ることを特徴とする請求項に４記載の白金極細線。5. The platinum ultrafine wire according to claim 4, wherein at least one of gold, palladium, and indium is less than 5% by weight, and the balance is platinum.
ラリに白金又は白金合金の極細線を挿通し、 該キャピラリ先端から引き出した前記白金又は白金合金
の極細線の先端を、放電によって溶融することによりボ
ール状に形成し、 前記ボール状の前記極細線を、前記キャピラリによって
チップ電極上に熱圧着させ、 前記ボール状の直上部にて前記極細線を切断し、前記チ
ップ電極に対してバンプが形成・接続されるようにした
ことを特徴とする半導体装置の製造方法。6. An ultrafine wire of platinum or platinum alloy is inserted into a capillary of a wire bonding apparatus, and the tip of the platinum or platinum alloy ultrafine wire pulled out from the capillary tip is melted by electric discharge to form a ball shape. Then, the ball-shaped ultrafine wire is thermocompression-bonded onto the chip electrode by the capillary, and the ultrafine wire is cut right above the ball-shape to form and connect a bump to the chip electrode. A method of manufacturing a semiconductor device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30996794A JP3121734B2 (en) | 1994-11-18 | 1994-11-18 | Semiconductor device and metal ball for semiconductor device bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30996794A JP3121734B2 (en) | 1994-11-18 | 1994-11-18 | Semiconductor device and metal ball for semiconductor device bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08148496A true JPH08148496A (en) | 1996-06-07 |
| JP3121734B2 JP3121734B2 (en) | 2001-01-09 |
Family
ID=17999528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30996794A Expired - Fee Related JP3121734B2 (en) | 1994-11-18 | 1994-11-18 | Semiconductor device and metal ball for semiconductor device bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3121734B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7009299B2 (en) * | 1998-11-20 | 2006-03-07 | Agere Systems, Inc. | Kinetically controlled solder |
| WO2007001598A2 (en) * | 2005-06-27 | 2007-01-04 | Advanced Micro Devices, Inc. | Lead-free semiconductor package |
| US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
| US7901997B2 (en) | 2007-02-05 | 2011-03-08 | Shinko Electric Industries Co., Ltd. | Method of manufacturing semiconductor device |
-
1994
- 1994-11-18 JP JP30996794A patent/JP3121734B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7009299B2 (en) * | 1998-11-20 | 2006-03-07 | Agere Systems, Inc. | Kinetically controlled solder |
| US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
| WO2007001598A2 (en) * | 2005-06-27 | 2007-01-04 | Advanced Micro Devices, Inc. | Lead-free semiconductor package |
| WO2007001598A3 (en) * | 2005-06-27 | 2007-03-15 | Advanced Micro Devices Inc | Lead-free semiconductor package |
| US7215030B2 (en) | 2005-06-27 | 2007-05-08 | Advanced Micro Devices, Inc. | Lead-free semiconductor package |
| GB2442391A (en) * | 2005-06-27 | 2008-04-02 | Advanced Micro Devices Inc | Lead-free semiconductor package |
| GB2442391B (en) * | 2005-06-27 | 2010-12-08 | Advanced Micro Devices Inc | Lead-free semiconductor package |
| US7901997B2 (en) | 2007-02-05 | 2011-03-08 | Shinko Electric Industries Co., Ltd. | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3121734B2 (en) | 2001-01-09 |
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