JP3141115B2 - バーストｅｄｏメモリ装置アドレス・カウンタ - Google Patents

バーストｅｄｏメモリ装置アドレス・カウンタ

Info

Publication number
JP3141115B2
JP3141115B2 JP08520515A JP52051596A JP3141115B2 JP 3141115 B2 JP3141115 B2 JP 3141115B2 JP 08520515 A JP08520515 A JP 08520515A JP 52051596 A JP52051596 A JP 52051596A JP 3141115 B2 JP3141115 B2 JP 3141115B2
Authority
JP
Japan
Prior art keywords
address
burst
signal
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP08520515A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10512383A (ja
Inventor
オング、エイドリアン・イー
ザガー、ポール・エス
ウィリアムス、ブレット・エル
マニング、トロイ・エー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/370,761 external-priority patent/US5526320A/en
Priority claimed from US08/386,894 external-priority patent/US5610864A/en
Priority claimed from US08/457,651 external-priority patent/US5675549A/en
Priority claimed from US08/553,986 external-priority patent/US5682354A/en
Priority claimed from US08/553,156 external-priority patent/US5721859A/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of JPH10512383A publication Critical patent/JPH10512383A/ja
Application granted granted Critical
Publication of JP3141115B2 publication Critical patent/JP3141115B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G11C7/1024—Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP08520515A 1994-12-23 1995-12-21 バーストｅｄｏメモリ装置アドレス・カウンタ Expired - Fee Related JP3141115B2 (ja)

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
US08/370,761 US5526320A (en) 1994-12-23 1994-12-23 Burst EDO memory device
US08/370,761 1994-12-23
US08/386,894 1995-02-10
US08/386,894 US5610864A (en) 1994-12-23 1995-02-10 Burst EDO memory device with maximized write cycle timing
US08/457,651 US5675549A (en) 1994-12-23 1995-06-01 Burst EDO memory device address counter
US08/457,651 1995-06-01
US370,761 1995-06-30
US386,894 1995-06-30
US08/553,986 1995-11-06
US08/553,986 US5682354A (en) 1995-11-06 1995-11-06 CAS recognition in burst extended data out DRAM
US553,156 1995-11-07
US08/553,156 US5721859A (en) 1994-12-23 1995-11-07 Counter control circuit in a burst memory
US457,651 1995-11-07
US08/553,156 1995-11-07
US553,986 1995-11-07
PCT/US1995/016656 WO1996020479A1 (en) 1994-12-23 1995-12-21 Burst edo memory device address counter

Publications (2)

Publication Number Publication Date
JPH10512383A JPH10512383A (ja) 1998-11-24
JP3141115B2 true JP3141115B2 (ja) 2001-03-05

Family

ID=27541321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08520515A Expired - Fee Related JP3141115B2 (ja) 1994-12-23 1995-12-21 バーストｅｄｏメモリ装置アドレス・カウンタ

Country Status (3)

Country Link
JP (1) JP3141115B2 (ko)
KR (1) KR100284987B1 (ko)
WO (1) WO1996020479A1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3855002B2 (ja) * 1996-07-19 2006-12-06 エルピーダメモリ株式会社 カウンタ、同期化メモリ装置および半導体メモリ
US6320812B1 (en) 2000-09-20 2001-11-20 Agilent Technologies, Inc. Error catch RAM for memory tester has SDRAM memory sets configurable for size and speed
US7557796B2 (en) * 2004-12-22 2009-07-07 Delphi Technologies, Inc. Joystick sensor with two-dimensional image sensing

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0122099B1 (ko) * 1994-03-03 1997-11-26 김광호 라이트레이턴시제어기능을 가진 동기식 반도체메모리장치

Also Published As

Publication number Publication date
KR100284987B1 (ko) 2001-03-15
JPH10512383A (ja) 1998-11-24
WO1996020479A1 (en) 1996-07-04

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