JP3131854B2 - One-chip microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a one-chip microcomputer,
In particular to a so-called slave one-chip microcontroller which is controlled by the operating system of the main CPU.

[0002]

2. Description of the Related Art In a so-called slave type one-chip microcomputer, an ALU, a ROM, a RAM, a register, an interface with a main CPU, an import and an out port (hereinafter referred to as an I / O unit) are provided on one chip.
The main CPU controls the one-chip man-con with a command. In addition, this type of one-chip microcomputer uses I / O to improve its performance and application range.
Although the functions of the units are devised, the one-chip microcomputer controls the I / O unit and the like according to its own control program.

On the other hand, a control device for controlling the operation of various electronic devices in an operating system using a one-chip microcomputer has been developed. In this type of conventional control device, the one-chip microcomputer is a main CPU. Under the control of commands from
The operation state of the electronic device is detected and controlled.

[0004]

In the conventional slave type one-chip microcomputer, output control and input control of the I / O section of the one-chip microcomputer can be performed only by the one-chip microcomputer itself. In order to cause the main CPU to perform this control, it is necessary to exchange commands between the CPU and the one-chip microcomputer. For this reason, if the CPU controls the I / O unit of the conventional one-chip microcomputer,
(1) A major obstacle occurs in software design.
(2) It takes time for the CPU to access the I / O unit, and it is difficult to achieve a high-speed access. (3) The access to the I / O unit by the CPU requires a vacancy in the I / O unit of the one-chip microcomputer. However, another hardware is required, the device becomes large, and there is a problem in manufacturing cost. (4) If the one-chip microcomputer becomes abnormal, control of the I / O unit of the one-chip microcomputer becomes impossible. Occurs.

In the above-described conventional control device, when the one-chip microcomputer is in an abnormal state, the electronic device cannot be normally controlled, and the operating system is in an abnormal operation state.

[0006] The present invention has been made in view of the current situation of this kind of one-chip microcomputer as described above, the
An object of the present invention is to provide a one-chip microcomputer in which input / output access can be performed from both the one-chip microcomputer and the main CPU.

[0007]

To achieve SUMMARY OF for the] said object, the present invention includes a main CP operating system
In one-chip microcomputer which is controlled by the U, the
The control unit of the one-chip microcomputer and the one-chip microcomputer
An input / output unit for inputting / outputting data between the external device and the outside;
A first connection unit connecting the control unit and the input / output unit;
Second connection unit for connecting the input / output unit and the main CPU
Wherein the main CPU is the one-chip microcomputer
It is configured to be able to directly access the input / output unit inside .

[0008]

[0009]

According to such a configuration , in the one-chip microcomputer according to the present invention, the main CPU is a one-chip microcomputer.
Since the input / output unit in the inside can be directly accessed, the input / output access of the one-chip microcomputer is performed from both the one-chip microcomputer side and the main CPU side.

Also, an output indicating an abnormality from the main CPU is provided.
The output signal of the one-chip microcomputer is discussed based on the signal.
Operating system abnormalities
Can be eliminated.

[0011]

Embodiments of the present invention will be described below with reference to screens. First, a first embodiment of a one-chip microcomputer according to the present invention will be described with reference to FIGS. here,
FIG. 1 is a block diagram showing the basic configuration of the first embodiment, and FIG.
3 is a block diagram showing the internal configuration of the first embodiment and the configuration of a system incorporating the slave microcomputer according to the first embodiment. FIG. 3 is a timing chart showing the operation of the first embodiment.

In FIG. 1, reference numeral 5 denotes a one-chip microcomputer. The one-chip microcomputer 5 has a control bus 5a (first connection portion) for internal data signals, address signals and chip select signals. . The control bus 5a has an out port 12 (input / output unit) composed of a D flip-flop to which two clock signals are inputted, and an import 13 composed of a tri-state buffer group to which two series of enable signals are inputted. The (input / output unit) and the bus controller 6 (second connection unit) for performing a control operation are connected to each other so as to be able to exchange signals. The bus controller 6 is connected to a control bus 6a for external data signals, address signals, chip select signals, and read / write signals. As shown in FIG. 2, the one-chip microcomputer 5 is actually further provided with an ALU 10 (control unit) , a register 7, a ROM 8, and a RAM 9. Then, the one-chip microcomputer 5 having such a configuration is connected to the main CPU 1 for controlling the operation of the operating system via the control bus 6a, and the RO for storing the control program for the operation.
M2, a RAM 3 to which various data is written or read during the operation, and an I / O unit 4 used for a direct access operation of the main CPU 1 during the operation.
This I / O unit 4 is, depending on the one-chip microcomputer 5,
May be unnecessary.

Next, the operation of the first embodiment will be described with reference to the timing charts of FIGS. 1, 2 and 3. First, at the time of output to the out port 12 inside the one-chip microcomputer 5, the WRI signal is
When supplied to the out port 12 composed of a group of D flip-flops, data on the data bus of the control bus 5a is written to the D flip-flop of the out port 12 in synchronization with the rising edge of the WRI signal as shown in FIG. Output. When the main CPU 1 outputs data from the out port 12, the control bus 6a
When the WR signal is supplied from the bus controller 6 to the D flip-flop group of the out port 12 in response to a signal from the CPU 1 via the CPU 1, the data signal on the data bus of the control bus 6a is synchronized with the rising edge thereof. Is written to the D flip-flop group of the out port 12 via the data bus of the control bus 5a and output.

Further, at the time of input from the import 13 inside the one-chip microcomputer 5, when the RDI signal is supplied from the bus controller 6 to the tristate buffer group of the import 13, the input 13a to the import 13
Is output on the data bus of the control bus 5a. On the other hand, at the time of input from the import 13 by the main CPU 1, when an RD signal is supplied from the bus controller 6 to the tri-state buffer group of the import 13 in response to a signal from the CPU 1 via the control bus 6a, the import 13 The input 13a is output on the data bus of the control bus 6a via the data bus of the control bus 5a and the bus controller 6.

Next, a second embodiment of the one-chip microcomputer according to the present invention will be described with reference to FIGS. Here, FIG. 4 is a block diagram showing a basic configuration of the second embodiment, and FIG. 5 is a block diagram showing an internal configuration of a main part of the second embodiment.

In the first embodiment already described, two clock signals and two enable signals are input to the D flip-flop of the out port 12 of the one-chip microcomputer 5 and the tri-state buffer group of the import 13, respectively. However, in the second embodiment, as shown in FIG. 4, a configuration in which one system of clock signal and one enable signal are input to the D flip-flop of the out port 12 and the tri-state buffer of the import 13, respectively. It is. For this purpose, for example, as shown in FIG. 5, the bus controller 6 performs an AND operation between the signal FI inside the one-chip microcomputer 5 and the signal FO from the outside.
By the AND operation in the circuits 14 and 15, the WR signal and R
D signal is calculated. In the second embodiment, AND
Whether the processing is inside the chip microcomputer 5 or outside the chip microcomputer 5 is determined based on the logical values of the output signals of the circuits 14 and 15, and the same operation as in the first embodiment is performed.

As described above, according to the first and second embodiments of the one-chip microcomputer according to the present invention, the main CPU 1
The out port 12 and the import 13 of the one-chip microcomputer 5 can be directly accessed, so that it is not necessary to provide an I / O unit separately. The one-chip microcomputer has a main CPU 1
This enables input / output access at a high access speed.

Next, a first embodiment of a control device having a one-chip microcomputer according to the present invention will be described with reference to FIGS. Here, FIG. 6 is a block diagram showing the configuration of the first embodiment, FIG. 7 is a flowchart of the operation of the first embodiment, and FIG. 8 is a time chart of the operation of the first embodiment.

As shown in FIG. 6, in the first embodiment, the out port 12 of the one-chip microcomputer 5 is connected to the clock input terminal C of the watch dog timer 18,
The output terminal of the watchdog timer 18 is connected to the main CPU
1 and a one-chip microcomputer 5. Although not shown, an electronic device is connected to the one-chip microcomputer 5 controlled and operated by the main CPU 1 in the first embodiment, and the operation of the electronic device is controlled by the one-chip microcomputer 5. .

In the first embodiment, as shown in FIG. 7A, after starting during the program of the main CPU 1, in step S19, the logical value of the signal of the out port 12 of the one-chip microcomputer 5 is set to "H". "Is provided. Similarly, as shown in FIG. 5B, during the program of the one-chip microcomputer 5, the step S20 after the start is executed.
Thus, control is provided to set the logical value of the signal of the out port 12 to "L". These controls are set so that they do not overlap with each other as shown in FIGS.

With this configuration, the watchdog timer 18 can be used during normal operation in which the program does not run away.
A clock signal as shown in the timing chart of FIG. In this state, if the program of the main CPU 1 goes out of control, the signal in FIG. 9C is fixed at the logical value "L". If the program in the one-chip microcomputer 5 goes out of control, the signal in FIG. Fixed to “H”. Further, when the programs of the main CPU 1 and the one-chip microcomputer 5 both run out of control, the signal (c) is fixed to the logical value “H” from the time of the access of the one-chip microcomputer 5.
In this state, a watchdog signal is output from the watchdog timer 18, and the watchdog signal is input to the CPU 1 and the one-chip microcomputer 5 as a reset signal or an NMI signal (non-maskable interrupt signal). A return operation is performed to eliminate the program runaway of the operating system.

Next, a second embodiment of the control device provided with the one-chip microcomputer according to the present invention will be described with reference to FIGS. Here, FIG. 9 is a block diagram showing the configuration of the second embodiment, and FIGS. 10 to 12 are flowcharts showing the operation of the second embodiment.

The second embodiment is provided with a one-chip microcomputer according to the present invention and controls printing of a thermal head of a facsimile machine or a printer. A main CPU 1 for controlling the entire operating system includes a one-chip microcomputer. The chip microcomputer 5 is connected. A thermal head 21 for performing a printing operation is connected to an out port 12 of the one-chip microcomputer 5. A thermistor 24 of the thermal head 21 is connected to an import 13 of the one-chip microcomputer 5 via an AD converter 22. It is. In this case, the AD converter 22 is not provided separately, and FIG.
As shown by a dotted line, an A / D converter 23 is built in the one-chip microcomputer 5, and the output signal of the A / D converter 23 is
PU1 may be able to capture.

In the second embodiment, when the one-chip microcomputer 5 receives a print command from the main CPU 1,
A printing operation is performed by applying a strobe signal to the thermal head 21. At this time, the temperature information due to the change in the resistance value of the thermistor 24 is converted into a digital signal by the AD converter 22, and the input signal of the one-chip microcomputer 5 is imported. Is input to In addition to the temperature information, various parameters in the print command from the main CPU 1 and information on the cycle of the print command are input to the one-chip microcomputer 5 as information signals. Based on these information signals, the width of the strobe signal is controlled to keep the print density constant, and control is performed so that the temperature of the thermal head 21 does not exceed the allowable set value.

In this case, if any disturbance occurs and the program of the one-chip microcomputer 5 runs away, control of the strobe width is not performed correctly, and a strobe signal having a width exceeding the limit is applied, resulting in print quality. Decreases,
In some cases, the temperature of the thermal head 21 exceeded the allowable limit and the thermal head 21 was destroyed. However, in the second embodiment, as shown in FIG.
When U1 sends a print command to the one-chip microcomputer 5 in step S31, U1 waits for a predetermined time (time corresponding to the allowable width of the strobe signal of the thermal head) in step S32, and then turns off the strobe signal in step S33. Perform control. For this reason, even if the one-chip microcomputer 5 runs away, the strobe signal is turned off.
Destruction of the thermal head is prevented.

As shown in FIG. 11, in the second embodiment, when the main CPU 1 receives the temperature information of the thermal head 21 from the AD converter 22 via the import 13 in step S41, the main CPU 1 proceeds to step S42. It is determined whether the temperature of the thermal head 21 has reached a preset allowable value. Then, the determination in step S42 is Y
If it is ES, the main CPU 1 performs control to turn off the strobe signal in step S43, so that even if the one-chip microcomputer 5 runs away, the thermal head is prevented from being destroyed (the AD conversion unit 23 is Even in the case where it is built in the one-chip microcomputer 5, the main CPU 1 makes the data of the AD conversion unit 23 readable so as to perform the same control). Further, in the second embodiment, the main C
When a command is sent from the main CPU 1 to the one-chip microcomputer 5 when a command is exchanged between the PU 1 and the one-chip microcomputer 5, the one-chip microcomputer 5 always arranges to return a response to the command to the main CPU 1. . For this reason, as shown in FIG. 12, when a command is sent from the main CPU 1 in step S51, if it is determined in step S52 that there is no response from the one-chip microcomputer 5, the main CPU 1 proceeds to step S53. Since the control for turning off the strobe signal is performed, even if the one-chip microcomputer 5 runs away, the thermal head is prevented from being broken.

As described above, according to the first and second embodiments of the control device including the one-chip microcomputer according to the present invention, when an abnormality occurs in the operating system in which the main CPU 1 and the one-chip microcomputer 5 are incorporated, the One-chip microcomputer 5 based on the output signal of CPU 1
By changing the logical value of the output signal, the abnormality of the operating system can be recovered or the operation of the operating system can be stopped to eliminate the abnormality.

[0028]

As described above, according to the present invention, the main CPU is connected to the input / output unit in the one-chip microcomputer.
Because it is configured to allow direct access , input / output access of the one-chip microcomputer can be performed from both the one-chip microcomputer side and the main CPU side . As a result, there is no need to provide dedicated hardware and the freedom of device design An apparatus having a one-chip microcomputer which is increased in size, miniaturized, and operates at a high access speed is provided at a low manufacturing cost.

Also, according to the present invention, from the main CPU
Of the one-chip microcomputer based on the output signal
Since the logical value of the output signal is changed, it is possible to eliminate an abnormality in the operating system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a first embodiment of a one-chip microcomputer according to the present invention.

FIG. 2 is a block diagram showing the internal configuration of a first embodiment of a one-chip microcomputer according to the present invention and the configuration of a system in which the first embodiment is a slave microcomputer.

FIG. 3 is a timing chart showing the operation of the first embodiment of the one-chip microcomputer according to the present invention.

FIG. 4 is a block diagram showing a basic configuration of a second embodiment of the one-chip microcomputer according to the present invention.

FIG. 5 is a block diagram showing an internal configuration of a main part of a one-chip microcomputer according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a first embodiment of a control device including a one-chip microcomputer according to the present invention.

FIG. 7 is a flowchart showing the operation of the first embodiment of the control device including the one-chip microcomputer according to the present invention.

FIG. 8 is a timing chart showing the operation of the first embodiment of the control device including the one-chip microcomputer according to the present invention.

FIG. 9 is a block diagram showing a configuration of a second embodiment of the control device including the one-chip microcomputer according to the present invention.

FIG. 10 is a flowchart of a first operation of the second embodiment of the control device including the one-chip microcomputer according to the present invention.

FIG. 11 is a flowchart of a second operation of the second embodiment of the control device including the one-chip microcomputer according to the present invention.

FIG. 12 is a flowchart of a third operation of the second embodiment of the control device including the one-chip microcomputer according to the present invention.

[Explanation of symbols]

 1 Main CPU 2 ROM 3 ROM 4 I / O unit 5a Control bus 6 Bus controller 6a Control bus 7 Register 8 ROM 9 RAM 10 ALU 12 Out port 13 Import 18 Watchdog timer 21 Thermal head 22 A / D converter 23 A / D converter 24 Thermistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁷ , DB name) G06F 15/17 G06F 11/16 310 G06F 11/30 G06F 15/78 510

Claims (3)

(57) [Claims] 1. A main CP of an operating system
A one-chip microcomputer controlled by U controls input / output of data between the one-chip microcomputer control unit and the one-chip microcomputer and the outside.
Input / output unit, and a first connection unit connecting the control unit and the input / output unit
And a second connection for connecting the input / output unit and the main CPU.
A main unit connected to the one-chip microcomputer.
A one-chip microcomputer characterized by being configured to directly access the unit . 2. A printer is connected to the input / output unit, the one-chip microcomputer further has an AD converter, and an output signal of the AD converter is output to the main CPU.
One-chip microcomputer according to claim 1, characterized in that it is. 3. An output indicating an abnormality from the main CPU.
The output signal of the one-chip microcomputer is discussed based on the signal.
The one-chip microcomputer according to claim 1, wherein a logical value is changed .