JP3125863B2 - Print processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a print processing apparatus capable of performing print processing in page units.

[0002]

2. Description of the Related Art With the development of an electrophotographic page printer suitable for small-sized, high-speed digital printing, images, figures, characters, etc., which have escaped from conventional character information-centric printing, are handled in the same manner. 2. Description of the Related Art A print processing apparatus using a description language in which enlargement, rotation, deformation, and the like of an image can be freely controlled has been widely used. A typical example of such a description language is PostScript (Adobe System).
s), Interpress (trademark of Xerox), Acrobat (trademark of Adobe Systems), GDI (Graphics Device I)
Internet, trademark of Microsoft Corporation) and the like are known.

[0003] Print data created in a description language includes:
It consists of commands and data strings in which drawing commands and data representing images, figures, and characters at arbitrary positions in a page are arranged in an arbitrary order. First, the print data must be rasterized. Rasterization is the process of developing a raster scan line by developing it into a series of individual dots or pixels that traverse a page or portion of a page, and successively generating successive scan lines below the page. In a conventional page printer, print data of an entire page is rasterized before printing and stored in a page buffer memory. However, storing raster data for an entire page requires a large amount of memory. Particularly, in the latest electrophotographic color page printer, C (Cyan), M
(Magenta), Y (Yellow) , B K (Bl
ack) requires raster data corresponding to the four color toners, and image quality is required more than a black and white page printer. Need.

[0004] In response to the need for a large amount of memory, band memory technology has recently emerged as a technology for reducing memory requirements from the viewpoint of cost reduction. Band memory technology can rasterize print data created in a description language faster than rasterizing print data instead of rasterizing all print data for one page before printing by a page printer. Convert to relatively simple intermediate data,
This is a technique of dividing a page into a plurality of adjacent areas (bands), storing intermediate data corresponding to each band, sequentially transferring the intermediate data to a raster development processing unit, and developing the data in a buffer memory corresponding to the band. In the band memory technology, a memory for storing intermediate data is newly required, but it is possible to reduce a buffer memory which requires a large capacity for raster data. However, in a general band memory technique, it is necessary to finish developing raster data from intermediate data for the next band before printing of raster data of a certain band is completed. When the print data includes a complicated graphic drawing instruction or an image drawing instruction with a large data amount, or when a specific band in one page includes a complicated graphic drawing instruction or an image drawing instruction, There is a possibility that a situation may occur where the development of the intermediate data into the raster data cannot be completed in time.

Therefore, it has been considered to use dedicated hardware in order to speed up the process of developing intermediate data into raster data. As described above, objects to be drawn on a page include images, figures, and characters, and these require special processing according to the type of each object. For example, in the case of an image, resolution conversion, affine conversion, interpolation accompanying these processes, color processing, and the like are performed. In the case of a figure, coordinate conversion, vector / raster conversion,
Filling processing is required. In the case of characters, conversion of outline coordinates, hint processing, vector / raster conversion, filling processing, and the like are required. Therefore, it is necessary to prepare dedicated hardware corresponding to all of these processes one by one. However, in this case, even if the memory amount can be reduced, there is a problem that the amount of dedicated hardware to be added increases and the entire system becomes expensive. In addition, H /
W can be used only when the intermediate data is converted into a bitmap, and there is a problem that preparing dedicated hardware corresponding to the processing in parallel is very useless considering the usage rate. .

Conventionally, as an attempt to solve such a problem, instead of providing hardware for all functions in parallel, the functions are changed by reconfiguring the hardware programmability or structure, and the hardware is reduced. Attempts have been made to realize many functions at high speed. As prior arts relating to the present invention having such a concept, there are JP-A-6-131155 and JP-A-6-282432.

[0007]

Problems to be Solved by the Invention
The technique disclosed in Japanese Patent Application Laid-Open No. 5-105605 reconfigures the means for generating an address for the data storage area and reconfigures the operation means for the data in the data storage area obtained by the means for generating the address, thereby performing various image processing. The goal is to achieve this with less hardware. This configuration can reconstruct image processing that is significant in address information, but cannot cope with vector processing such as graphics and characters. Also, since image processing is always performed by performing reconstruction, there is also a problem that the reconstruction time increases when various images appear arbitrarily, such as in a page description language (PDL).
Furthermore, unless the rewriting process is a process of almost the same size, the rewriting unit is matched to the largest process, and there is a problem that reconfiguration of processes of various sizes causes waste.

Japanese Patent Application Laid-Open No. 6-282432 discloses a method of controlling a data flow by providing a plurality of arithmetic circuits capable of operating in parallel in a necessary number in advance. Such a method is suitable for an application in which a small number of arithmetic circuits are frequently used for some image processing.
When applied to a device in which various types of drawing elements such as images, figures, and characters coexist, a large number of types of arithmetic circuits are required, so that there is a problem that the hardware amount, which is the original purpose, cannot be reduced.

The present invention has been made in consideration of the above points, and rewrites the reconfiguration of hardware used for expansion processing in accordance with at least the contents of print data including images, figures, and characters. An object of the present invention is to enable high-speed and resource-saving print processing using the same hardware resources by efficiently performing both the number of times and the scale of rewriting.

[0010]

According to the present invention, in order to achieve the above-mentioned object, at least one of a character, a graphic, and an image drawing element, which is described by a predetermined drawing command, is described. the print data expanded into the second print data of the image output data structure, said to the print processing apparatus that performs image output based on the second print data, the input data of a plurality of logical blocks and the plurality of logical Glock and a switching means for controlling the flow of output data including a logic circuit device
In addition, at least one of the function of the logic circuit block and the switching mode of the switching unit can be set according to the configuration data, and the configuration data is changed according to the logic circuit configuration information to change the logic circuit configuration information. Corresponding argument
A logic circuit for developing the first print data to the second print data in physical circuit configuration, an input means for inputting the first print data, the input to the input means 1
Determining means for determining the overlap of the drawing elements included in the print data, and at least input to the input means based on the determination information of the determination means and the content of the first print data input to the input means. rearranged the drawing element of the first print data, first is further developed by the conversion means and said logic circuit and supplying the converted into print data of a predetermined format to said logic circuit device including the logic circuit configuration information And output means for outputting an image based on the print data. And the logic circuit device is the predetermined
Corresponding to the logic circuit configuration information contained in the print data
The print data of the predetermined format is stored in the second
To print data.

[0011] In this configuration, it is possible to logic circuitry is provided a configurable logic device flexible, with less hardware elements to implement the many functions required to deploy the drawing element. Further, it is possible to optimize the processing order of the rendering elements by analyzing the overlapping and the contents of the rendering elements, and to optimize the logic circuit configuration according to the rendering element to be processed, thereby improving the throughput.

In this configuration, the reordering of the drawing elements in the conversion means may be performed so that the drawing elements which can be developed in parallel by the logic circuit device are continuous.

The parallel development by the logic circuit device may be performed by a logic circuit configuration set to include a plurality of the same or different functional blocks.

[0014] The arrangement of the drawing elements in the conversion means may be performed so that the number of times of changing the configuration data of the logic circuit device is reduced.

[0015] The conversion means may not perform the rearrangement of the order between the drawing elements determined to be overlapped by the determination means.

The judging means may judge the overlap using a circumscribed rectangle including the drawing element.

Further, the conversion means may perform the order rearrangement after removing the overlap between the drawing elements determined to have the overlap by the determination means.

The rearrangement of the drawing elements may be performed for each page or for each band obtained by dividing the page into a plurality of scan lines.

In the above-mentioned logic circuit device , the logic circuit configuration may be changed in whole or in part.

Further, the logic circuit device is configured to omit the change of the configuration data when the logic circuit configuration information included in the print data of the predetermined format input one after another is the same. Is also good.

Further, the logic circuit device may include at least a field programmable gate array.

The logic circuit device may include a plurality of arithmetic processing units, and switching means for switching a flow of input data and output data of the plurality of arithmetic processing units.

The conversion means may include a plurality of logical blocks.
And a switching means for controlling the flow of input data and output data of the click and the plurality of logical blocks, the logical
A logic circuit capable of setting at least one of the function of the block and the switching mode of the switching means according to the configuration data.
A path device may be provided, and at least a part of the processing of the conversion means may be executed by the logic circuit device in the conversion means.

Further, the logic circuit device may be set so that a plurality of functional blocks are expanded by pipeline operation.

According to the present invention, in order to achieve the above-described object, the first print data described by a predetermined drawing command, which represents at least one of a character, a graphic, and an image drawing element, A plurality of logical blocks and a plurality of the plurality of logical blocks are expanded to a print processing device that develops the image data into second print data and outputs an image based on the second print data.
A including a logic circuit device and a switching means for controlling the flow of input data and output data of the logical block, can be set according to at least one of the configuration data of the switching aspects of the function and the switching means of said logic block
There, for developing the first print data to the second print data in the logic circuit configuration corresponding to the logic circuit configuration information and change the configuration data according to the logic circuit configuration information
A logic circuit device ; input means for inputting the first print data; determination means for determining an overlap of drawing elements included in the first print data input to the input means; and determination by at least the determination means Based on the information and the content of the first print data input to the input means, the first print data input to the input means is printed in a predetermined format including the logic circuit configuration information. the above logic times are converted into data
A conversion unit that supplies the image data to the path device and an output unit that outputs an image based on the second print data developed by the logic circuit device are provided. And the above logic circuit device
Is the logic circuit configuration included in the print data of the predetermined format.
The print data of the above-mentioned predetermined format is
Data to the second print data.

[0026] In this configuration, it is possible to logic circuitry is provided a configurable logic device flexible, with less hardware elements to implement the many functions required to deploy the drawing element. Furthermore, by analyzing the overlapping and the contents of the drawing elements, the logic circuit configuration can be optimized according to the drawing element to be processed, and the throughput can be improved.

[0027] In this configuration, the conversion means may include a logic circuit configuration for developing print data including a plurality of continuous drawing elements determined to be non-overlapping by the determination means in parallel with the plurality of drawing elements. Logic circuit to specify
You may make it convert into the format containing configuration information.

Further, the rendering of the drawing elements in parallel may be performed by a logic circuit configuration including a plurality of the same or different functional blocks.

According to the present invention, in order to achieve the above object, the first print data described by a predetermined drawing command, which represents at least one of a character, a graphic, and an image drawing element, A plurality of logical blocks and a plurality of the plurality of logical blocks are expanded to a print processing device that develops the image data into second print data and outputs an image based on the second print data.
A including a logic circuit device and a switching means for controlling the flow of input data and output data of the logical block, can be set according to at least one of the configuration data of the switching aspects of the function and the switching means of said logic block
There, for developing the first print data to the second print data in the logic circuit configuration corresponding to the logic circuit configuration information and change the configuration data according to the logic circuit configuration information
A logic circuit device , input means for inputting the first print data, and a logic circuit structure corresponding to the content of the first print data, the first print data input to the input means being converted to the first print data.
Said logic is converted into print data of a predetermined format including forming information
Conversion means for supplying the circuit device and output means for outputting an image based on the second print data developed by the logic circuit device are provided. And the above logic circuit
The apparatus includes a logic circuit structure included in the print data of the predetermined format.
Print data of the above-mentioned predetermined format with a logic circuit configuration corresponding to the
Data to the second print data. Also the above conversion
The means is a drawing element that can be developed in parallel by the above logic circuit device.
The drawing elements are rearranged so that the elements are continuous. There
The above conversion means makes the drawing elements of the same type
The above drawing elements are rearranged.

[0030] In this configuration, it is possible to logic circuitry is provided a configurable logic device flexible, with less hardware elements to implement the many functions required to deploy the drawing element. Further, the content of the drawing element is analyzed, and the logic circuit configuration is optimized according to the drawing element to be processed, thereby improving the throughput.

Further, in this arrangement, the conversion means, in response to the logic circuit configuration information may be omitted the logic circuit configuration information in the conversion data.

[0032]

Embodiments of the present invention will be described below. First Embodiment FIG. 1 is a block diagram illustrating a configuration of a first embodiment according to the present invention. 1, the image processing apparatus includes a print data creation unit 1, a print data input unit 2, a conversion processing unit 3, a development processing unit 4, and an output unit 5. Further, the conversion processing unit 3 includes a lexical analysis unit 30 and an intermediate data generation unit 3
1, intermediate data sequence control 32, and intermediate data storage unit 3
And 3. The expansion processing unit 4 includes a reconfigurable expansion unit 40, a reconfiguration control unit 41, and a configuration data management unit 42.

The print data creating section 1 has a function of creating print data described in a description language from document data generated by an application program for processing document creation and editing in a personal computer or a workstation. Things. The description language targeted in this embodiment is, for example, PDF (Portable Document Fo) represented by GDI and Acrobat.
rmat), Page Description Language such as PostScript (Page Description Language)
e).

The print data input unit 2 has a communication function for inputting the print data generated by the print data creation unit 1,
Alternatively, it has a function of temporarily storing print data until the print data is output to the conversion processing unit 3.

The conversion processing unit 3 converts print data input from the print data input unit 2 into intermediate data that can be expanded into print data in the expansion processing unit 4 and rearranges the intermediate data. The conversion processing unit 3 includes a lexical analysis unit 30, an intermediate data generation unit 31, an intermediate data order control unit 32,
And an intermediate data storage unit 33.

The lexical analysis unit 30 cuts out the print data input from the print data input unit 2 as a token according to the syntax of a predetermined description language, and outputs the token to the intermediate data generation unit 31.

The intermediate data generation unit 31 includes a lexical analysis unit 30
Receives and interprets the token output from the CPU, executes a rendering command, generates data in a trapezoidal basic unit for each rendering command, and sends the data to the intermediate data order control unit 32. The purpose of generating the intermediate data is to enable high-speed expansion processing in the expansion processing unit 4. Therefore, the intermediate data is represented by a set of simple figures (trapezoids). In addition, the expansion data ID is also added to the intermediate data as information regarding the expansion processing. The intermediate data order control unit 32 reads a certain amount of intermediate data output from the intermediate data generation unit 31, determines overlap between them, performs rearrangement based on the result, and stores the intermediate data. Output to the unit 33. At this time, for each group of intermediate data that can be processed in parallel based on the rearrangement, information indicating a boundary with another group and hardware that is an identifier for configuration data written to the reconfigurable expansion unit 40 of the expansion processing unit 4 A hardware configuration ID is added. The intermediate data storage unit 33 stores the transmitted intermediate data, and is read from the development processing unit 4 as needed.

The expansion processing section 4 reads the output intermediate data from the conversion processing section 3 in band units, and creates print data in a band buffer memory in the expansion processing section 4. This processing is alternately stored in two band buffer memories in the expansion processing unit 4. As will be described later, the output unit 5 used in this embodiment is a color page printer, and the print data alternately stored in the buffer memory corresponds to the print data of the recording color printed by the output unit 5. are doing. continue,
The print data stored in the band buffer memory is alternately output to the output unit 5 in response to a print data request from the output unit 5.

The output section 5 receives the print data output from the band buffer memory of the expansion processing section 4, prints it on recording paper, and outputs it. More specifically, C
This is a color page printer using a laser scanning type electrophotographic method capable of outputting a full-color image by repeating exposure, development, and transfer for each of MYB _K (cyan, magenta, yellow, and black) colors. The output unit 6 may be an ink jet type color printer.
In this case, print data is simultaneously output from the band buffer memory of the expansion processing unit 4 to the output unit 5 in four colors.

Here, the configuration and operation of a color page printer using a general laser scanning electrophotographic system will be described with reference to FIG. In FIG. 2, a video interface 50 inputs print data corresponding to CMYBK color information sequentially sent from the expansion processing unit 4 to a driver (not shown) for controlling the lighting of a semiconductor laser, and converts it into an optical signal. Semiconductor laser scanning device 51
Is composed of an infrared semiconductor laser, a lens 711, and a polygon mirror 510, and scans the photosensitive drum 72 as spot light of several tens μm. The photoconductor drum 52 is charged by the charger 53, and an electrostatic latent image is formed by an optical signal. The latent image is converted into a toner image by two-component magnetic brush development on a rotary developing device 54, and is transferred to a transfer drum 55.
The image is transferred onto the paper adsorbed on the upper side. Photoconductor drum 52
The excess toner is cleaned by the cleaner 56. This process is repeated in the order of BK, Y, M, and C, and multiple transfer is performed on paper. Finally, the sheet is peeled off by the transfer drum 55, and the toner is fixed by the fixing device 57. Note that 58
Is a paper transport path.

Next, the flow of print data in the print processing apparatus configured as described above will be summarized. The print data created by the print data creation unit 1 is input to the lexical analysis unit 30 of the conversion processing unit 3 via the print data input unit 2. The token cut out from the print data in the lexical analyzer 30 is input to the intermediate data generator 31. The intermediate data generator 31 interprets the token and generates intermediate data divided in band units. The intermediate data order control unit 32 rearranges the order of the intermediate data based on the overlap, divides the intermediate data into groups that can be processed in parallel, and stores one page in the intermediate data storage unit 33 in band units. At this time, the intermediate data includes data based on a trapezoid set, a band ID indicating which band belongs,
The type of image, character, graphic, etc., the attribute of drawing, the circumscribed rectangle for the trapezoid set, the group ID that can be processed in parallel, and the hardware configuration ID are added. Then, the intermediate data storage unit 33 sends out the intermediate data in response to a request from the development processing unit 4.

On the other hand, the expansion processing unit 4 inputs the configuration data from the configuration data management unit 42 as needed based on the hardware configuration ID added to the intermediate data input from the conversion processing unit 3 and The function of the reconfigurable developing unit 40 is rewritten under the control of the unit 41. Further, the expansion processing unit 4 receives the intermediate data and performs the expansion process until the band buffer memory is filled with the print data recorded first by the output unit 5. When the cycle of the output unit 5 is completed or the output preparation is completed, the print data is transferred from the band buffer memory to the output unit 5 line by line according to the recording speed of the output unit 5, and printing is performed. While the print data of one band buffer memory is being printed, the expansion processing is executed until one band buffer memory is filled with the print data. The expansion of the print data by the expansion processing unit 4 and the printing by the output unit 6 are repeated for each color or simultaneously for four colors until the print data for one page is processed. Further, when the print data includes a plurality of pages, the process is repeated until the output of all pages is completed.

The outline of the print processing apparatus of the present invention has been described above. Next, details of a main part of the print processing apparatus will be described.

First, details of the intermediate data generator 31, intermediate data order controller 32, and intermediate data storage 33 will be described.

As shown in FIG. 3, the intermediate data generation unit 31 includes a token interpretation unit 310, an instruction execution unit 311, an image processing unit 312, a drawing state storage unit 313, a vector data generation unit 314, a font Management section 315, matrix conversion section 316, short vector generation section 31
7, a trapezoid data generation unit 318, and a band decomposition management unit 3
And 19 parts.

The token interpretation unit 310
, And converts the token into an internal instruction and sends it to the instruction executing unit 311. The command execution unit 311 transfers the command to the image processing unit 312, the drawing state storage unit 313, and the vector data generation unit 314 according to the command sent from the token interpretation unit 310. The image processing unit 312 performs various types of image processing based on the input image header and image data to generate an output image header and output image data, and transfers the output image header and output image data to the trapezoid data management unit 320. The drawing state storage unit 313 includes:
Information necessary for drawing given by a command of the command execution unit 311 is stored. The vector data generation unit 314 generates vector data to be drawn using the instruction of the instruction execution unit 311 and the information added thereto, the information from the drawing state storage unit 313, and the information from the font management unit 315.
The data is transferred to the matrix conversion unit 316. The font management unit 315 manages and stores outline data of various fonts, and provides outline data of characters in response to a request. The matrix conversion unit 316 affine-transforms the vector data input from the vector data generation unit 314 using the conversion matrix of the drawing state storage unit 313,
Transfer to the short vector generation unit 317. The short vector generation unit 317 approximates the vector for the curve in the input vector with a set of a plurality of straight vectors (short vector), and sends it to the trapezoid data generation unit 318.
The trapezoid data generation unit 318 generates trapezoid data to be drawn from the input short vector, and
Transfer to 19. The band decomposition management unit 319 divides the trapezoidal data spanning a plurality of bands from the input trapezoidal data into trapezoidal data of each band, and further determines to which band the trapezoidal data divided in band units belongs. , A circumscribed rectangle for a trapezoidal data set divided in band units, data management information and color information input from the drawing state storage unit 313 or image data input from the image processing unit 312, and expansion processing An expansion process ID as information is added and sent to the intermediate data order control unit 32. The intermediate data order control unit 32 rearranges the order for each band based on the overlap of the intermediate data, divides the order into groups that can be processed in parallel, and adds a hardware configuration ID and a group ID. Intermediate data storage unit 3
Reference numeral 3 stores one page of intermediate data output by the intermediate data order control unit 32 in band units. The processes from the token interpreting unit 310 to the intermediate data generating unit 31 described above are repeatedly performed each time a drawing command is input. The processing from the intermediate data order control unit 32 to the intermediate data storage unit is performed in band units or page units as occasion demands. The transfer of the intermediate data from the intermediate data storage unit 33 to the expansion processing unit 4 is performed after the intermediate data for one page is stored.

In the following, while showing the actual data structure, the intermediate data generator 31, intermediate data order controller 3
2. The operation of each unit of the intermediate data storage unit 33 will be described in more detail.

The token interpreter 310 is used by the lexical analyzer 30
Interprets the token input from, converts it into an internal instruction and its arguments, and converts the set of these internal instructions and arguments into an instruction execution unit 31.
Transfer to 1. For example, the internal commands include a drawing command for executing drawing of a character / figure / image and a drawing state command for setting information required for drawing such as a color and a line attribute.

The instruction execution unit 311 includes the token interpretation unit 31
Execute the internal instruction sent from 0. The commands executed here mainly include a drawing command and a drawing state command. For example, the drawing commands include three types of drawing commands as shown in Table 1, and information necessary for each drawing is shown. Among them, information having an underline is given as an argument in a drawing command, and other information is stored in the drawing state storage unit 313 in advance by initial setting, a preceding command, or the like. For the execution of the drawing command, the received drawing command other than the image drawing is transferred to the vector data generation unit 314 as it is. In the case of image drawing, the received drawing command is transferred to the image processing unit 312, and the vertical and horizontal sizes of the image header are transferred to the vector data generating unit 314. For the drawing state command, the command is stored in the drawing state storage unit 31.
Transfer to 3.

The image processing unit 312 receives the input image header and the input image data, which are the arguments of the command input from the command execution unit 311. Is subjected to affine transformation using the transformation matrix acquired from the drawing state storage unit 313. Further, in some cases, the processed image is compressed, an output image header and output image data are generated, and transferred to the band decomposition management unit 319. For this compression, it is usual to use a compression method which originally compressed image data on the PDL side, but this need not be the case. For example, if the data is compressed by DCT (Discrete Cosine Transform) on the PDL side,
It may be compressed by DCT or LZW (Lempe
Compression may be performed by the l-Ziv & Welch) method, or may not be performed. In the affine transformation to be performed, the affine transformation may be intentionally performed for a resolution smaller than the resolution of the output device in order to reduce the memory amount of the intermediate data buffer.

The drawing state storage unit 313 stores the instruction execution unit 31
For example, the value of the information without the underline shown in Table 1 is set with the value of the argument included in the instruction received from No. 1 and stored. The image processing unit 31
2. In accordance with requests from the vector data generation unit 314, the matrix conversion unit 316, the short vector generation unit 317, the band decomposition management unit 320, and the like, these values are transferred.

[0052]

[Table 1] The vector data generation unit 314 uses the command and argument sent from the command execution unit 311 and the value of the drawing state storage unit 313 to generate vector data for new drawing except for the solid drawing. First, the case of character drawing will be described. The character code given by the argument and the font ID obtained from the drawing state storage unit are transferred to the font management unit to obtain character outline data. Since the acquired outline data does not include information on the drawing origin (current point), the drawing state storage unit 3
The target vector data is generated by adding the offset of the current point acquired from 13 to the outline data. In the case of image drawing, a rectangular vector corresponding to the image header given by the argument is generated from the vertical and horizontal sizes of the image header, and the offset of the current point obtained from the drawing state storage unit 313 is added to obtain the target vector data. Generate. In the case of stroke drawing, an outline vector of a line having a thickness as shown in FIG. 4 is generated from the vector given as an argument and various line attributes acquired from the drawing state storage unit 313. The vector generated in this manner (in the case of a solid drawing, the instruction execution unit 3
11) is transferred to the matrix conversion unit 316.

The font management unit 315 stores outline vector data for various fonts, and provides outline vector data for the character in accordance with a given character code and font ID.

The matrix conversion unit 316 affine-transforms the vector data received from the vector data generation unit 314 using the conversion matrix obtained from the drawing state storage unit 313. The main purpose of the affine transformation is to convert the resolution (coordinate system) of the application to the resolution (coordinate system) of the printer. A 3 × 3 matrix as shown in the following equation (1) is used for the conversion matrix. The input vector data (Xn, Yn) is converted into output vector data (Xn ′, Yn ′), Sent.

[0055]

(Equation 1) The short vector generation unit 317 converts a curve vector, when there is a curve vector, into a plurality of input vectors so that an error is smaller than a flatness value obtained from the drawing state storage unit 313. The approximation process is performed using the short vector. For example, a Bezier curve represented by four control points shown in FIG. 5 is used as a curve vector. In this case, the short vector processing recursively divides the Bezier curve as shown in FIG. 5, and ends the division when the height (distance d) becomes smaller than the value given by flatness. Then, by connecting the start point and the end point of each of the divided Bezier curves in order, the short vectorization is completed. The generated short vector is sent to the trapezoid data generation unit 318.

The trapezoid data generation unit 318 generates a set of trapezoid data (in some cases, a triangle, but the data structure is the same as the trapezoid) indicating the drawing area from the input vector data. For example, a polygonal vector indicated by a thick line shown in FIG. 6A has a drawing area indicated by four trapezoids. Note that this trapezoid is a trapezoid having two sides parallel to the scan line of the output device, and one trapezoid is represented by (sx, sy, x0, x1, x2, h) as shown in FIG. It is represented by two data. The generated trapezoid is sent to the band decomposition management unit 319.

The band decomposition management section 319 divides trapezoidal data over a plurality of bands from the input trapezoidal data into trapezoidal data for each band. For example, in FIG. 7, four trapezoidal data are divided into six trapezoidal data by the band decomposition unit. Further, additional information is added to the trapezoid data decomposed for each band to generate intermediate data. Additional information is
Management information for managing the intermediate data;
Are the development process IDs representing the contents to be processed in, and color information indicating in what color the trapezoidal data is to be painted. The management information for the character / graphic drawing command is a band ID for indicating to which band the object belongs, an object ID, the type of the object, data of the number of trapezoids, and a circumscribed rectangle for the trapezoid data set. The object ID is an identification number assigned to one rendering command, and the type of the object is identification data for an object to be rendered such as a character / graphic / image. The development processing ID is an ID indicating the processing in the development processing unit 4, and the color information is, for example, CMY.
The value of B _K is These pieces of additional information are added before the trapezoidal data for each band generated by the drawing command, as shown in FIG. Thus, the object is
It consists of a plurality of trapezoidal data to which a set of drawing attributes is attached. The intermediate data is a set of data for such an object. The management information for the image drawing command is the same as the character / graphic, but the color information is the image header and image data. Further, as shown in FIG. 8B, one image header and one image data are added to each of the trapezoidal data for each band generated by the drawing command. The image header and the image data are stored in the image processing unit 312.
However, the image data added as the intermediate data may be image data corresponding to a minimum rectangle of a vector indicating a converted image as shown in FIG. It may be data. Further, since the image data has a large capacity, it may be stored in a compressed form. The image header includes the type of the color conversion process and the type of the compression method, in addition to the parameter indicating the size of the image. Finally, the expansion processing ID will be described. The expansion processing ID is code information corresponding to the processing executed by the expansion processing unit 4, and has a meaning as shown in Table 2. These are stored in the intermediate data sequence control unit 32 according to the actual configuration of the reconfigurable expansion unit 40 and 1 according to the scale of the reconfigurable hardware and the processing contents executed in parallel.
It is converted to a configuration ID corresponding to one-to-one.

[0058]

[Table 2] The intermediate data order control unit 32 inputs the intermediate data output from the intermediate data generation unit 31 by a certain unit, performs overlap determination between them, performs rearrangement based on the result, and performs intermediate data storage. 33. At that time, for each set of intermediate data objects that can be processed in parallel based on rearrangement, information indicating a boundary with another set,
A hardware configuration ID that is an identifier for configuration data written to the reconfigurable expansion unit 40 of the expansion processing unit 4 is added. FIG. 10 shows an output data format in the intermediate data order control unit 32. In FIG. 10, the data structure of the intermediate data output from the intermediate data order control unit 32 is organized for each object that can be processed in parallel. The data of each set includes a band ID, a hardware configuration ID, the number of objects, and data of objects belonging to the set.

FIG. 11 shows the configuration of the intermediate data order control unit 32. In FIG. 11, reference numeral 321 denotes an object buffer; 322, a drawing order dependency detection unit; 323, an optimization table creation unit; 324, a configuration data selection unit; and 325, a reorder unit. The intermediate data order control unit 32 is a block that detects the drawing order dependency of a plurality of input objects, divides the objects into a group that can be expanded in parallel, and orders the expansion processing among them. . The rendering order dependency of objects means the order in which the lexical interpretation unit 30 interprets print data input and the intermediate data generation unit 31 generates a rendering object when objects overlap, that is, the object ID assigned to the intermediate data. In this order, it must be drawn from the back to the top. In this way, a model that overwrites a later interpreted object on a previously interpreted object is called opaque.
Call it a model. For example, in FIG. 12, 900 is a page area, and 901, 902, 903, and 904 are individual drawing objects. The objects 901 and 902 overlap, and the latter must be drawn in front of the former. This is because the object 901 is interpreted temporally earlier than the object 902. On the other hand, the object 903 overlaps with the object 904, and for the same reason, the latter must be drawn in front of the former.

The object buffer 321 receives and stores a plurality of object data. The unit in which the object data is input and stored may be a plurality of drawing objects, or may be a larger unit such as a band or a page. The drawing order dependency detection unit 322 inputs the ID of each object having the same band ID stored in the object buffer 321 and the coordinate value of the circumscribed rectangle, and detects the drawing order dependency between the objects. This process will be described in detail with reference to FIG. In FIG. 12, 901 and 904 are graphic objects, and 902 and 903 are image objects. Object 902 overlaps object 901 and object 904 overlaps object 903. Grouping is performed by checking whether the area represented by the circumscribed rectangle attached to each object overlaps. The method of checking the overlap is performed for any combination of two objects, with the overlap detection of the circumscribed rectangle of the two objects as the minimum unit. The detection of the overlap of the circumscribed rectangles of the two objects is performed as follows. Whether each of the coordinate points (P1, P2, P3, P4) representing the circumscribed rectangular area of one object is inside or on the boundary of the circumscribed rectangular area P5-P6-P7-P8 of another object Find out. If at least one point among P1, P2, P3 and P4 is inside or on the boundary of the rectangular area P5-P6-P7-P8, the two objects have an overlap, otherwise the two objects have No overlap. Therefore, in the case of FIG. 12, (901, 9
02) and (903, 904). This is the drawing of the object 901 and the drawing of the object 9
02 must be performed prior to drawing
This indicates that drawing of the object 903 must be performed prior to drawing of the object 904. Also, the group (901, 902) and the group (9
03,904) indicates that the data can be expanded in parallel. The drawing order dependency detection unit 322 outputs the ID of each object with a group ID and a number indicating the drawing order. In the case of FIG. 12, the data (901, 1,
1), (902, 1, 2), (903, 2, 1), (9
04, 2, 2) is output. Here, numbers consisting of three sets of data represent an object ID, a group ID, and a drawing order, respectively. Depending on the case, the size of the object buffer may be a unit of a plurality of objects belonging to a certain band, or may be the entire band buffer or the entire page. The grouping and selection of objects that can be processed in parallel are performed in band units or page units.

The optimization table creation unit 323 creates a table as shown in FIG. 13 based on the object ID, group ID, and drawing order input from the drawing order dependency detection unit 322, and 324. In FIG. 13, the group ID is a group ID grouped by the drawing order dependent detection unit. In the column of object ID, the ID of the object to be drawn first in each group, that is, the object whose input drawing order is 1, is written. Expansion processing I
In the field of D, the expansion processing ID corresponding to each object is input from the object buffer 321 and written. In the case of the example of FIG. 13, the processing ID for the object 901
Is Code A, and the processing ID for the object 903 is Code G. In the box for circumscribed rectangle area,
The coordinates of the circumscribed rectangle corresponding to each object are input from the object buffer 321 and the area is calculated and written.

The configuration data selection section 324 selects the configuration of the reconfigurable expansion section 40 that is most suitable for a plurality of parallel-processable objects output from the optimization table creation section 323. The configuration data selection unit 324 selects the configuration data of the reconfigurable expansion unit 40 according to the flowchart shown in FIG. 14 using the table output by the optimization table creation unit 323. The processing executed by the configuration data selection unit 324 includes four steps from S1 to S4. In S1, a development process ID of a plurality of objects to be processed in parallel from the input table is input. next,
In S2, a candidate for a parallel combination of expansion processing hardware that is allowed in the entire reconfigurable hardware resources is selected. This is performed by selecting a combination that satisfies the following equation based on the scale of the processing circuit obtained from the expansion processing ID of the object processed in parallel.

[0063]

SIZE ≧ XN × SIZE (X) + YN × SIZE (Y) +. . . + ZN × SIZE (Z) where SIZE is the size of the entire reconfigurable hardware circuit in the reconfigurable expansion unit 40, SIZE (X), SIZE
(Y) and SIZE (Z) are the circuit scales of the circuits X, Y and Z corresponding to the respective development processing IDs, and XN, YX and ZN are the circuits X and
This is the degree of parallelism between Y and Z. As represented by this formula, the configuration data selection unit 324 selects a configuration data of a circuit configuration having a plurality of identical functions or a configuration of a circuit configuration having a plurality of different functions and performs a parallel processing. Is provided. In addition, a mechanism is provided for selecting a circuit configuration having a plurality of different functions and performing a pipeline-like operation of exchanging input / output data in a pipeline between them. For example, a candidate having a configuration as shown in FIG. 15 is selected corresponding to the table of FIG. In FIG. 15, a candidate whose hardware configuration ID is X has a degree of parallelism of 3 as a hardware resource for the object 901 and a degree of parallelism of 2 as a hardware resource for the object 903. The candidate whose hardware configuration ID is Y has a parallelism of 4 as a hardware resource for the object 901 and a parallelism of 1 as a hardware resource for the object 903. Next, in S3, the development end time for each hardware configuration candidate calculated from the data amount of each object is calculated. Here, the expansion end time is a time until all the expansion processing of the objects that can be processed in parallel is completed. The expansion processing time To for each object is

[0064]

Calculated by To = DSIZE × TdｄPAR. Here, DSIZE is the data amount of the object to be processed, Td is the time required for one processing circuit to process the unit data amount, and PAR is the degree of parallelism.
FIG. 1 shows an approximate value of the data amount of the object to be processed.
The area of the circumscribed rectangle of the table No. 3 is used. In the example of FIG. 15, the processing time is 20 ms for the candidate whose hardware configuration ID is X, and is 30 ms for the candidate whose hardware configuration ID is X. In S4, the candidate with the shortest deployment time is selected as the final hardware configuration. In the example of FIG. 15, the hardware configuration ID
Is selected as the final configuration.

The reorder unit 325 converts the data of the object to be processed in parallel with the finally selected hardware configuration ID into the data structure described in FIG. 10 and outputs it to the intermediate data storage unit 33. For the object data, the object ID is output to the object buffer 321, and the data for the object is input from the object buffer 321.

Objects not selected by the configuration data selection unit 324 as objects that can be processed in parallel remain in the object buffer 321 as they are.
The processing described above is repeated for the combination of objects in the new object buffer 321 and the data structure of the intermediate data shown in FIG. 10 is output.

The data output by the intermediate data order control unit 32 is sent to the intermediate data storage unit 33, where the band ID is interpreted by the intermediate data storage unit 33, and is stored collectively for each band. When the lexical analysis unit 30 interprets the page output command, the EOP (End Of Page) is sent to the intermediate data storage unit 33 via the intermediate data generation unit 31 and the intermediate data order control unit 32, and the intermediate data storage The final data of each band stored in the unit 33 has EOD
Data representing (End Of Data) is added,
Clarify the end of band data. This EOP is also sent to the expansion processing unit 4, and the processing of the expansion processing unit 4 is started.

Next, the expansion processing section 4 will be described in detail. FIG. 16 shows a block diagram of the reconfigurable developing unit 40. The intermediate data for each band generated by the conversion processing unit 3 is read by the intermediate data transfer control unit 43 and written to the input buffer A420 or the input buffer B421 of the memory unit 410. Reconfigurable hardware unit 46
Is the input buffer A 420 or the input buffer B 42
The intermediate data is read from No. 1, expanded and drawn on the band buffer A422 or the band buffer B423. The print data transfer control unit 44 reads the print data developed from the drawn band buffer A422 or B423, converts the read data into serial data for each read word, and synchronizes the output data with the serial output clock signal. Output to Refresh control unit 44
Controls refresh of the memory unit 42 including the input buffer A420, the input buffer B421, the band buffer A422, the band buffer B423, and the work area 424. The arbitration unit 45 includes a refresh control unit 47, an intermediate data transfer control unit 43, a print data transfer control unit 44, a reconfiguration hardware unit 46, and a reconfiguration control unit 41, each of which accesses the memory unit 410.
Arbitration control is performed according to the access priority assigned to each block.

A method of using the input buffer and the band buffer will be described. FIGS. 17A and 17B show the use states of the buffers while intermediate data is being input to the input buffer A and the input buffer B, respectively.
In FIG. 17A, intermediate data corresponding to band i is being input to input buffer A, and intermediate data corresponding to band (i-1) has already been input to input buffer B. The reconfiguration hardware unit 46 has an input buffer B
Is read out, expanded, and drawn in the band buffer B. The band buffer A stores print data as a result of developing and rendering intermediate data corresponding to the band (i-2), and the print data transfer control unit 44 reads this to the output unit 5. FIG.
In FIG. 7 (b), intermediate data corresponding to band (i + 1) is being input to input buffer B, and intermediate data corresponding to band i has already been input to input buffer A. The reconfiguration hardware unit 46 reads the intermediate data stored in the input buffer A, develops the intermediate data, and draws the intermediate data in the band buffer A. The band buffer B stores print data as a result of developing and rendering the intermediate data corresponding to the band (i-1), and the print data transfer control unit 44 reads this to the output unit 5.

The work area 424 is used as a temporary work area as needed when the expansion processing section 4 expands the intermediate data input from the conversion processing section 3.

The procedure in which the reconfigurable expanding section 40 expands the intermediate data output by the conversion processing section 3 shown in FIG. 10 will be described. The configuration control unit 41 inputs the hardware configuration ID and the object ID from the input buffer, and controls the reconfiguration hardware unit 46 according to the flowchart shown in FIG. The processing performed by the configuration control unit 41 is from S11 to S
It consists of seventeen steps. First, in S11, the hardware configuration ID of the object to be processed next
Enter In S12, it is checked whether the configuration ID to be processed next is the same as the configuration ID just processed. If they are the same, the process jumps to S15 because there is no need to newly write the configuration data to the reconfiguration hardware unit 46. If not, the configuration data is read from the configuration data management unit 42 based on the hardware configuration ID in S13, and
Is written to the reconfiguration hardware unit 46. In S15, the object ID to be processed is output to the reconfiguration hardware unit 46, and a start signal is sent to notify the start of the processing. In S16, the process waits until the processing in the reconfiguration hardware unit 46 ends. In S17, it is checked whether or not there is an object to be further processed in the band currently being processed. if there is,
The process returns to S1 and ends if not.

FIG. 19 shows the configuration of the configuration data management unit 42. The conversion table 415 is a table for inputting a hardware configuration ID and outputting a start address and a data length of the configuration code storage area 411. The configuration code storage area 411 is an area in which configuration data for an actual hardware configuration ID is stored, and each entry has a variable length. A control unit 412 includes a read control unit 413 and an addition / update unit 414. The read control unit 413 inputs the read signal and the hardware configuration ID from the reconfiguration control unit 41, and stores the hardware configuration ID in the conversion table 415.
, The address and data length of the configuration data on the configuration code storage area 411 are input. Next, the read control unit 413 outputs the input address to the configuration code storage area 411, and stores the configuration data corresponding to the hardware configuration ID for the data length in the configuration code storage area 41.
1 and output to the reconstruction control unit 41. An adding / updating unit 414 is a control unit for adding / updating configuration data sent via a host computer (not shown) or the like. Remove, delete, or update. In the configuration code storage area 411,
Configuration data corresponding to various circuit configurations that process a single function, configuration data corresponding to a parallel circuit configuration with multiple identical functions, and configuration data corresponding to a parallel circuit configuration with multiple different functions And configuration data corresponding to a pipeline-like circuit configuration having a plurality of different functions.

Next, a specific configuration and processing contents of the reconfiguration hardware unit 46 will be described with reference to an example. The reconfiguration hardware unit 46 is a processing block that can change its function by writing configuration data managed and stored by the configuration data management unit 42 under the control of the reconfiguration control unit 41. Typically, the reconfiguration hardware unit 46
Field Programmable Gate Array (FPG)
A). For example, US X
ILINX FPGAs or equivalent components can be employed.

FIG. 20 shows reconfiguration hardware 46 configured using an FPGA. 20, the reconfiguration hardware 46 includes a control unit 461 and an FPGA unit 46.
2 and a register group 463. The register group 463 stores the configuration data sent from the configuration data management unit 42. FPGA unit 46
The function of No. 2 is determined by the configuration data held in the register group 462. The control unit 461 controls the register group 4
It controls input / output of data of 63, operation timing of the FPGA unit 462, and the like.

As shown in FIG. 21, the FPGA unit 462 includes a plurality of logic blocks 4621, a plurality of cross point switches 4622, and a plurality of switch matrices 4623. Logic block 4621
Is a lookup table 4621 as shown in FIG.
A, selector 4621B and flip-flop 462
1C. Look-up table 462
1A is mounted with a desired truth table. Truth table of this lookup table 4621A and selector 462
The 1B switching input signal is determined by a value held in the register group 463, that is, a part of the configuration data. Also, the cross point switch 4622 and the switch matrix 4623 can be configured as shown in FIGS. 23 and 24, respectively.

The functional block diagram showing the function of the reconfiguration hardware unit 46 is variable depending on the configuration data to be written. Therefore, in FIG. The configuration and operation of the reconfiguration hardware unit 46 will be described. At this time, the reconfiguration hardware unit 46 has a configuration as shown in FIG. In FIG. 25, reference numerals 460, 460-1 and 460-2 denote processing circuits 470, 4
70-1, 470-2, and 470-3 have the expansion processing ID of C
a processing circuit corresponding to the mode G. Processing circuit 460
Has a trapezoidal drawing circuit 461 and a screen processing circuit 462. The internal configuration of the processing circuit 470 includes an image expansion circuit 471, a resolution conversion circuit 472, and a color conversion circuit 4
73, trapezoidal drawing circuit 474, screen processing circuit 475
Consists of Processing circuit 460-1, processing circuit 460-2,
Processing circuit 480-1, processing circuit 480-2, processing circuit 4
Like the circuit configuration 80-3, the reconfigurable hardware unit 46 can perform parallel processing using a circuit configuration having a plurality of identical functions or a circuit configuration having a plurality of different functions. Further, like the internal configuration of the processing circuit 480, a pipeline-like operation of exchanging input / output data between a plurality of different functional functions in a pipeline manner is also possible. A more detailed configuration and operation of the processing circuit 460 whose expansion processing ID corresponds to Code A and the processing circuit 470 whose expansion processing ID corresponds to Code G will be described.

(I) Processing Circuit with Expansion Process ID Corresponding to Code A The processing circuit 460 processes the intermediate data for the graphic generated by the conversion processing unit 3. The trapezoidal drawing circuit 461 generates trapezoidal data (sx, sy, x
0, x1, x2, h) is converted into a data format consisting of four points as shown in FIG. 26 to draw a trapezoidal area. FIG. 27 shows a functional block diagram of the trapezoidal drawing circuit 461.
The intermediate data input unit 463 reads data of each trapezoid from the input buffer, and stores the data in the coordinate calculation unit A464.
And the trapezoid data is output to the coordinate calculation unit B465. The coordinate calculation unit A464 is in charge of calculating the coordinates of the left edge of the trapezoid (the edges P0 and P1 in FIG. 26), and outputs the coordinate values on the edges in order from P0 to P1. The coordinate calculator B465 calculates the right edge of the trapezoid (edge P2 in FIG. 26).
It is in charge of the coordinate calculation of P3) and outputs the coordinate values on the edge in order from P2 to P3. Edge drawing unit 466
Draws a straight line parallel to the trapezoidal x-axis based on the coordinate values input from the coordinate calculation unit A464 and the coordinate calculation unit B465.

FIG. 28 shows a functional block diagram of the coordinate calculator. Input trapezoidal data (sx, sy, x0, x
1, x2, h) are converted into four-point trapezoidal data (P0, P1, P2, P3) by a DDA parameter calculation unit 467, and DDA parameters such as an initial value of a slope and a residual are calculated. Output to the unit 468. DDA processing unit 4
Reference numeral 68 performs DDA processing based on the input parameters, and outputs a moving direction and a moving amount with respect to the last obtained point. The coordinate updating unit 469 updates the currently held coordinate values based on the input movement direction and movement amount and outputs the updated coordinate values. The initial values of the coordinates are set by the intermediate data input unit 463.

FIG. 29 is a block diagram of the edge drawing section 466. The edge drawing unit 466 inputs the coordinate values A / B and color information and paints the trapezoidal internal area. The address calculator 470 receives the coordinate values A / B and calculates the address of the edge component to be drawn. Mask operation unit 471
Inputs a coordinate value A / B and outputs a mask representing valid bits in a word to be drawn. Data operation unit 4
Reference numeral 72 denotes input of color data representing a fixed color, develops this value into words, outputs the word to a screen processing circuit, and outputs the result of the screen processing to the RmodW unit 473.
The RmodW unit 473 receives the input address, mask,
Drawing is performed by performing the following processing using the data. First, the band buffer is read according to the address. Assuming that the read data is Source, the mask data is Mask, and the drawing data is Data, (Mask * Data + Mask # * Source)
Calculate the value of e) and write it back to the same address. However,
* Represents logical product, + represents logical sum, and # represents logical negation. This process is repeated for each word including the edge to be drawn. Also, the screen processing circuit 462 includes:
This is a process for performing final gamma correction and halftone, and a screen pattern optimized for outputting a graphic is set. When the development processing ID is Code B, the screen processing is processing for performing final gamma correction and halftone, and a screen pattern optimized for outputting characters is set.

(Ii) Processing Circuit whose Expansion Process ID Corresponds to Code G The processing circuit 480 inputs an image in which intermediate data is different in color for each pixel, and performs various image processing as shown in Code G in Table 2. Do. Image processing is a combination of processing,
A processing circuit in the case of (expansion processing, resolution conversion, color space conversion, trapezoid processing, screen) will be described.

(Expansion Processing Circuit 481) The image, which is the input intermediate data, is compressed,
When decompression processing is required, the decompression processing circuit 481 decompresses the intermediate data using an algorithm such as JPEG. FIG. 30 shows a functional block diagram of the decompression processing circuit 481. The intermediate data input unit 481-1 inputs intermediate data that is compressed image data from the input buffer currently being input. The Huffman decoding unit 481-2 decodes the compressed data based on a built-in Huffman decoding table. The inverse quantization unit 481-3 outputs the Huffman decoding unit 4
The data input from 81-2 is inversely quantized based on a built-in quantization table and output. Inverse DCT
The unit 481-4 transforms the data input from the inverse quantization unit 481-3 by an inverse DCT transform and outputs the data.
The writing unit 481-5 writes the image data decoded by the inverse DCT unit to the work area 424.

(Resolution Conversion Circuit 482) FIG. 31 shows a functional block diagram of the resolution conversion circuit 482. The pixel data input unit 482-1 reads pixel data from the work area 424 in which the result of the decompression processing is written. Pixel reading is performed by reading only input pixels necessary for interpolation of the pixel currently being calculated by the inverse conversion of the resolution conversion formula (1). The interpolation processor 482-2 interpolates the luminance of the converted pixel from the input pixel data for each color component. The interpolation algorithm is performed by a linear interpolation method. In the pixel address calculation unit 482-3,
The write address of the work area 424 is calculated from the coordinates of the pixel currently being calculated. The writing unit writes a new pixel value based on the pixel address and the interpolation data. On the work area 424, the areas to which the input image and the output image are assigned are different areas.

(Color Space Conversion Circuit 483) FIG. 32 shows a functional block diagram of the color space conversion circuit 483. In the color space conversion, an input image in the RGB space is converted into a CMYK space which is a printing color. Pixel data input unit 4
83-1 inputs pixel data on the work area 424 for storing the result of the affine transformation for each pixel. The table conversion unit 483-2 inputs the RGB image data,
The image data of each color of CYMK is output. In this embodiment, C
Since the MYK colors are processed for each color, only one color conversion table is required at a time. When it is desired to process four colors simultaneously, a conversion table for four colors is built in. Further, the conversion table is built in the table conversion unit 452, and has nine representative points for each color of RGB as table addresses in order to reduce the capacity of the table. This is performed by the processing unit 483-3. The interpolation processing unit 483-3 obtains detailed conversion values by three-dimensional linear interpolation processing from six representative points surrounding one point in the RGB color space to be converted. FIG. 33 shows this process. For the point P in the RGB space to be converted, look up the conversion values of six points (a, b, c, d, e, f) that become the vertices of a triangular prism surrounding the point P in the table conversion unit 483-2. It is obtained from an up table, and linear interpolation is performed based on this. The writing unit 483-4 overwrites the conversion result on the same address input by the pixel data input unit 483-1.

(Trapezoid processing circuit 484) Trapezoid drawing circuit 4 for drawing image data in a trapezoid area
The configuration of 84 is basically the same as the functional block for trapezoidal processing of characters and graphics shown in FIG. The image is pasted on the trapezoid area as shown in FIG. 8B. At this time, the difference unique to the drawing of the image in FIG. 27 is that the intermediate data input unit 463 inputs the image data from the work area 424 and outputs the image data to the edge drawing unit 466. Intermediate data representing trapezoidal data is input from an input buffer. The edge drawing unit 466 writes the output image in the band buffer currently being output, as in the case of characters and graphics.

(Screen Processing Circuit 485) When the number of colors per color held as data is larger than the number of colors per color that can be expressed by the printer, the screen has a color value of the number of colors that can be expressed by the printer. This is the process for converting to. This typical processing is called halftone processing, which has NxM threshold data called a halftone matrix, compares the data with image data for each color, and determines a color value for each color of the printer. It is. For example, when processing image data represented by 8 bits per color by a printer with 1 bit per color, an arbitrary value from 0 to 255 is stored in the halftone matrix of the NxM threshold data. Then, by comparing the value of the actual image data with the halftone matrix threshold data determined by the position of the image,
If the image data is larger, a color value for printing the pixel is output; otherwise, a color value for not printing the pixel is output.

The above is the configuration of the processing circuit 480 corresponding to a combination of processing (decompression processing, resolution conversion, color space conversion, trapezoid processing, screen) whose processing object is image data and whose expansion processing ID corresponds to CodeG. And the processing contents performed by it.

The reconfiguration hardware unit 46 performs input / output with respect to the memory through the arbitration unit 45, and stores the expansion result in the band buffer.

(Utilization of Expansion Processing Unit as Accelerator) In the present embodiment, the intermediate data generation processing is described to be performed by the intermediate data generation unit 31. By changing the hardware configuration, it is also possible to cause the reconfigurable developing unit 40 to execute the processing.

This will be described with reference to FIG. For example,
LZ input to the instruction execution unit 311 of the intermediate data generation unit
The W-compressed image is converted to an L by the conventional image processing unit 312.
The data is expanded by ZW, subjected to matrix calculation, compressed by LZW, and sent to the band decomposition management unit 219. This processing is performed by the reconfigurable developing unit 40 of the expansion processing unit 4 instead of the image processing unit 312. The reconstructed data for performing such processing is developed by the processing ID
Together with the configuration data management unit 41 in advance, and when an image to be processed is input to the image processing unit 312,
The image processing unit 312 interprets the contents of the processing, and sends the expansion processing ID and the input image data to the reconfigurable expansion unit 40. The reconfigurable expansion unit 40 acquires the configuration data from the configuration data management unit based on the transmitted expansion process ID,
Reconfigure internal reconfigurable hardware. Thereafter, in accordance with the image processing procedure, the received input image data is processed using the reconfigurable hardware, and the image data created as the processing result is sent back to the image processing unit 312. With such a configuration, the reconfigurable deployment unit 4
0 reconfigurable resources can be used effectively.

(Partial Rewriting of Reconfiguration Hardware) The rewriting of the reconfiguration hardware unit 46 performed by the reconfiguration control unit 41 described above is based on the premise that all hardware resources are rewritten. A method of partially rewriting the configuration hardware unit 46 as necessary may be considered. Partial reconfiguration hardware unit 4
The control method of the reconfiguration control unit 41 on the premise of the rewriting of No. 6 will be described. In this case, all objects that can be processed in parallel when generating the data structure of FIG. FIG. 35 is a flowchart of a process performed by the reconfiguration control unit 41 when partially rewriting the reconfiguration hardware unit 43.
Shown in FIG. 35 is a control flow performed by the reconfiguration control unit 41 for one group of objects that can be processed in parallel. The control flow performed by the reconstruction control unit 41 is S18
To S25. First, in S18, an expansion processing ID of an object to be processed next is input. In S19, it is checked whether or not there is enough space to write the configuration data corresponding to the expansion processing ID input to the resource of the reconfiguration hardware unit 46. If there is a space, the process jumps to S21, and if there is no space, the process proceeds to S20.
In S20, the process waits until the reconfigurable hardware unit 46 completes a partial process being processed. In S21, it is checked whether or not the configuration data needs to be partially rewritten. If the processing performed by the reconfigurable hardware unit 46 and the expansion processing ID of the next processing are the same, there is no need for partial rewriting. If there is no need for partial rewriting, the process jumps to S24. If partial rewriting is necessary, the process proceeds to S22. . S
At 22, the configuration data corresponding to the expansion processing ID input from the configuration data management unit 42 is read, and at S <b> 23 the
Partially write to In S24, a synchronization signal is sent to the reconfiguration hardware unit 46 to inform that the partial writing has been completed and the processing can be started. S
At 25, it is checked whether or not there is still object data in the currently processed collection of parallel-processable objects. If there is, the process returns to S18; otherwise, the process ends. When the processing is completed, the control flow of FIG. 35 is repeated for a new set of objects that can be processed in parallel, after waiting for completion of the expansion processing of all the objects in the reconfiguration hardware unit 46.

[Embodiment 2] FIG. 36 is a block diagram showing the configuration of Embodiment 2 according to the present invention. In FIG. 36, the image processing apparatus includes a print data creation unit 1, a print data input unit 2, a conversion processing unit 3, a development processing unit 4, and an output unit 5. Further, the conversion processing unit 3 includes a lexical analysis unit 30, an intermediate data generation unit 31, an intermediate data optimization unit 34, an intermediate data reconstruction unit 35, and an intermediate data storage unit 33.
The expansion processing unit 4 includes a reconfigurable expansion unit 40, a reconfiguration control unit 41, and a configuration data management unit 42.

In the above configuration, the print data creation unit 1
Since the print data input unit 2, the expansion processing unit 4, and the output unit 5 have the same configuration as those in the first embodiment, the description is omitted here.

The conversion processing unit 3 generates intermediate data that can be expanded into print data in the expansion processing unit 4 from the print data input from the print data input unit 2. It comprises a data generation unit 31, an intermediate data optimization unit 34, an intermediate data reconstruction unit 35, and an intermediate data storage unit 33. The lexical analyzer 30, the intermediate data generator 31, and the intermediate data storage 33
Is the same as the configuration in the first embodiment, and the description is also omitted here.

The intermediate data optimizing unit 34 converts the intermediate data (hereinafter also referred to as an object) for each drawing command after band division generated in the order described in the page description language by the intermediate data generating unit 31 into a band. The rearrangement is performed so that the intermediate data of the same drawing command continues as much as possible. This is because the number of times of reconfiguration of the reconfigurable circuit in the expansion processing unit 4 is reduced to enable high-speed processing. The rearrangement process compares the circumscribed rectangles of the intermediate data for each drawing command for each band, determines whether or not there is an overlap,
If the rearrangement is possible based on the result, the rearrangement is performed so that the intermediate data of the same drawing command continues. If the rearrangement is impossible, the intermediate data is stored in the intermediate data storage unit 33 in the same order. Is written. The reason why it is necessary to determine whether or not the order of the drawing commands can be rearranged depending on whether or not there is an overlap is that PDL uses an imaging model called opaque, so that a plurality of drawing can be performed in the same place. This is because, when performed, only the last drawn command remains as a result. The intermediate data reconstructing unit 35 determines whether to perform the process or skip the process according to the status of the intermediate data compiled for each drawing type in the intermediate data optimizing unit 34. Compared with the threshold value preset in the intermediate data optimization unit 34, if the rearrangement of the intermediate data optimization unit 34 alone is performed, the number of times of reconfiguration of the reconfigurable circuit in the expansion processing unit 4 is sufficiently small. If it is determined that the processing is skipped, the processing is skipped, but if it is determined that the processing is not sufficient, the intermediate data is read from the intermediate data storage unit 33 in band units to remove the overlap between the intermediate data in band units. And generate intermediate data of the result. Since the intermediate data do not overlap at all, the intermediate data is completely reconstructed collectively for each drawing type, and written to the intermediate data storage unit 33 again in band units. This process is repeated for the number of bands.

Next, the flow of print data in the print processing apparatus configured as described above will be summarized.

The print data created by the print data creation unit 1 is input to the lexical analysis unit 30 of the conversion processing unit 3 via the print data input unit 2. The token cut out from the print data in the lexical analyzer 30 is input to the intermediate data generator 31. The intermediate data generated by the intermediate data generating unit 31 and divided into band units is input to the intermediate data optimizing unit 34, where the intermediate data is rearranged so that the same drawing instruction is continued as much as possible, and the intermediate data is processed in band units. The data is written to the storage unit 33. The intermediate data read out from the intermediate data storage unit 33 in units of bands as necessary is input to the intermediate data reconstructing unit 35, reconstructed into intermediate data that is completely grouped for each drawing command, and re-created in band units. Is written to the intermediate data storage unit 33.

Since the expansion processing section 4 and the output processing section 5 have the same configuration as in the first embodiment, the description is omitted here.

The outline of the image processing apparatus of the present invention has been described above. Next, details of a main part of the image processing apparatus will be described.

Here, the intermediate data optimizing unit 34 and the intermediate data reconstructing unit 35 in the generation processing unit 3 having a different configuration from the first embodiment will be mainly described.

First, the details of the intermediate data optimizing unit 34 will be described. FIG. 37 shows the configuration of the intermediate data optimization unit 34. The intermediate data optimization unit 34 includes a band number determination unit 326 and a number of divided intermediate data optimization units 327 corresponding to the number of bands. FIG. 37 shows that one page is divided into four bands, and the four intermediate data optimization units 327 that match the number of bands of four use the intermediate data optimization unit 3.
4 is configured. Band number determination unit 32
6 determines the band ID included in the object transferred from the band decomposition unit 319, and
The object related to the section intermediate data optimization unit 327 corresponding to D is transferred.

FIG. 38 shows the structure of the segmented intermediate data optimizing unit 327 (for the sake of convenience, two segmented intermediate data optimizing units 32).
7 only). Sectional intermediate data optimization unit 327
Are the latch processing unit 3271 and the circumscribed rectangle overlap determination unit 32
72, an output buffer 3273, and a circumscribed rectangle set storage unit 3274. The latch processing unit 3271 holds the object as the intermediate data transferred from the band number determination unit 326. Circumscribed rectangle overlap determiner 3272
Determines the overlap of the circumscribed rectangles of the objects held by the latch processing unit 3271. In addition, the circumscribed rectangle overlap determination unit 3272 adds an object to the output buffer 3273 or flushes the output buffer 3273 based on a procedure described later. Output buffer 3
The output buffer group 273 includes a so-called first-in first-out type output buffer group for each processing type, that is, for each expansion processing ID as shown in FIG. 39 in order to enable sequential processing.
The circumscribed rectangle set storage unit 3274 holds, as a bitmap, a set of circumscribed rectangle data of each object for which overlap of the circumscribed rectangle is determined by the circumscribed rectangle overlap determination unit 3272 (hereinafter, each object is stored as a bitmap). A set of circumscribed rectangle data is referred to as a circumscribed rectangle set.) The circumscribed rectangle set is used for the overlap determination of the circumscribed rectangle in the circumscribed rectangle overlap determination unit 3272. In the overlap determination of the circumscribed rectangle, the circumscribed rectangle data for which the overlap of each object is to be determined is hereinafter referred to as a circumscribed rectangle to be inspected. An object corresponding to the circumscribed rectangle to be inspected is called an object to be inspected. The circumscribed rectangle overlap determination unit 3272 stores the expansion processing I in order to hold the expansion processing ID of the object processed immediately before the object to be inspected.
A D register is provided.

The circumscribed rectangles overlap when the circumscribed rectangle to be inspected overlaps the circumscribed rectangle set (a) or when the circumscribed rectangle to be inspected does not overlap the circumscribed rectangle set (b) (FIG. 4).
0), the processing type of the object to be inspected and the processing type of the object processed immediately before processing the object to be inspected, that is, whether the processing type indicated by the expansion processing ID register is the same,
As shown in FIG. 41, it is divided into four modes. Below, FIG.
2, a procedure of intermediate data optimization performed for each band, that is, a processing procedure of trapezoidal data rearrangement in each segmented intermediate data optimization unit 327 will be described.

(1) Initialization of the circumscribed rectangle overlap determination unit 3272 and others (S26).

The development processing ID register of the circumscribed rectangle overlap determination unit 3272 is cleared. The bitmap stored in the circumscribed rectangle set storage unit 3274 is cleared. The buffer of each output processing ID of the output buffer 3273 is cleared.

(2) Object latch processing (S2
7).

The latch processing unit 3271 holds the object for each band transferred from the band number determination unit 326. The held object is the object to be inspected.

(3) Judgment of identity of processing type (S2
8).

The circumscribed rectangle overlap determination section 3272 determines the identity between the processing type of the object to be inspected held by the latch processing section 3271 and the processing type of the object processed immediately before. That is, it is determined whether the expansion processing ID of the inspection object is equal to the expansion processing ID stored in the expansion processing ID register.

If the processing types are the same, the expansion processing ID
The register value is assigned to the process ID of the inspection object.
And the process proceeds to S30. On the other hand, if the processing types are different, the value of the expansion processing ID register is updated with the expansion processing ID of the object to be inspected, and the process proceeds to S29.

FIG. 43 shows the latch processing unit 3271 and the circumscribed rectangle overlap determination unit 3272 in determining the identity of the processing type.
2 shows the state of the expansion processing ID register. For example, when the latch processing unit 3271 sequentially stores the object 1 having the expansion processing ID of Code A, the object 2 having the expansion processing ID of Code A, and the object 3 having the expansion processing ID of Code B, the object 2 is processed. When the object is the inspection object, the value of the expansion processing ID register is Code A, and it is determined that the processing types are the same. When the object 3 is the object to be inspected, the value of the development processing ID register is Code.
B, and it is determined that the processing types are different.

When processing is performed on the first object held in the latch processing unit 3271, the expansion processing I
Since the D register has been cleared, the value of the expansion processing ID register is updated with the expansion processing ID of the object to be inspected, and the process immediately proceeds to S30.

(4) Judgment of overlap of circumscribed rectangles (S2
9).

The circumscribed rectangle overlap judging section 3272 judges the overlap between the circumscribed rectangles to be inspected and the circumscribed rectangle set held by the circumscribed rectangle set storage section 3274 by calculating the logical product.

If the circumscribed rectangle to be inspected overlaps the circumscribed rectangle set (a), the process proceeds to S31. On the other hand, when the circumscribed rectangle to be inspected does not overlap the circumscribed rectangle set (b), S3
Move to the process of 0.

(5) Object connection processing (S3
0).

[0116] The logical sum of the bitmap data corresponding to the circumscribed rectangle to be inspected and the bitmap data held in the circumscribed rectangle set storage unit 3274 is calculated, and the bitmap data in the circumscribed rectangle set storage unit 3274 is calculated based on the result. To update. The object to be inspected is added to the output buffer corresponding to the expansion processing ID of the output buffer 3273. Subsequently, the process proceeds to S32.

For example, FIG. 44 shows the circumscribed rectangle set storage unit 32.
The state of the bitmap update process at 74 is shown. The logical sum of the circumscribed rectangle to be inspected and the circumscribed rectangle set is calculated, and the bitmap is updated with the result. Also, when the object 2 whose circumscribed rectangle does not overlap with the object 1 is held in the latch processing unit 3271, the object shown in FIG.
The object 2 is linked to the object 1 in a first-in first-out manner as shown in FIG.

(6) Buffer flush processing (S3
1).

The bit map of the circumscribed rectangle set storage unit 3274 is cleared. The objects stored in the buffer for each expansion processing ID of the output buffer 3273 are transferred to the intermediate data storage unit 33 in a predetermined order. Then, S1
Move on to 3g processing.

(7) Inspection of existence of object to be processed (S32).

The latch processing section 3271 determines whether or not the object transferred from the band number determination section 326 is an EOD indicating the end of the object for each band, thereby checking whether or not there is an object to be processed. If there is an object to be processed, the process proceeds to S27. On the other hand, if there is no object to be processed, the process ends.

If the expansion processing unit 4 can process a plurality of processes of the same or different configuration data in parallel, that is, simultaneously, a plurality of processes, the divided intermediate data optimization unit 327 may be configured and operated as follows. it can. First,
As shown in FIG. 45, the circumscribed rectangle set storage unit 3274 is configured to hold the coordinates of the vertices of the circumscribed rectangle for each layer in a list format. Here, the circumscribed rectangle overlap determination unit 3272
A unit of processing for each single object or a plurality of objects distinguished by the overlap of circumscribed rectangles in is referred to as a layer. Objects in each layer do not overlap each other. Also, as shown in FIG.
Is configured to hold objects to which layer numbers are added in a list format. As for the data of the layer number, the object is stored in the intermediate data storage unit 3 from the output buffer 3273.
3 when it is forwarded. Here, the expansion processing ID register is not necessary for the circumscribed rectangle overlap determination unit 3272. The circumscribed rectangle overlap determination unit 3272 includes a layer total number register that holds the value of the total number of layers, a current layer register that holds the value of the layer number being processed, and a circumscribed rectangle for each layer held in the circumscribed rectangle set storage unit 3274. A circumscribed rectangle register is provided for holding the last data of the list data of the rectangle vertex coordinates. According to the procedure shown in FIG.
Optimize the arrangement of objects as follows.

(1) Initialization of the circumscribed rectangle overlap determination unit 3272 and others (S33).

The values of the layer total number register and the current layer register of the circumscribed rectangular overlap determination unit 3272 are set to 0. The circumscribed rectangle register, the circumscribed rectangle set storage unit 3274, and the output buffer 3273 are cleared.

(2) Object latch processing (S3
4).

The latch processing unit 3271 holds the object for each band transferred from the band number determination unit 326. The held object is the object to be inspected.

(3) Judgment of overlap of circumscribed rectangles (S35).

The circumscribed rectangle overlap judging section 3272 judges the overlap between the circumscribed rectangle of the object to be inspected held in the latch processing section 3271 and the circumscribed rectangle held in the circumscribed rectangle register. If the bounding rectangles overlap,
The process proceeds to S36. On the other hand, if the circumscribed rectangles do not overlap, the process proceeds to S37. FIG. 48 shows the state of the layers due to the overlapping of the circumscribed rectangles. For example, the object 1, the object 2, and the object 3 are sequentially stored in the latch processing unit 32.
When the circumscribed rectangle of the object 1 and the circumscribed rectangle of the object 2 do not overlap each other, the layers are the same. Here, object 1 and object 2 belong to the first layer. When the circumscribed rectangle of the object 2 and the circumscribed rectangle of the object 3 overlap, the object 3 belongs to a layer different from that of the object 2. Here, the object 3 belongs to the second layer.

(4) Object List Addition Processing (S
36).

The value held by the layer total number register is incremented. The circumscribed rectangle of the object to be inspected is added as the last data of the list data in the circumscribed rectangle set storage unit 3274, and the circumscribed rectangle data is set as the contents of the circumscribed rectangle register. Further, the object to be inspected is added as a layer number with the value held by the layer total number register and added as the last data of the list data in the output buffer 3273. FIG. 49 shows a state before and after the object to be inspected is added to the list data in the output buffer 3273. The layer total register is incremented from 1 to 2, and the object 3 to be inspected is added so as to follow the object 2. At this time, the layer number 2 is added to the object 3.

(5) Object List Insertion Processing (S
37).

FIG. 50 shows a detailed processing procedure of the following object list insertion processing (S37).

(5.1) Initialization of the current layer register (S39).

Assume that the value of the current layer register is 1.

(5.2) Judgment of overlap of circumscribed rectangles (S4
0).

The circumscribed rectangle overlap judging section 3272 stores the circumscribed rectangle of the object to be inspected and the circumscribed rectangle set storage section 3.
The overlap with the circumscribed rectangle corresponding to the layer number held in the current layer register held in 274 is determined. If there is an overlap, the process proceeds to S41. On the other hand, when there is no overlap, the process proceeds to S42.

(5.3) Increment of Current Layer Register (S41) The circumscribed rectangle overlap determination unit 3272 increments the value held by the current layer register, and proceeds to the processing of S40.

(5.4) Update of circumscribed rectangular vertex coordinates (S4
2).

The circumscribed rectangle overlap determination unit 3272 calculates the circumscribed rectangle vertex coordinates corresponding to the layer number held in the current layer register and held in the circumscribed rectangle set storage unit 3274 based on the circumscribed rectangle of the object to be inspected. Update. FIG. 51 shows a state before and after updating the circumscribed rectangular vertex coordinates. For example, following object 1, object 1
When the object 2 whose circumscribed rectangle does not overlap with the circumscribed rectangle of is stored in the latch processing unit 3271, the current layer register is 1, and the circumscribed rectangle corresponding to the first layer stored in the circumscribed rectangle set storage unit 3274 Vertex coordinates (Fig. 51
When the hatched rectangle in the upper part of the figure indicates the coordinates of the circumscribed rectangle of the object 1, the circumscribed rectangle including the circumscribed rectangle of the object to be inspected, that is, the circumscribed rectangle of the object 2 (the solid-line rectangle in FIG. 51) (dashed line in FIG. 51) Is calculated, and the calculation result is updated to a circumscribed rectangle (FIG. 5) corresponding to the first layer.
1 (the lower hatched rectangle) is stored in the circumscribed rectangle set storage unit 3274.

(5.5) Object List Insertion Processing (S43) The circumscribed rectangle overlap determination unit 3272 outputs the object to be inspected as the last object of the layer corresponding to the layer number held in the current layer register. Buffer 32
73 is added to the list. At this time, a layer number is added to the object. FIG. 52 shows the state before and after the object list insertion processing. Current layer register is 1
, The object 4 is the object 3 after the object 2 with the layer number 1 and the object 3 with the layer number 2
Inserted before. At this time, the layer number 1 is added to the object 4.

(6) Inspection of existence of object to be processed (S38).

The latch processing unit 3271 determines whether or not the object transferred from the band number determination unit 326 is an EOD indicating the end of the object for each band, thereby checking whether or not there is an object to be processed. If there is an object to be processed, the process proceeds to S34. On the other hand, if there is no object to be processed, the process ends. The objects held in the output buffer 3273 in the form of a list are transferred to the intermediate data storage unit 33 in a predetermined order for each layer and processed in parallel.

Finally, the intermediate data reconstructing section 35 will be described in detail. The reconstruction of the intermediate data, that is, the removal of the overlap of the trapezoidal data is performed by the intermediate data reconstruction unit 3 shown in FIG.
5 is performed. The intermediate data reconstruction unit 35 includes a page end determination unit 331 and a number of segmented intermediate data reconstruction units 332 corresponding to the number of bands. FIG.
One page is divided into four bands, indicating that the intermediate data reconstructing unit 35 is composed of four divided intermediate data reconstructing units 332 corresponding to four bands. FIG.
4 shows a processing procedure of intermediate data reconstruction. First, the page end determination unit 331 determines whether or not all the latch processing units 3271 of the intermediate data optimization unit 34 hold an EOD indicating the end of the object to be processed in each band. It is determined whether or not the page has ended based on whether or not one page of data has been transferred to the intermediate data storage unit 33, and an instruction to start the operation of all the divided intermediate data reconstruction units 332 is issued (S44). The sectioned intermediate data reconstruction unit 332 reconstructs the intermediate data corresponding to each band from the intermediate data storage unit 33, and transfers the result to a portion of the intermediate data storage unit 33 corresponding to each band (S45). The sectioned intermediate data reconstruction unit 332 is described below.
And the procedure of S35 will be described in detail.

FIG. 55 shows an example of the configuration of the sectioned intermediate data reconstructing section 332. The section intermediate data reconstruction unit 332
Intermediate data transfer unit 3321, input band buffer 332
2. Fetch processing unit 3323, trapezoid overlap determination unit 332
4. It is composed of a trapezoidal data subdivision unit 3325 and an output band buffer 3326. Intermediate data transfer unit 3
Numeral 321 transfers the intermediate data from the intermediate data storage unit 33 to the input band buffer 3322, and transfers the reconstructed intermediate data from the output band buffer 3326 to the intermediate data storage unit 33. The input band buffer 3322 is configured as a so-called first-in first-out type band buffer, and holds an object as intermediate data. The fetch processing unit 3323 transfers the object held in the input band buffer 3322 to the trapezoid overlap determination unit 3324. The trapezoid overlap determination unit 3324 determines the overlap of the trapezoid data of each object according to a procedure described later. The trapezoid overlap judging unit 332 outputs the output band buffer 33.
26 has an index holding register Reg CUR for indicating the position of the object in 26. The trapezoid data subdivision unit 3325 converts the trapezoid data so that the trapezoid data of all objects held in the output band buffer 3326 does not overlap with the trapezoid data of the object transferred to the trapezoid overlap determination unit 3324 by the fetch processing unit 3323. Subdivide. Output band buffer 332
Reference numeral 6 holds an object having no trapezoidal data overlap. In the output band buffer 3326, the objects are held in a list format in which the end is specified. The reconstruction of the intermediate data for each band is performed by the following procedure as shown in FIG.

(1) Initialization of the trapezoid overlap judging unit 3324 and others (S46).

The intermediate data transfer section 3321 transfers the intermediate data corresponding to each band from the intermediate data storage section 33 to the input band buffer 3322. Output band buffer 3
Clear 326.

(2) Object fetch processing (S4
7).

The fetch processing unit 3323 transfers the object from the input band buffer 3322 to the trapezoid overlap determination unit 3.
324. The object is an object to be inspected.

(3) Overlapping removal processing of trapezoidal data (S4
8).

FIG. 57 shows the details of the following trapezoidal data overlap removal processing procedure.

(3.1) Initialization of the index holding register (S51).

Index holding register Reg CUR
Is an index indicating the position of the head object of the output band buffer 3326.

(3.2) Overlap judgment of trapezoidal data (S5
2).

The trapezoidal overlap judging section 3324 calculates the trapezoidal data
The overlap with all trapezoidal data constituting the object held in the output band buffer 3326 indicated by the index of the index holding register Reg CUR is checked. If there is an overlap, the process proceeds to S13p.
On the other hand, when there is no overlap, the process proceeds to S54.

(3.3) Trapezoidal data division processing (S5
3).

The trapezoidal data re-dividing unit 3325 further divides the trapezoidal data held in the output band buffer 3326, which is judged by the trapezoidal overlap judging unit 3324 to overlap with the trapezoidal data of the object to be inspected, into trapezoidal data. The trapezoidal data corresponding to the overlapping part is removed. FIG. 58 shows the trapezoid data before and after the overlap removal processing. Object to be inspected is object 2
When the trapezoid data of the object 1 overlaps with the trapezoid data of the object 1, the trapezoid data of the object 1 is divided as shown in FIG. Here, the trapezoid data of the object 2 itself is not changed.
In this way, the overlap is removed so that the trapezoid data of the object to be inspected is overwritten.

(3.4) Update processing of the index holding register (S54).

Index holding register Reg CUR
Updates the value to hold the index indicating the location of the following object.

(3.5) Inspection of existence of object to be processed (S55).

The trapezoid overlap judging unit 3324 checks whether or not there is an object to be processed by judging whether or not the object indicated by the index held by the index holding register Reg CUR is the last object. If there is an object to be processed, the process proceeds to S52. On the other hand, when there is no object to be processed, the process proceeds to S49.

(4) Object Addition Processing (S4
9).

The object to be inspected is added to the output band buffer 3326.

(5) Inspection of existence of object to be processed (S50).

The fetch processing unit 3323 checks whether or not there is an object in the input band buffer 3322 to check whether or not there is an object to be processed. If there is an object to be processed, S48
Move on to processing. On the other hand, if there is no object to be processed, the process ends.

In order to reduce the number of rewrites of the configuration data in the expansion processing unit 4, after S50, the intermediate data is rearranged so as to be continuous for each expansion processing ID for each band in the intermediate data storage unit 33, or The output band buffer 3326 of each sectioned intermediate data reconstruction unit 332 is
The output buffer 3273 of the intermediate data optimizing unit 34 is configured as a buffer for each expansion processing ID, and can be sequentially rearranged so that the intermediate data is continuous for each expansion processing ID for each band. Further, as described above, when the rewriting of the configuration data in one band is equal to or less than the predetermined value, the processing from S46 to S50 may be omitted.
That is, after the intermediate data optimizing process and before the intermediate data reconstructing process, the number of times the development process ID of each object in the intermediate data storage unit 33 changes is counted. Configuration processing can also be omitted.

[Third Embodiment] FIG. 59 is a block diagram showing a configuration of a third embodiment according to the present invention. 59, the image processing apparatus includes a print data creation unit 1, a print data input unit 2, a conversion processing unit 3, a development processing unit 4, and an output unit 5. Further, the conversion processing unit 3 includes a lexical analysis unit 30, an intermediate data generation unit 31, a parallel processing determination unit 36, and an intermediate data storage unit 33. The expansion processing unit 4 includes a reconfigurable expansion unit 40, a reconfiguration control unit 41, and a configuration data management unit 42.

In the above configuration, the print data creation unit 1
Since the print data input unit 2, the expansion processing unit 4, and the output unit 5 have the same configuration as those in the first embodiment, the description is omitted here.

The conversion processing unit 3 generates intermediate data that can be expanded into print data in the expansion processing unit 4 from the print data input from the print data input unit 2. It comprises a data generation unit 31, a parallel processing determination unit 36, and an intermediate data storage unit 33.
Of these, the lexical analyzer 30 and the intermediate data generator 31
Since the intermediate data storage unit 33 has the same configuration as that of the first embodiment, the description is omitted here.

The parallel processing judging section 36 sequentially reads the intermediate data output from the intermediate data generating section 31, makes an overlap judgment between them, and judges that there is no overlap between a plurality of continuous intermediate data. In this case, as a group of intermediate data that can be processed in parallel, a hardware configuration ID that is an identifier for configuration data to be written in the reconfigurable expansion unit 40 of the expansion processing unit 4 and that performs parallel processing is added, and the intermediate data storage Output to the unit 33.

Next, the flow of print data in the print processing apparatus configured as described above will be summarized.

The print data created by the print data creation unit 1 is input to the lexical analysis unit 30 of the conversion processing unit 3 via the print data input unit 2. The token cut out from the print data in the lexical analyzer 30 is input to the intermediate data generator 31. The intermediate data divided in band units generated by the intermediate data generation unit 31 is input to the parallel processing determination unit 36, and based on the overlap of the intermediate data,
The data is divided into groups that can be processed in parallel, and one page is stored in the intermediate data storage unit 33 in band units.

Since the expansion processing unit 4 and the output processing unit 5 have the same configuration as that of the first embodiment, the description is omitted here. The outline of the image processing apparatus of the present invention has been described above. Next, details of a main part of the image processing apparatus will be described.

Here, the parallel processing judging section 36 in the conversion processing section 3 having a configuration different from that of the first embodiment will be mainly described.

The parallel processing judging section 36 sequentially reads the intermediate data output from the intermediate data generating section 31 and makes an overlap judgment sequentially. When it is judged that there is no overlap between a plurality of continuous intermediate data, As a group of intermediate data that can be processed in parallel, a hardware configuration ID that is an identifier for configuration data to be written in the reconfigurable expansion unit 40 of the expansion processing unit 4 and that performs parallel processing is added to the intermediate data storage unit 33. Output. The output data format in the parallel processing determination unit 36 is the same as that in FIG. 10 shown in the first embodiment. In FIG. 10, the data structure of the intermediate data output by the parallel processing determination unit 36 is organized for each object that can be processed in parallel. The data of each set includes a band ID, a hardware configuration ID, the number of objects, and data of objects belonging to the set. FIG. 60 shows a configuration diagram of the parallel processing determination unit 36. In FIG. 60, 3
61 is an input object buffer, 362 is an overlap determination unit, 363 is a configuration data addition unit, and 364 is an output object buffer.

The input object buffer 361 inputs and stores object data. The unit for inputting and storing the object data may be one, a plurality of drawing objects, or a larger unit such as a band or a page. The overlap determination unit 362 determines the overlap between objects by inputting the coordinate values of the circumscribed rectangle of each object having the same band ID to the objects sequentially stored in the input object buffer 321. The overlap determination between the objects is to determine the overlap between the circumscribed rectangle corresponding to the band ID of the input object and the circumscribed rectangle of the input object among the circumscribed rectangles held for each band by the overlap determination unit. . The description of the processing in the future will be limited to the band corresponding to the band ID of the input object since the processing is independent for each band. The circumscribed rectangle held by the overlap judging unit 362 starts from nothing at first and then becomes the circumscribed rectangle of the first input object. Then, from the next object, overlap determination is performed, and if it is determined that there is no overlap, the circumscribed rectangle held is set to the circumscribed rectangle of the area where the circumscribed rectangle of the input object and the object itself are ORed. Be changed. If it is determined that there is overlap,
The held circumscribed rectangle is replaced with the circumscribed rectangle of the input object. In the overlap judgment, the lower left coordinates (ldx0, ldy0) and upper right coordinates (rux0, ruy0) of the circumscribed rectangle, the lower left coordinates (ldx1, ldy1), and the upper right coordinates (rux1, ruy1) of the circumscribed rectangle of the input object are stored. When the following expression is satisfied, it is determined that there is no overlap.

[0176]

Ldx0> rux1 or rux0 <ldx1 or ldy0> ruy1 or ruy0 <ldy1 OR of a circumscribed rectangle when it is determined that there is no overlap
Becomes

[0177]

Ldx0 = min (ldx0, ldx1), ldy0 =
min (ldy0, ldy1), rux0 = max (rux0, rux1), ruy0 =
max (ruy0, ruy1) The determination result thus determined is sent to the configuration data adding unit 363. The configuration data adding unit 363 determines the result of the determination and the object ID of the input object.
In the case where the judgment result indicates that there is no overlap, the expansion processing unit 4 can be reconfigured from the object ID of the previously input object stored in the output object buffer 364 and the object ID of the input object. If the combination is a combination that can be processed in parallel by the expansion unit 40, the input object is additionally written into the output object buffer 364. If the combination cannot be processed in parallel by the reconfigurable expansion unit 40 of the expansion processing unit 4, the parallel processing configuration data for the previously input object group stored in the output object buffer 364 is added. Then, after sending the object stored in the output object buffer 364 to the intermediate data storage unit 33, the input object is written to the output object buffer 364, and the circumscribed rectangle of the input object is input to the overlap determination unit 362. Then, the data of the circumscribed rectangle and the band ID are sent so that the held circumscribed rectangle is reset. If the determination result indicates that there is overlap, the output object buffer 364 is output.
After adding the configuration data of the parallel processing to the previously input object group stored in the output object buffer 364 and sending out the object stored in the output object buffer 364 to the intermediate data storage unit 33, the input object is output. A process for writing to the object buffer 364 is performed. The output object buffer 364 inputs and stores object data. If the number of objects to be input and stored is equal to or more than the maximum number of objects that can be processed in parallel in the reconfigurable expansion unit 40 of the expansion processing unit 4, even if the number of objects is larger, such as a band or a page. Good. In this way, the data output from the parallel processing determination unit 36 is sequentially sent to the intermediate data storage unit 33.

[0178] The processing after the expansion processing section 4 is the same as that of the first embodiment, and therefore the description is omitted.

The description of the embodiment of the present invention has been completed.
Note that the present invention is not limited to the above-described embodiment, and can be variously changed without departing from the gist of the present invention. For example, the reconfiguration hardware unit 46 is configured as shown in FIG.
As shown in (1), the configuration is made of an FPGA, but a plurality of arithmetic processing units (arithmetic and logical operation units) may be provided, and the input / output flow of each arithmetic processing unit may be controlled by the switching device. In this case, for example, the logical block 4 in FIG.
An arithmetic processing unit may be arranged as 621. Further, a simple gate may be used instead of the cross point switch 4622 or the switch matrix 4623.

[0180]

As described above, according to the present invention, characters,
A print processing device that has one of a drawing element of a figure and an image and receives print data described by a predetermined drawing command and outputs the print data to an output device. By using hardware, the required amount of hardware can be reduced, and the throughput can be improved by adopting an optimum hardware configuration according to the print data to be processed. For example, judging the overlap of drawing elements included in the print data, and rearranging the drawing elements of the print data based on the determination information and the contents of the print data, thereby causing the reconfiguration hardware means to operate in parallel. When,
By reducing the number of changes in the configuration of the reconfigurable hardware means, it is possible to speed up the expansion processing by the reconfigurable hardware means.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a configuration of a color page printer.

FIG. 3 is a block diagram illustrating an intermediate data generation unit.

FIG. 4 is a diagram illustrating an outline vector.

FIG. 5 is a diagram illustrating recursive division of a Bezier curve.

FIG. 6 is a diagram illustrating trapezoidal data.

FIG. 7 is a diagram illustrating division of trapezoidal data at a band boundary.

FIG. 8 is a diagram illustrating an example of a data representation of trapezoidal data.

FIG. 9 is a diagram for explaining correspondence of image data to trapezoidal data.

FIG. 10 is a diagram illustrating a data structure generated by an intermediate data order control unit.

FIG. 11 is a block diagram illustrating an intermediate data order control unit.

FIG. 12 is a diagram illustrating overlapping of drawing objects in a band area.

FIG. 13 is a diagram illustrating an example of an optimization table.

FIG. 14 is a flowchart illustrating a procedure in which a configuration data selection unit selects configuration data.

FIG. 15 illustrates an example of a candidate for a hardware configuration ID.

FIG. 16 is a block diagram of a reconfigurable developing unit.

FIG. 17 is a diagram illustrating a method of using a force buffer and a band buffer.

FIG. 18 is a flowchart illustrating a procedure in which a configuration control unit controls a reconfiguration hardware unit.

FIG. 19 is a diagram showing a configuration of a configuration data management unit.

FIG. 20 is a block diagram illustrating a configuration example of a reconfiguration hardware unit.

21 is a diagram illustrating a configuration of the FPGA unit in FIG.

FIG. 22 is a diagram for explaining the logical block in FIG. 21;

FIG. 23 is a diagram illustrating the cross point switch of FIG. 21.

FIG. 24 is a diagram illustrating the switch matrix of FIG. 21.

FIG. 25 is a diagram illustrating a configuration of a reconfiguration hardware unit when a hardware configuration ID is X;

FIG. 26 is a diagram illustrating trapezoidal data drawing.

FIG. 27 is a functional block diagram of a trapezoidal drawing circuit.

FIG. 28 is a functional block diagram of a coordinate calculation unit.

FIG. 29 is a functional block diagram of an edge drawing unit.

FIG. 30 is a functional block diagram of a decompression processing circuit.

FIG. 31 is a functional block diagram of a resolution conversion circuit.

FIG. 32 is a functional block diagram of a color space conversion circuit.

FIG. 33 is a diagram illustrating a process of linear interpolation of color space conversion.

FIG. 34 is a diagram illustrating a relationship between the conversion processing unit and the expansion processing unit when the expansion processing unit is used as an accelerator.

FIG. 35 is a flowchart illustrating a control procedure performed by the reconfiguration control unit when partially rewriting the reconfiguration hardware unit;

FIG. 36 is a block diagram showing a second embodiment of the present invention.

FIG. 37 shows an example of the configuration of the intermediate data optimization section 34.

FIG. 38 shows an example of the configuration of a sectioned intermediate data optimization section 327.

FIG. 39 illustrates an example of a configuration of an output buffer 3273.

FIG. 40 illustrates an aspect of overlapping circumscribed rectangles in the second embodiment.

FIG. 41 illustrates a mode of overlapping circumscribed rectangles based on the same processing type according to the second embodiment.

FIG. 42 shows a processing procedure of intermediate data optimization.

FIG. 43 shows how a latch processing unit 3271 and a circumscribed rectangle overlap determination unit 3272 determine the identity of processing types.

FIG. 44 shows a state of a bitmap update process of the circumscribed rectangle set storage unit.

FIG. 45 illustrates an example of a configuration of a circumscribed rectangle set storage unit 3274.

FIG. 46 illustrates an example of a configuration of an output buffer 3273.

FIG. 47 shows a processing procedure of second intermediate data optimization.

FIG. 48 shows a state of layers formed by overlapping circumscribed rectangles.

FIG. 49 shows an object list adding process.

50 shows details of the object list insertion processing procedure in FIG. 47.

FIG. 51 shows a state before and after updating the circumscribed rectangular vertex coordinates.

FIG. 52 shows an object list insertion process.

FIG. 53 shows an example of the configuration of an intermediate data reconstruction unit 35.

FIG. 54 shows a processing procedure of intermediate data reconstruction.

FIG. 55 shows an example of the configuration of a sectioned intermediate data reconstruction unit 332.

FIG. 56 shows a processing procedure of intermediate data reconstruction for each band.

FIG. 57 shows a trapezoidal data overlap removal processing procedure.

FIG. 58 shows a state before and after a trapezoidal data overlap removal process.

FIG. 59 is a block diagram showing a third embodiment of the present invention.

FIG. 60 is a block diagram illustrating a parallel processing determination unit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Print data creation part 2 Print data input part 3 Conversion processing part 4 Expansion processing part 5 Output part 30 Lexical analysis part 31 Intermediate data generation part 310 Token interpretation part 311 Command execution part 312 Image processing part 313 Drawing state storage part 314 Vector data Generation unit 315 Font management unit 316 Matrix conversion unit 317 Short vector generation unit 318 Trapezoidal data generation unit 319 Band decomposition management unit 32 Intermediate data order control unit 321 Object buffer 322 Drawing order dependence detection unit 323 Optimization table creation unit 324 Configuration data selection Section 325 reorder section 326 band number determination section 327 section intermediate data optimization section 3271 latch processing section 3272 circumscribed rectangle overlap determination section 3273 output buffer 3274 circumscribed rectangle set storage section, 33 intermediate data storage section 332 Intermediate data transfer unit 3322 Input band buffer 3323 Fetch processing unit 3324 Trapezoid overlap determination unit 3325 Trapezoid data subdivision unit 3326 Output band buffer 34 Intermediate data optimization unit 35 Intermediate data reconstruction unit 36 Parallel processing determination unit 361 Input object buffer 362 Overlap Judgment unit 363 Configuration data addition unit 364 Output object buffer 40 Reconfigurable development unit 41 Reconfiguration control unit 410 Memory unit 411 Configuration code storage area 412 Control unit 413 Read control unit 414 Addition / update unit 415 Conversion table 42 Configuration data management unit 420 input buffer A 421 input buffer B 422 band buffer A 423 band buffer B 424 work area 43 intermediate data transfer control unit 44 print data transfer control unit 45 arbitrage Section 46 Reconstruction hardware section 460, 460-1, 460-2 Code A processing circuit 461 Trapezoid drawing circuit 462 Screen processing circuit 463 Intermediate data input section 464 Coordinate calculation section A 465 Coordinate calculation section B 466 Edge drawing section 467 DDA Parameter calculation section 468 DDA processing section 469 Coordinate update section 47 Refresh control section 470 Address calculation section 471 Mask calculation section 472 Data calculation section 473 RmodW processing section 480, 480-1, 480-2, 480-3 Co
de G processing circuit 481 Image decompression circuit 481-1 Intermediate data input section 481-2 Huffman decoding section 481-3 Inverse quantization section 481-4 Inverse DCT section 481-5 Writing section 482 Resolution conversion circuit 482-1 Pixel data Input section 482-2 Interpolation processing section 482-3 Pixel address calculation section 482-4 Writing section 483 Color conversion circuit 483-1 Pixel data input section 483-2 Table conversion section 483-3 Interpolation processing section 483-4 Writing section 484 Trapezoid Drawing circuit 485 Screen processing circuit 50 Video interface 51 Semiconductor laser scanning device 510 Polygon mirror 511 Lens 52 Photoreceptor drum 53 Charger 54 Rotary developing device 55 Transfer drum 56 Cleaner 57 Fixing device 58 Paper transport path 900 Band area 901 Graphic object DOO 902 image object 902 graphic object 903 image object

Continued on the front page (72) Inventor Takashi Nagao 430 Nakai-cho, Nakai-machi, Ashigarashimo-gun, Kanagawa Prefecture Inside Fuji Xerox Fuji Xerox Co., Ltd. 72) Inventor Kazuki Hirata, 430 Green Tech Nakai, Sakai-Nami, Kanagawa Prefecture Fuji Xerox Fuji Xerox Co., Ltd. (72) Inventor Yoshinori Wada 430 Green Tech Nakai, Sakai Nakagami-cho, Kanagawa Prefecture, Fuji Xerox Co., Ltd. 430 Nakai-cho, Nakai-machi, Ashigara-gun, Kanagawa Prefecture Green Tech Nakai Fuji Xerox Co., Ltd. (56) References JP-A-5-324930 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) B41J 5 / 30 G06F 3/12

Claims (20)

(57) [Claims] 1. Developing first print data described by a predetermined drawing command, which represents at least one of a character, a graphic, and an image drawing element, into second print data of an image output data structure; in the print processing apparatus that performs image output based on the second print data, a logic circuit device including a switching means for controlling the flow of input data and output data of a plurality of logical blocks and the plurality of logical blocks , can be set according to at least one configuration data switching aspects of the function and the switching means of the logic blocks, said logic circuitry to change the configuration data according to the logic circuit configuration information <br/> paper a logic circuit device for expanding the first print data into the second print data with a logic circuit configuration corresponding to information; and an input means for inputting the first print data. A step, a judging means for judging an overlap of drawing elements included in the first print data inputted to the input means, and at least judgment information of the judging means and the first print data inputted to the input means. Based on the contents, the drawing elements of the first print data input to the input means are rearranged, and further converted into print data of a predetermined format including the logic circuit configuration information and supplied to the logic circuit device. e Bei means, and output means for outputting an image based on the second print data developed by the logic device, the logic device is contained in the print data of the predetermined format
The logic circuit configuration corresponding to the logic circuit configuration information
Format print data into the second print data.
And a print processing apparatus. 2. The rearrangement of drawing elements in the conversion means is performed so that drawing elements which can be developed in parallel by the logic circuit device are continuous.
The print processing apparatus according to the above. 3. The parallel development by the logic circuit device is as follows.
3. The print processing apparatus according to claim 2, wherein the print processing is performed by a logical circuit configuration set to include a plurality of the same or different functional blocks. 4. The method according to claim 1, wherein the rearrangement of the drawing elements in the conversion unit is performed so that the number of times of changing the configuration data of the logic circuit device is reduced.
Or the print processing apparatus according to 3. 5. The print processing apparatus according to claim 1, wherein the conversion unit does not rearrange the order of the drawing elements determined to be overlapped by the determination unit. . 6. The print processing apparatus according to claim 5, wherein the determination unit determines the overlap using a circumscribed rectangle including the drawing element. 7. The method according to claim 1, wherein said converting means removes an overlap between the drawing elements determined to have an overlap by said determining means, and then rearranges the order.
5. The print processing apparatus according to 2, 3, or 4. 8. The method according to claim 1, wherein the reordering of the drawing elements is performed for each page or for each band obtained by dividing the page into a plurality of scan lines.
The print processing apparatus according to 5, 6, or 7. 9. The print processing apparatus according to claim 1, wherein the logic circuit device can change the configuration of the logic circuit entirely or partially. 10. The logic circuit device according to claim 1, wherein the change of the configuration data is omitted when the logic circuit configuration information included in the print data of the predetermined format inputted one after another is the same. The print processing apparatus according to claim 1. 11. The print processing apparatus according to claim 1, wherein the logic circuit device includes at least a field programmable gate array. 12. The print processing apparatus according to claim 1, wherein the logic circuit device includes a plurality of arithmetic processing devices, and switching means for switching a flow of input data and an output data of the plurality of arithmetic processing devices. 13. The conversion means, and a switching means for controlling the flow of input data and output data of a plurality of logical blocks <br/> and the plurality of logical blocks, the logical Bed
Logic circuit capable of setting at least one of a lock function and a switching mode of the switching unit according to configuration data
2. The print processing apparatus according to claim 1, further comprising an apparatus , wherein at least a part of the processing of the conversion unit is executed by the logic circuit device in the conversion unit. 14. The print processing apparatus according to claim 1, wherein the logic circuit device is set so that a plurality of functional blocks are expanded by performing a pipeline operation. 15. A first description described by a predetermined drawing command, which represents at least one of a drawing element of a character, a graphic, and an image.
The print data expanded into the second print data of the image output data structure, the print processing apparatus that performs image output based on the second print data, input of a plurality of logical blocks and the plurality of logical blocks a logic circuit device comprising a switching means for controlling the data and flow of output data, can be set according to at least one configuration data switching aspects of the function and the switching means of said logic block, logic circuitry logic for developing the first print data to the second print data in the logic circuit configuration corresponding to the logic circuitry <br/> information by changing the configuration data in response to information <br/> report a device, input means for inputting the first print data, judging means for judging overlap of drawing elements included in the first print data input to the input means, Based on the content of the first print data input to the determination information and said input means of said determination means even without, the first print data input to the input means, said logic circuit
The theory is converted into print data of a predetermined format containing the configuration information
E Bei converting means for supplying sense circuit device, and output means for outputting an image based on the second print data developed by the logic device, the logic device is contained in the print data of the predetermined format Re
The logic circuit configuration corresponding to the logic circuit configuration information
Format print data into the second print data.
And a print processing apparatus. 16. The conversion means, logical to expand the print data including a plurality of drawing elements successive it is determined that there is no overlap by the determining means, the plurality of drawing elements in parallel
Print processing apparatus according to claim 15, wherein the converting the format including logic circuitry information specifying the physical circuit configuration. 17. The print processing apparatus according to claim 16, wherein the parallel development of the drawing elements is performed by a logic circuit configuration including a plurality of the same or different functional blocks. 18. A first method which is described by a predetermined drawing command and represents at least one of a character, a figure, and a drawing element of an image.
The print data expanded into the second print data of the image output data structure, the print processing apparatus that performs image output based on the second print data, input of a plurality of logical blocks and the plurality of logical blocks and switching means for controlling the data and flow of output data a including logic device, it can be set according to at least one configuration data switching aspects of the function and the switching means of said logic block, logic circuit logic for developing the first print data in a logic circuit configuration corresponding to the logic circuitry <br/> information by changing the configuration data in accordance with the configuration information <br/> report to the second print data A circuit device ; input means for inputting the first print data; and a logic circuit structure corresponding to the content of the first print data. E Bei converting means supplied to the logic circuit unit converts the print data of a predetermined format including forming information, and output means for outputting an image based on the second print data developed by the logic circuit the logic device is included in the print data of the predetermined format
The logic circuit configuration corresponding to the logic circuit configuration information
Format print data is expanded into the second print data, and the conversion means can be expanded in parallel by the logic circuit device
Rearrange the above drawing elements so that various drawing elements are continuous
A print processing apparatus characterized by the above-mentioned . 19. A method for drawing at least characters, figures, and images.
A first one described by a predetermined drawing command
Print data of the image output data structure 2 printing data
Data based on the second print data.
In a print processing device that performs force, Input data of multiple logical blocks and the multiple logical blocks
Switching means for controlling the flow of data and output data;
A logic circuit device including the function of the logic block
And at least one of the switching modes of the switching means.
Can be set according to the configuration data.
The above configuration data is changed according to the
The first print data is stored in a logic circuit configuration corresponding to the information.
A logic circuit device for developing the second print data; Input means for inputting the first print data; The first print data input to the input means is
1 includes the logic circuit configuration information corresponding to the content of the print data.
And converts it to print data of a predetermined format and
Converting means for supplying; Based on the second print data developed by the logic circuit device,
Output means for outputting an image The logic circuit device is included in the print data of the predetermined format.
The logic circuit configuration corresponding to the logic circuit configuration information
Format print data into the second print data, The above-mentioned conversion means is used so that drawing elements of the same type are
Print processing apparatus for rearranging drawing elements
Place. 20. The conversion means, in response to the logic circuit configuration information <br/> paper, print processing apparatus according to claim 18, wherein omitting the logic circuit configuration information in the converted data .