JP3125130B2 - Data playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus applied to a PCM data recording / reproducing apparatus, for example, a mini disk.

[0002]

2. Description of the Related Art A conventional example of a data reproducing apparatus according to the present invention will be described by taking a mini disk system as an example.

In a mini disc system, data is reproduced intermittently and at high speed from an optical disc on which audio data is recorded, and when data is sufficiently stored in a buffer memory, reproduction is temporarily disabled by vibration or the like. Even so, the data stored in the buffer memory can be used to reproduce sound without interruption, so that it is suitable for a portable player.

[0004] In the case of a portable player, since it is driven by a battery, it is important to reduce the power consumption of the consuming parts of the player and extend the battery life.

As a technique for reducing the power consumption of the mini disk system, there is a technique described in Japanese Patent Application Laid-Open No. 5-342585 entitled "Information Reproducing Apparatus".

According to this conventional example, when the data storage amount of the buffer memory exceeds a predetermined value, the power consumption of the pickup, the RF amplifier, the signal processing circuit, the servo circuit, the driver circuit, and the like is cut off to thereby reduce the consumption. Techniques for reducing power are disclosed.

[0007]

However, in the above conventional example, after the power supply to each block is started,
It takes time to start the motor, lock the servo, etc. until the effective data can be stored in the buffer memory.
It is not possible to reproduce data in small units, and the data stored in the buffer memory is periodically reduced significantly.
There was a problem that the seismic performance of the buffer memory was reduced.

For this reason, the conventional example has two modes, a power save mode and a seismic performance priority mode.

Further, in the above-mentioned conventional example, since the power supply is cut off to reduce the power consumption, a switch is required in the power supply path. If a relay or the like is used, the mounting area becomes large, and a semiconductor switch such as a transistor is used. However, there is a problem that power loss of the switch itself occurs when the switch is used.

The present invention solves the above problems,
It is an object of the present invention to provide a data reproducing apparatus capable of reducing both power consumption and seismic performance.

[0011]

In order to achieve the above object, a data reproducing apparatus according to the present invention demodulates a reproduction signal reproduced from a recording medium and writes the demodulated data into a first memory. A demodulation unit; an error correction unit that corrects an error of data written to the first memory;
A first data reading unit that reads data from the memory and transfers the data to the second memory; a second data reading unit that reads data from the second memory; and a data reading unit that reads data stored in the second memory. A data amount determining unit for determining an amount, based on a determination result of the data amount determining unit, when the data stored in the second memory becomes equal to or greater than a first predetermined value, the error correcting unit The supply of the clock to the first data reading unit is stopped, and the amount of data stored in the second memory becomes equal to or less than a second predetermined value set lower than the first predetermined value. After that, a clock generation unit that starts supplying a clock to the error correction unit and the first data reading unit, and prohibits a block to which the clock generation unit has stopped supplying a clock from accessing the first memory. Do Includes a stem control unit, said first memory and said second memory, characterized in that structure and the using two regions on a single memory.

A demodulation unit for demodulating a reproduction signal reproduced from a recording medium and writing the demodulated data in a first memory; and an error correction unit for correcting an error in the data written in the first memory. A first data reading unit that reads data from the first memory and transfers the data to a second memory; and a second data reading unit that reads data from the second memory.
A data readout unit, a data amount determination unit that determines the amount of data stored in the second memory, and data stored in the second memory based on the determination result of the data amount determination unit. When the value becomes equal to or more than a first predetermined value, the supply of the clock to the error correction unit and the first data reading unit is stopped, and the amount of data stored in the second memory is reduced to a first predetermined value. When the value becomes equal to or less than a second predetermined value which is set lower than the value, the clock supply to the error correction unit is started, and after a predetermined time, the clock supply to the first data reading unit is started. And a system control unit that prohibits a block to which the clock generation unit has stopped supplying a clock from accessing the first memory, wherein the first memory and the second memory are One memory Wherein the structure and the using two regions of.

[0013]

According to the above configuration, while the data storage amount of the shock proof memory is almost full, access to the correction memory of the demodulation unit, the error correction unit, and the data reading unit can be stopped. Power consumption can be reduced without using an element having a large power loss such as a power cutoff switch. In addition, since power consumption is reduced by on / off processing of memory access, the overhead at the time of switching is small, the switching can be switched on / off frequently, and the data storage amount of the shock-proof memory is almost full. , So that seismic performance is not reduced.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a mini disk system showing a reference example for explaining an embodiment of a data reproducing apparatus according to the present invention, wherein 1 is a disk which is a magneto-optical disk or an optical disk, 2 is a spindle motor, Is a driver, 4 is a spindle servo unit, 5 is an optical head, 6 is a driver, 7 is an optical servo unit, 8 is a reproduction amplifier, 10 is a demodulation unit, 20 is an error correction / encoding unit, 21 is a correction memory, and 30 is a correction memory. Decoder / encoder section, 40 is a shock proof memory, 42 is a data amount determination section, 50 is a system control section, 60 is a compression / expansion section, 61 is an ADC, 62 is a DAC, 70 is a modulation section, 71 is a driver, 72 Indicates a magnetic head.

The spindle motor 2 is driven by a spindle servo unit 4 via a driver 3. The signal recorded on the disk 1 is read by the optical head 5. The optical head 5 is driven by an optical servo unit 7 via a driver 6. The reproduction amplifier 8 is an optical head 5
A current-voltage conversion is performed on the reproduced signal reproduced in step (1), the waveform is equalized, and the resulting signal is supplied to the demodulation unit 10. Further, the reproducing amplifier 8 converts the signal reproduced by the optical head 5 (address implement groove) from current to voltage and supplies the signal to the demodulation unit 10. The configuration of the mini-disc system and the method of separating the reproduction signal and the ADIP signal from the optical head are described in Nikkei Electronics Magazine No. 535, 1991.9.2, pp. 127-141.

When the system control unit 50 instructs demodulation, the demodulation unit 10 extracts a clock from the reproduction signal supplied from the reproduction amplifier 8, detects data using the extracted clock, and performs EFM (8-14 modulation). The demodulated data is demodulated.
The extraction of the clock is realized by a PLL (Phase Locked Loop) circuit. After that, the demodulation unit 10 detects the frame synchronization signal and writes the demodulated data to the correction memory 21.

The demodulation unit 10 supplies the frame clock (about 7.35 kHz) detected at the time of demodulation to the spindle servo unit 4. The frame clock is a clock having the same frequency as the reproduced frame, and is generated by the demodulation unit 10 based on the frame synchronization signal.

The demodulation unit 10 demodulates the ADIP signal recorded on the magneto-optical disk, generates a bit clock, supplies the bit clock to the spindle servo unit 4, and outputs the bit clock.
An address signal recorded in the IP is detected and sent to the system control unit 50. The spindle servo unit 4 controls the number of rotations of the disk with the frame clock supplied from the demodulation unit 10 during reproduction of the optical disk.

The spindle servo section 4 controls the number of rotations of the magneto-optical disk during reproduction or recording by the bit clock of the ADIP signal generated by the demodulation section.

The error correction / encoding unit 20 includes a system control unit 50
Indicates an error, the data stored in the correction memory 21 is read, and the error is detected and corrected.
Write back to 21.

The error correction / encoding unit 20 operates when the system control unit 50 instructs error correction encoding.
The data stored in the memory 21 is read, an error correction code is generated, and the error correction code is written in the correction memory 21.

The error correction / encoding unit 20 is constituted by a microprocessor.

When the system control unit 50 instructs decoding, the decoder / encoder unit 30 (second data reading unit) detects a synchronizing signal from the data stored in the correction memory 21, de-scrambles the data, and releases the shock signal. Transfer to proof memory 40. Decoder / encoder unit 30
Reproduces the address data recorded after the synchronization signal and sends it to the system control unit 50.

When the system control unit 50 instructs the encoding, the decoder / encoder 30
Data is read from the proof memory 40, scrambled, a synchronization signal is added, and the data is written to the correction memory 21. The shock proof memory 40 includes a first-in first-out memory, and outputs a currently stored data amount.

When the data amount reaches the upper limit of the memory capacity based on the data amount stored in the shock proof memory 40, the data amount determination unit 42
The flag MF is set, and the data amount becomes (the upper limit of the memory capacity−
4 sectors) or less, memory full flag MF
Cancel.

Further, the data amount determination unit 42 is based on the data amount information transmitted from the shock proof memory 40,
When the data amount reaches 0, the memory empty flag ME is set, and when the data amount exceeds 4 sectors, the memory empty flag ME is released.

The system control unit 50 controls the data amount determination unit 4 according to the system mode (recording mode or reproduction mode).
2, the optical servo unit 7, the spindle servo unit 4, the demodulation unit 10, the modulation unit 70, the error correction / encoding unit 20, and the decoder based on the memory full flag MF supplied from 2 and the memory empty flag ME. -Control the encoder unit 30 and the compression / expansion unit 60.

The compression / expansion unit 60 (second data reading unit / data writing unit) reads data from the shock proof memory 40 at a constant rate when the system control unit 50 instructs the reproduction mode, and compresses the data. Decompress audio data. As a result, 16-bit data for two channels is output at a rate of 44.1 kHz for each channel. This data is output as an audio output signal for two channels via a DAC (digital-analog converter) 62.

An ADC (analog-to-digital converter) 61 performs an analog-to-digital conversion of the input voice input signal. As a result, 16-bit data for two channels is supplied to the compression / decompression unit 60 at a rate of 44.1 kHz for each channel. When the system control unit 50 instructs the recording mode, the compression / expansion unit 60 compresses the audio data supplied from the ADC 61 using ATRAC (Advanced Transform Coding). The data compressed by the compression / expansion unit 60 is written to the shock proof memory 40 at a constant rate.

When the system control unit 50 instructs the modulation, the modulation unit 70 reads out the data stored in the correction memory 21, modulates the data by 8-14, adds a frame SYNC to generate a recording signal, and generates a recording signal. To supply.

The magnetic head 72 is driven by the driver 71 when the system control unit 50 instructs recording.

Next, the operation will be described.

FIG. 2 shows the operation of the reference example of the data reproducing apparatus shown in FIG. 1 in the reproducing mode.

In FIG. 2, MS indicates the data storage state of the shock proof memory 40, full on the vertical axis indicates the state where the shock proof memory 40 is full, and (full-M) indicates the shock proof memory. State when the free space of the proof memory 40 is M (M = 4) sectors, (Empty +
N) indicates a state in which data for N (N = 4) sectors is stored in the shock proof memory 40. Empty indicates that the shock proof memory 40 is empty.

MF is a memory full flag sent by the data amount judgment unit 42. The data amount judgment unit 42
When the amount of data stored in the proof memory 40 becomes full, the memory full flag MF is set, and when the free space of the shock proof memory 40 becomes M (M = 4) sectors, the memory・ Clear the full flag MF. Note that the horizontal axis indicates the passage of time.

When the shock proof memory 40 starts playing at a constant rate X from the empty state at time A, the shock proof memory 40 becomes full at time B. During this time, the system control unit 50 sets the flag DEMAEN for permitting the demodulation unit 10 to access the correction memory 21, the error correction / encoding unit 20
ECCAEN, which permits access to the correction memory 21 of the
The flag CDRAEN that permits access to the correction memory 21 of the decoder / encoder unit 30 is turned on. When the memory full flag MF is turned on at time B, the system control unit 50 sets the demodulation unit 10, the error correction / encoding unit 20, the decoder
Access to the correction memory 21 of the encoder unit 30 is prohibited. That is, the flags DEMAEN, ECCAEN, and CDRAEN are turned off.

At time B, the system control unit 50 prohibits the demodulation unit 10 from accessing the correction memory 21 and then instructs the optical servo unit 7 to perform a track jump to the next sector. Normally, access to the sector next to the sector fetched into the correction memory 21 by time B is instructed. When the access is completed, the tracking signal TRON supplied from the optical servo unit 7 to the system control unit 50 turns on.

Thereafter, no data is written to the shock proof memory 40 until time C.
The compression / expansion unit 60 reads data from the shock proof memory 40 at a rate of X / 5.

Next, at time C, when the data amount of the shock proof memory 40 becomes (full-M), the system controller
50 turns on the flags DEMAEN, ECCAEN, and CDRAEN.

Next, the system control unit 50 controls the ADIP address sent from the demodulation unit 10 and the decoder / encoder unit 30.
After confirming that the address data transmitted from the address is the address indicating the sector immediately before the sector to be captured next, a data transfer instruction (SPMWEN) is issued to the decoder / encoder unit 30 at time D, and the shock proof is issued.・ Memory 40
To transfer data to

Next, when the memory full flag MF is turned on at time E, access to the correction memory 21 of the demodulation unit 10, the error correction / encoding unit 20, and the decoder / encoder unit 30 is prohibited.

Thereafter, the system control unit 50 repeats the same processing as that from time B to time E.

Here, during the period from time B to time C, the demodulation unit
10, error correction / encoding unit 20, decoder / encoder unit 30
Access to the correction memory 21 of
During this time, the error correction / encoding unit 20 and the decoder / encoder unit 30 may not only prohibit access to the correction memory 21 but also stop the processing.

The error correcting / encoding unit 20 constituted by a microprocessor can stop the processing by stopping a program counter, for example.
Further, the decoder / encoder unit 30 detects a synchronization signal,
The processing can be stopped by stopping the sequencer that manages the timing of the scramble processing or the like.

The demodulation unit 10 needs to supply a frame clock or an ADIP bit clock detected at the time of demodulation to the spindle servo unit 4. 4
Since the operation becomes unstable, access to the correction memory 21 is only prohibited. However, the operation can be temporarily stopped after the access of a new sector by the optical servo unit 7 is completed. In this case, it is necessary to take measures such as holding the spindle servo so that tracking is performed immediately when data reading becomes necessary.

As described above, the shock-proof memory
According to the amount of data stored in 40, the correction memory of the demodulation unit 10, the error correction / encoding unit 20, and the decoder / encoder unit 30
By prohibiting the access to the correction memory 21, it is possible to eliminate the power consumption caused by the access to the correction memory 21 between the time B and the time C in FIG.

In particular, the correction memory 21 is an IC different from the demodulation unit 10, the error correction / encoding unit 20, and the decoder / encoder unit 30.
(Integrated circuit), the power consumption is higher than the access to the memory in the integrated circuit.
Reducing the rate of access to 21 has a significant effect on reducing power consumption (generally, signal transmission between different integrated circuits requires a large current to flow due to the long signal path).

Next, a first embodiment of the data reproducing apparatus of the present invention will be described with reference to the drawings.

The configuration of the data reproducing apparatus according to the first embodiment of the present invention will be described.

The first embodiment of the present invention has the following two features.

(1) When the shock proof memory 40 is full, the master clock supplied to the error correction / encoding unit 20 and the decoder / encoder unit 30 is stopped to reduce power consumption in this part. I do.

(2) Access is prohibited so that unnecessary access to the correction memory 21 does not occur when the clock is stopped.

FIG. 3 is a block diagram showing the configuration of the first embodiment of the data reproducing apparatus of the present invention. Reference numeral 51 denotes a clock generator, and the other components are the same as in the reference example shown in FIG. .

In the first embodiment of the present invention, the correction memory 21
And the shock-proof memory 40 are shared, and access is made in a time-division manner using two areas on the same memory.

In FIG. 3, when the system control unit 50 enables the clock-on flag CKON, the clock generation unit 51 and the error correction / encoding unit 20 and the decoder / encoder unit
Supply clock to 30 and stop it when CKON is invalid. The system control unit 50 controls access to the correction memory 21 of the demodulation unit 10 and the error correction / encoding unit 20 based on the data amount information output from the data amount determination unit 42, and sends a clock to the clock generation unit 51.・ Supply the ON flag CKON.

FIG. 4 is a block diagram showing the configuration of the error correction / encoding unit 20. In FIG. 4, reference numeral 80 denotes an error correction / encoding circuit that executes error correction processing or error correction / encoding processing together with the master clock ECCMCK supplied from the clock generation unit 51. 81 is an error correction / encoding circuit
An AND gate 89 (AND) gates the correction memory access request signal sent from the device 80 with the error correction encoder access permission signal ECCAEN supplied from the system controller 50. When ECCAEN is off, access to the correction memory 21 is prohibited. Therefore, even if the master clock ECCMCK stops, access to the correction memory 21 is forcibly prohibited if ECCAEN is off.

Next, the operation of the first embodiment of the data reproducing apparatus of the present invention will be described.

FIG. 5 shows the operation of the data reproducing apparatus of the first embodiment in the reproducing mode.

In FIG. 5, the clock-on flag CK
Except for ON, the operation is the same as that of the reference example shown in FIG. In FIG. 5, the system control unit 50 sends out to the clock generation unit 51 by the clock-on flag CKON.
When the clock-on flag CKON is on, the clock generation unit 51 supplies a clock to the error correction / encoding unit 20 and the decoder / encoder unit 30, and the clock-on flag CKON
Is off, the clock generation unit 51 outputs the error correction / encoding unit.
The supply of the clock to 20 and the decoder / encoder unit 30 is stopped. The system control unit 50 turns on the clock-on flag CKON when ECCAEN and CDRAEN are on. Therefore, the clock-on flag CKON is set when the memory full flag MF is off, that is, when the shock proof memory 40 is not full (the period from time A to time B and from time C to time E). ), And when the memory full flag MF is on, that is, when the shock proof memory 40 is full (period B to time C), it is off. Thereafter, the system control unit 50 repeats the same processing as that from time B to time E.

As described above, according to the second embodiment of the present invention,
When the shock proof memory 40 is full, the clock supply to the error correction / encoding unit 20 and the decoder / encoder unit 30 can be stopped, and the access to the correction memory 21 can be stopped. Can be greatly reduced.

Next, a second embodiment of the data reproducing apparatus of the present invention will be described with reference to the drawings.

The configuration of a second embodiment of the data reproducing apparatus according to the present invention will be described. The features of the second embodiment of the present invention are as follows.

When the shock proof memory 40 is full, the demodulator 10, the error correction / encoder 20, the decoder
Access to the correction memory 21 of the encoder unit 30 is prohibited,
The amount of data in the shock proof memory 40 becomes (full-4
(Sectors), the access to the correction memory 21 of the demodulation unit 10 is first permitted, and then the data (approximately 1.1 sectors) sufficient for error correction processing is stored. 20, correction memory of decoder / encoder section 30
Allow access to 21.

FIG. 6 is a block diagram showing the configuration of the second embodiment of the present invention. Reference numeral 52 denotes a delay circuit. 6, the configuration other than the delay circuit 52 is the same as that of the first embodiment of the present invention shown in FIG.

In FIG. 6, a delay circuit 52 is a memory access permission signal of the demodulation unit 10 supplied from the system control unit 50.
The rising edge of DEMAEN is delayed for a certain time, and the falling edge is not changed.

FIG. 7 shows the operation in the reproducing mode of the second embodiment of the data reproducing apparatus of the present invention.

In FIG. 7, the data of the present invention except for a flag ECCAEN for permitting the error correction / encoding unit 20 to access the correction memory 21 and a flag CDRAEN for permitting the decoder / encoder unit 30 to access the correction memory 21. Since the operation of the first embodiment of the reproducing apparatus is the same as that of FIG. 5, the description is omitted. In FIG. 7, ECCAEN and CDRAEN are a delay circuit that sets a flag DEMAEN that permits access to the correction memory 21 of the demodulation unit 10.
This is a signal in which only the rising edge is delayed by 52. When DEMAEN rises at point C, ECCAEN and CDRAEN
It rises at the point L with a certain delay. From time C to time L
In the meantime, about 1.1 sectors of data are stored in the correction memory 21, and data sufficient for error correction processing is prepared in the time L. Since ECCAEN and CDRAEN rise after time L, error correction and decoding are performed. In addition, the error correction code of the mini-disc is 108 error correction codes at the maximum.
Since a frame (approximately 1.1 sectors, one sector is 98 frames) is completed, error correction processing cannot be started unless data for 108 frames is stored in advance. Thereafter, the system control unit 50 repeats the same processing as that from time B to time E.

As described above, according to the second embodiment of the data reproducing apparatus of the present invention, the data necessary for error correction is stored in the correction memory 21 in accordance with the amount of data stored in the shock proof memory 40. Error correction / encoding unit 20,
The error correction / encoding unit 20 and the decoder / encoder unit are started by accessing the correction memory 21.
Access to the 30 correction memories 21 can be prohibited to the maximum, and power consumption caused by accessing the correction memory 21 can be greatly reduced.

[0070]

As described above, according to the data reproducing apparatus of the present invention, when the data storage amount of the second memory becomes equal to or more than a predetermined value, the operation clock of the error correction unit and the first data reading unit is supplied. At the same time, prohibits access to the first memory by the block to which the clock supply of the error correction unit, the first data reading unit, and the like is stopped, and the data storage amount of the second memory becomes equal to or less than a predetermined value. Supply of the operation clock of the error correction unit and the data read unit is started,
By starting the processing including the memory access, the power consumption can be further reduced while maintaining the seismic performance.

Further, according to the data reproducing apparatus of the present invention, after the data necessary for error correction is stored in the first memory according to the amount of data stored in the second memory,
By starting access to the encoding unit and the first memory, it is possible to prohibit the error correction encoding unit and the decoder / encoder unit from accessing the first memory as much as possible. The power consumption caused by accessing the memory can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a reference example for explaining a data reproducing apparatus of the present invention.

FIG. 2 is a timing chart showing the operation of the reference example shown in FIG.

FIG. 3 is a block diagram showing a configuration of a first embodiment of the data reproducing apparatus of the present invention.

FIG. 4 is a block diagram illustrating a configuration of an error correction encoding unit according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the first embodiment of the data reproducing apparatus of the present invention.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the data reproducing apparatus of the present invention.

FIG. 7 is a timing chart showing the operation of the second embodiment of the data reproducing apparatus of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Disk, 20 ... Error correction / coding part, 21 ... Correction memory, 30 ... Decoder / encoder part, 40 ... Shock proof memory, 42 ... Data amount determination part, 50 ... System control part, 51 ... Clock generation Unit, 52 delay circuit, 60 compression / expansion unit, 70 modulation unit, 80 error correction coding circuit, 81 AND gate (AND).

Claims (2)

(57) [Claims] 1. A demodulation section for demodulating a reproduction signal reproduced from a recording medium and writing the demodulated data to a first memory, and performing error correction on the data written to the first memory.
Cormorant an error correction unit, a first data reading unit for transferring from the previous SL first memory to the second memory reads the data, and the previous SL second data reading section for reading data from the second memory, before Symbol determines the data amount determination unit amount of data stored in the second memory, before SL on the basis of the data amount determination unit of the judgment result, pre Symbol data is first to be stored in the second memory The error correction unit and the first data reading unit when the value becomes a predetermined value or more;
Stops supplying the clock to, after the previous SL amount of data stored in the second memory is equal to or less than a second predetermined value which is set lower than the first predetermined value, the error correction Department and front
The clock supply to the first data reading unit is started.
A clock generator and a block to which the clock generator has stopped supplying a clock.
E Bei system control unit which prohibits access to the first memory of the click, the said first memory said second memory in a single memory
Data reproducing apparatus characterized by constituting the. Wherein demodulating the reproduction signal reproduced from the recording medium, error correction performed and the demodulation unit for writing the demodulated data to the first memory, the error correction of the data written in the previous SL first memory and parts, before Symbol a first data reading unit for transferring the second memory reads the data from the first memory, the previous SL second data reading section for reading data from the second memory, before Symbol first and determining the data amount determination unit amount of data stored in the second memory, before SL on the basis of the data amount determination unit of the judgment result, before Symbol data stored in the second memory is a first predetermined value when it becomes more, before Symbol error correction unit before Symbol stop the clock supply to the first data reading unit, the amount of data stored in the previous SL second memory, than the first predetermined value Is also less than a second predetermined value set low , To the error correction unit
Clock supply, and after a certain time, the first clock
Clock that starts supplying the clock to the
A clock generation unit, and the clock generation unit supplies a clock.
Prohibit access of the stopped memory to the first memory
A system control unit for stopping the first memory and the second memory in one memory
A data reproducing apparatus having a configuration using the above two areas .