JP3123707B2 - Solder bump formation method, solder bump connection method and pressure jig - Google Patents

Solder bump formation method, solder bump connection method and pressure jig

Info

Publication number
JP3123707B2
JP3123707B2 JP09029952A JP2995297A JP3123707B2 JP 3123707 B2 JP3123707 B2 JP 3123707B2 JP 09029952 A JP09029952 A JP 09029952A JP 2995297 A JP2995297 A JP 2995297A JP 3123707 B2 JP3123707 B2 JP 3123707B2
Authority
JP
Japan
Prior art keywords
solder
semiconductor chip
chip
bump
solder bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP09029952A
Other languages
Japanese (ja)
Other versions
JPH10229087A (en
Inventor
秀起 恒次
正風 細矢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP09029952A priority Critical patent/JP3123707B2/en
Publication of JPH10229087A publication Critical patent/JPH10229087A/en
Application granted granted Critical
Publication of JP3123707B2 publication Critical patent/JP3123707B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301Bonding head
    • H01L2224/75314Auxiliary members on the pressing surface
    • H01L2224/75315Elastomer inlay
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301Bonding head
    • H01L2224/75314Auxiliary members on the pressing surface
    • H01L2224/75315Elastomer inlay
    • H01L2224/75316Elastomer inlay with retaining mechanisms
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3489Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高精度で高密度な
端子接続が可能で、しかも確実にはんだバンプを形成す
ることができるはんだバンプの形成方法,はんだバンプ
の接続方法および加圧治具に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a solder bump, a method of connecting a solder bump, and a pressing jig, which enable high-precision and high-density terminal connection and can form a solder bump reliably. It is about.

【0002】[0002]

【従来の技術】従来の半導体チップと配線基板との高密
度な端子接続法としてはフリップチップ法が一般的に知
られており(文献例:半導体実装技術ハンドブック,株
式会社サイエンスフォーラム社発行)、直径100μm
程度のはんだバンプを用いて接続することにより、半導
体チップ全面からの端子取り出しが可能なため高密度な
接続が可能で、しかも、接続長が短いことから接続部の
浮遊容量や寄生インダクタンスを極力低減することがで
きるため、高速LSIの端子接続法としても重要な技術
になってきている。
2. Description of the Related Art As a conventional high-density terminal connection method between a semiconductor chip and a wiring board, a flip-chip method is generally known (reference example: Handbook for Semiconductor Packaging Technology, published by Science Forum Co., Ltd.). 100μm diameter
By using solder bumps of the appropriate degree, terminals can be taken out from the entire surface of the semiconductor chip, enabling high-density connections. In addition, the short connection length minimizes stray capacitance and parasitic inductance at the connection. Therefore, it is becoming an important technology as a terminal connection method for a high-speed LSI.

【0003】しかしながら、従来のフリップチップ法で
は、半導体基板に半導体素子等を形成した後、電極端子
上に直接はんだ層を形成する工程が必要であるため、工
程が複雑で歩留りが悪く、生産性に劣るという問題があ
った。このため、多数のはんだバンプをキャリア基板上
に形成しておき、前記はんだバンプを半導体素子の電極
上に転写し、基板にフリップチップ接続する方法が考案
されている(特開平5−166880号公報)。この方
法の概略工程を図9に示す。
However, the conventional flip-chip method requires a process of forming a semiconductor element or the like on a semiconductor substrate and then directly forming a solder layer on an electrode terminal, so that the process is complicated, yield is low, and productivity is low. There was a problem that it was inferior. For this reason, a method has been devised in which a large number of solder bumps are formed on a carrier substrate, the solder bumps are transferred onto the electrodes of a semiconductor element, and flip-chip connected to the substrate (Japanese Patent Laid-Open No. Hei 5-166880). ). FIG. 9 shows schematic steps of this method.

【0004】図9において、はんだの濡れ性に劣る転写
用キャリアチップ1上にドット状のはんだ層2をパター
ン形成した後(a)、前記転写用キャリアチップ1を半
導体チップ3の電極4上に位置合わせし(b)、はんだ
を溶融することにより、転写用キャリアチップ1上のは
んだ層2を半導体チップ3の電極4上に転写し、はんだ
バンプ5を形成する(c)。さらに、前記半導体チップ
3を配線基板6上の電極7に位置合わせし(d)、はん
だバンプ5をリフロすることによりフリップチップ接続
する(e)方法である。
In FIG. 9, after a dot-shaped solder layer 2 is patterned on a transfer carrier chip 1 having poor solder wettability (a), the transfer carrier chip 1 is placed on the electrodes 4 of the semiconductor chip 3. By aligning (b) and melting the solder, the solder layer 2 on the transfer carrier chip 1 is transferred onto the electrodes 4 of the semiconductor chip 3 to form solder bumps 5 (c). Further, the method is such that the semiconductor chip 3 is aligned with the electrodes 7 on the wiring board 6 (d), and the solder bumps 5 are reflowed to perform flip-chip connection (e).

【0005】また、転写用キャリアチップ1上のはんだ
層2を半導体チップ3の電極4上に転写する工程におい
て、半導体チップ3の厚さのばらつきや加圧軸の傾きが
あった場合においてもはんだ層2の転写が確実に行える
ことをねらいとして、図10に示すように、凸形状の曲
面からなる先端部を有する加圧治具8で転写用キャリア
チップ1と半導体チップ3を加圧する方法が考案されて
いる。さらに、図11に示すように、前記半導体チップ
3を配線基板6上にフリップチップ接続する工程におい
ても、前記の転写の工程と同様に、凸形状の加圧治具8
で半導体チップ3と配線基板6を加圧する方法が考案さ
れている(特願平8−254311号)。
In the step of transferring the solder layer 2 on the transfer carrier chip 1 onto the electrodes 4 of the semiconductor chip 3, even if the thickness of the semiconductor chip 3 varies or the pressing axis is inclined, As shown in FIG. 10, a method of pressing the transfer carrier chip 1 and the semiconductor chip 3 with a pressing jig 8 having a tip portion formed of a convex curved surface with a view to reliably transferring the layer 2 is provided. It has been devised. Further, as shown in FIG. 11, in the step of flip-chip connecting the semiconductor chip 3 on the wiring board 6, similarly to the above-mentioned transfer step, a convex pressing jig 8 is formed.
A method of pressing the semiconductor chip 3 and the wiring substrate 6 has been devised (Japanese Patent Application No. 8-254431).

【0006】[0006]

【発明が解決しようとする課題】しかしながら、図12
に示すように、転写用キャリアチップ1や半導体チップ
3が大きくなった場合、従来の凸形状の加圧治具8を用
いた方法では大形キャリアチップ9等のそりの影響によ
り均一な加圧に限界があり、多数のはんだ層2を大形半
導体チップ10の電極4に完全に転写しはんだバンプ5
を形成することや、また、はんだバンプ5の接続工程に
おいても大形半導体チップ10を配線基板6や他の半導
体チップに完全にバンプ接続することが困難となる。
However, FIG.
As shown in FIG. 7, when the transfer carrier chip 1 and the semiconductor chip 3 become large, the conventional method using the convex pressing jig 8 causes uniform pressurization due to the influence of the warpage of the large carrier chip 9 and the like. The solder bumps 5 are completely transferred to the electrodes 4 of the large semiconductor chip
Also, it is difficult to completely connect the large-sized semiconductor chip 10 to the wiring board 6 and other semiconductor chips in the step of connecting the solder bumps 5 in the solder bump 5 connection process.

【0007】本発明は、転写用のキャリアチップや半導
体チップが大形化しても、はんだ層を完全に半導体チッ
プの電極に転写しはんだバンプを形成したり、配線基板
にバンプ接続することができるはんだバンプの形成方
法,はんだバンプの接続方法および加圧治具を提供する
ことを目的とするものである。
According to the present invention, even if a transfer carrier chip or a semiconductor chip is enlarged, the solder layer can be completely transferred to the electrode of the semiconductor chip to form a solder bump or can be connected to a wiring board by a bump. It is an object of the present invention to provide a method of forming a solder bump, a method of connecting a solder bump, and a pressing jig.

【0008】[0008]

【課題を解決するための手段】本発明にかかるはんだバ
ンプの形成方法は、はんだとのぬれ性が劣るキャリアチ
ップ上に所望の形状,ピッチからなる複数のドット状の
はんだ層を形成し、当該はんだ層と対向する位置に半導
体チップの電極部を位置合わせし、前記はんだ層を加熱
溶融することにより、前記はんだ層を前記半導体チップ
の電極部に転写してはんだバンプを形成するはんだバン
プの形成方法において、前記はんだ層を転写する工程
で、前記キャリアチップのはんだ層と半導体チップの電
極間を位置合わせし加圧により仮止めした後、フラック
スを塗布する工程の後、前記はんだの融点以下の温度
で、かつ、前記キャリアチップや半導体チップより大き
な面積の柔軟性シ−トにより加圧面が構成され、密閉さ
れた構造であって内部が所望の圧力に制御された加圧治
で、所望の時間、前記キャリアチップや半導体チップ
を加圧・加熱する工程に引き続き、前記はんだの融点以
上の温度で所望の時間加熱する工程を行うことにより前
記はんだ層を前記半導体チップの電極に転写しはんだバ
ンプを形成するものである。
According to the present invention, there is provided a method for forming a solder bump, comprising forming a plurality of dot-shaped solder layers having a desired shape and pitch on a carrier chip having poor wettability with solder; Positioning the electrode portion of the semiconductor chip at a position facing the solder layer, and heating and melting the solder layer, thereby transferring the solder layer to the electrode portion of the semiconductor chip to form a solder bump. In the method, in the step of transferring the solder layer, after the solder layer of the carrier chip and the electrode of the semiconductor chip are aligned and temporarily fixed by pressing, after the step of applying a flux, the melting point of the solder is equal to or lower than the melting point. Temperature and larger than the carrier chip or semiconductor chip
The pressurized surface is composed of a flexible sheet with a large area,
Pressurization with an internal structure controlled to a desired pressure
Tool , for a desired time, subsequent to the step of pressurizing and heating the carrier chip or the semiconductor chip, performing a step of heating the solder layer at a temperature equal to or higher than the melting point of the solder for a desired time, thereby forming the electrodes of the semiconductor chip on the solder layer. To form a solder bump.

【0009】[0009]

【0010】さらに上記のはんだバンプの形成方法では
んだバンプを形成し、前記はんだバンプが形成された半
導体チップを配線基板あるいは他の半導体チップにバン
プ接続する際に、前記半導体チップを配線基板あるいは
他の半導体チップの電極間を位置合わせし加圧により仮
止めした後、フラックスを塗布する工程の後、前記はん
だの融点以下の温度で、かつ、前記キャリアチップや半
導体チップより大きな面積の柔軟性シ−トにより加圧面
が構成され、密閉された構造であって内部が所望の圧力
に制御された加圧治具で、所望の時間、前記半導体チッ
プあるいは配線基板を加圧・加熱する工程に引き続き、
前記はんだの融点以上の温度で所望の時間熱処理をする
工程を行うことによりバンプ接続するものである。
Further, a solder bump is formed by the above-described method for forming a solder bump, and when the semiconductor chip on which the solder bump is formed is connected to a wiring board or another semiconductor chip by a bump, the semiconductor chip is connected to the wiring board or another semiconductor chip. after temporarily fixed by inter-electrode Shi the positioning pressure of the semiconductor chip, after the step of applying the flux, in the solder melting point below the temperature and the carrier chip and half
Pressing surface due to flexible sheet with larger area than conductor chip
Is constructed, the structure is sealed and the inside is at the desired pressure.
With a pressure jig controlled to a desired time, following the step of pressing and heating the semiconductor chip or the wiring board,
The bump connection is performed by performing a heat treatment at a temperature equal to or higher than the melting point of the solder for a desired time.

【0011】[0011]

【0012】また、本発明の加圧治具は、半導体チップ
にはんだを転写する時、あるいは半導体チップを配線基
板に接続する時に用いるものであって、剛体の基底部と
柔軟性シートを基底部に装着して密閉構造とした先端部
とを備え、該密閉構造内を所定の圧力にしたものであ
る。
The pressing jig of the present invention is used when transferring solder to a semiconductor chip or when connecting a semiconductor chip to a wiring board, and comprises a rigid base and a flexible sheet. And a front end portion which is attached to a sealed structure to make the inside of the sealed structure a predetermined pressure.

【0013】[0013]

【発明の実施の形態】本発明のはんだバンプの形成方法
は、図1および図2に基本構成を示すように、はんだ層
2を転写する工程において、はんだの融点以下の温度
で、かつ、ホルダ11の先端部に柔軟性樹脂12を装着
した加圧治具13(図1)、あるいは、ホルダ11と柔
軟性シート14で所望の圧力に制御された加圧治具15
(図2)で、所望の時間、前記大形キャリアチップ9あ
るいは大形半導体チップ10を加圧・加熱する工程の
後、前記はんだの融点以上の温度で所望の時間加熱処理
をする工程を行うことにより前記はんだ層2を大形半導
体チップ10に転写しはんだバンプを形成することを特
徴とするものである。
Method of forming solder bumps of the embodiment of the present invention, as showing the basic structure 1 and 2, in the step of transferring the solder layer 2, at a temperature below the melting point of the solder, and the holder A pressing jig 13 (FIG. 1) in which a flexible resin 12 is mounted on the tip of the pressing member 11, or a pressing jig 15 controlled to a desired pressure by the holder 11 and the flexible sheet 14.
In FIG. 2, after the step of pressurizing and heating the large carrier chip 9 or the large semiconductor chip 10 for a desired time, a step of performing a heat treatment at a temperature equal to or higher than the melting point of the solder for a desired time is performed. Thus, the solder layer 2 is transferred to the large semiconductor chip 10 to form a solder bump.

【0014】また、本発明のはんだバンプの接続方法
は、前記はんだ層2を転写する工程において、加圧しな
がら所望の時間熱処理する工程、およびこの工程に引き
続き熱処理する工程に加え、図3および図4に基本構成
示すように、前記大形半導体チップ10を配線基板あ
るいは他の半導体チップ6にバンプ接続する工程におい
ても前記はんだ層2を転写する工程に類似した工程と
し、前記はんだの融点以下の温度で、かつ、ホルダ11
の先端部に柔軟性樹脂12を装着した加圧治具13(図
3)、あるいはホルダ11と柔軟性シート14で所望の
内部圧力に制御された加圧治具15(図4)で、所望の
時間、前記大形半導体チップ10あるいは配線基板を加
圧・加熱する工程の後、前記はんだの融点以上の温度で
所望の時間加熱処理をする工程を行うことによりバンプ
接続することを特徴とするものである。
In the method of connecting solder bumps according to the present invention, in the step of transferring the solder layer 2, in addition to the step of performing heat treatment for a desired time while applying pressure and the step of performing heat treatment subsequent to this step, FIGS. 4 Basic configuration
As shown in the figure, the step of bump-connecting the large semiconductor chip 10 to a wiring board or another semiconductor chip 6 is also a step similar to the step of transferring the solder layer 2, and at a temperature equal to or lower than the melting point of the solder, And the holder 11
With the pressing jig 13 (FIG. 3) in which the flexible resin 12 is attached to the tip of the sheet, or the pressing jig 15 (FIG. 4) controlled to a desired internal pressure by the holder 11 and the flexible sheet 14. After the step of pressurizing and heating the large semiconductor chip 10 or the wiring board for a period of time, the bump connection is performed by performing a step of heating for a desired time at a temperature equal to or higher than the melting point of the solder. Things.

【0015】さらに本発明は、前記はんだ層を転写する
工程において、前記はんだの融点以下の温度で、かつ、
イヤフラム機能をもたせるよう密閉された構造で内部
を所望の圧力に制御された柔軟性シートを有する加圧治
具13で、所望の時間、前記大形キャリアチップあるい
大形半導体チップ10を加圧・加熱する工程により、前
記大形キャリアチップ上に形成したはんだ層を、対向す
る大形半導体チップの電極上に一様な圧力でギャップを
生じることなく接触させることができるものである。
[0015] The present invention, in the step of transferring the solder layer, by the solder melting point temperature below One or,
In pressing jig 13 having a sealed flexible sheet structure internal controlled to a desired pressure so as to have a da Iyafuramu function, desired time, pressure to have large semiconductor chip 10 with the large carrier chip By the step of applying pressure and heating, the solder layer formed on the large carrier chip can be brought into contact with the electrodes of the large semiconductor chip facing each other at a uniform pressure without a gap.

【0016】[0016]

【実施例】本発明と技術分野を同じくする関連技術を図
5、図6に、そして本発明の実施例を図7,図8に示
す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
5 and 6 and an embodiment of the present invention is shown in FIGS .

【0017】図5にはんだバンプの形成方法に関する例
を示す。はんだとの濡れ性に劣る基板材料として、例え
ばシリコン,チタン,モリブデン等からなる大形キャリ
アチップ9の上に、フィルム状の厚膜レジスト(例え
ば、デュポン社の商品名「リストン」あるいは液状のレ
ジスト(例えば、シプレー社のAZ系レジスト)を用い
てパターン形成し、真空蒸着法等によりはんだを形成し
た後、リフトオフ技術により前記レジストを除去し、は
んだ層2を形成する(a)。前記大形キャリアチップ9
に形成したはんだ層2と大形半導体チップ10上の電極
4を位置合わせし、若干の加圧により両者を仮止めし、
これをキャリア治具17に載せ、はんだ層2に浸透する
ようにフラックス16を塗布する(b)。次に、ホルダ
11の先端部に柔軟性樹脂12を装着した加圧治具13
を用いて大形キャリアチップ9の裏面を加圧するととも
に、前記はんだ層2の融点以下の温度に設定されたホッ
トプレート18上で、所望の時間,圧力,温度に制御さ
れた条件のもとで加圧・加熱処理を行う(c)。ここ
で、柔軟性樹脂12としては、耐熱性にも優れるシリコ
ーン樹脂を用いることができる。この工程に引き続き、
前記はんだの融点以上の温度で所望の時間加熱処理を行
い、転写用のはんだバンプ5を作成する(d)。最後
に、有機溶剤を用いてフラックス16を洗浄除去しはん
だバンプ5が完成する(e)。
[0017] An example <br/> about the method of forming solder bumps in FIG. As a substrate material having poor wettability with solder, for example, a film-like thick film resist (for example, DuPont product name "Liston" or liquid resist) is formed on a large carrier chip 9 made of silicon, titanium, molybdenum, or the like. (For example, an AZ-based resist manufactured by Shipley Co.), a solder is formed by a vacuum evaporation method or the like, and then the resist is removed by a lift-off technique to form a solder layer 2 (a). Carrier chip 9
The solder layer 2 formed on the large-sized semiconductor chip 10 is aligned with the electrode 4 and temporarily fixed by a slight pressure.
This is placed on a carrier jig 17 and a flux 16 is applied so as to permeate the solder layer 2 (b). Next, a pressing jig 13 in which a flexible resin 12 is attached to the tip of the holder 11
Is applied to the back surface of the large-sized carrier chip 9 and, on a hot plate 18 set at a temperature equal to or lower than the melting point of the solder layer 2, under a condition controlled to a desired time, pressure and temperature. A pressure / heat treatment is performed (c). Here, as the flexible resin 12, a silicone resin having excellent heat resistance can be used. Following this step,
Heat treatment is performed for a desired time at a temperature equal to or higher than the melting point of the solder to form a solder bump 5 for transfer (d). Finally, the flux 16 is washed and removed using an organic solvent to complete the solder bump 5 (e).

【0018】図6は転写されたはんだバンプ5を有する
大形半導体チップ10を配線基板6にバンプ接続する工
程を示したものである。転写されたはんだバンプ5を有
する大形半導体チップ10(a)のはんだバンプ5を配
線基板6の電極7上に位置合わせし、若干の加圧により
両者を仮止めし、これをキャリア治具17に載せ、はん
だバンプ5に浸透するようにフラックス16を塗布する
(b)。次に、先の転写工程で用いたものと同じく、ホ
ルダ11の先端部に柔軟性樹脂12を装着した加圧治具
13(図1)を用いて大形半導体チップ10の裏面を加
圧するとともに、前記はんだバンプ5の融点以下の温度
に設定されたホットプレート18上で、所望の時間,圧
力,温度に制御された条件のもとで加圧・加熱処理を行
う(c)。この工程に引き続き、前記はんだの融点以上
の温度からなる所望の温度,時間に制御された条件で加
熱処理をし、バンプ接続を行う(d)。最後に、有機溶
剤を用いてフラックス16を洗浄除去しバンプ接続が完
成する(e)。
FIG. 6 shows a step of connecting the large semiconductor chip 10 having the transferred solder bumps 5 to the wiring board 6 by bump connection. The solder bumps 5 of the large semiconductor chip 10 (a) having the transferred solder bumps 5 are positioned on the electrodes 7 of the wiring board 6 and temporarily fixed by a slight pressure. And apply a flux 16 so as to penetrate the solder bumps 5 (b). Next, the back surface of the large-sized semiconductor chip 10 is pressed by using a pressing jig 13 (FIG. 1) in which a flexible resin 12 is attached to the tip of the holder 11 in the same manner as that used in the previous transfer step. Then, a pressurizing / heating process is performed on the hot plate 18 set at a temperature equal to or lower than the melting point of the solder bump 5 under conditions controlled to a desired time, pressure and temperature (c). Subsequent to this step, a heat treatment is performed under a condition controlled at a desired temperature and time, which is equal to or higher than the melting point of the solder, to perform bump connection (d). Finally, the flux 16 is washed and removed using an organic solvent to complete the bump connection (e).

【0019】図7は転写工程において、ホルダ11と柔
軟性シート14で所望の内部圧力に制御された加圧治具
15を用いて大形キャリアチップ9の裏面を加圧すると
ともに、前記はんだバンプ5の融点以下の温度に設定さ
れたホットプレート18上で、所望の時間,圧力,温度
に制御された条件のもとで加圧・加熱処理を行うはんだ
バンプの形成工程を示したものである。ここで、柔軟性
シート14としては、樹脂材料では耐熱性のあるフィル
ム材のフッ素樹脂やポリイミド樹脂等、また、金属材料
ではフィルム状のアルミニウム,ステンレス等を用いる
ことができる。
FIG. 7 shows that in the transfer step, the back surface of the large carrier chip 9 is pressed by using a pressing jig 15 controlled to a desired internal pressure by the holder 11 and the flexible sheet 14, and the solder bump 5 3 shows a process of forming solder bumps in which pressure and heat treatments are performed under conditions controlled to a desired time, pressure and temperature on a hot plate 18 set to a temperature equal to or lower than the melting point. Here, as the flexible sheet 14, a heat-resistant film material such as fluororesin or polyimide resin can be used as a resin material, and a film-like aluminum or stainless steel can be used as a metal material.

【0020】図8は、ホルダ11と柔軟性シート14で
所望の内部圧力に制御された加圧治具15を用いて転写
されたはんだバンプ5を有する大形半導体チップ10を
配線基板6にフリップチップ接続する工程を示したもの
である。
FIG. 8 shows that a large semiconductor chip 10 having solder bumps 5 transferred thereto by a pressing jig 15 controlled to a desired internal pressure by a holder 11 and a flexible sheet 14 is flipped onto a wiring board 6. It shows a step of connecting chips.

【0021】なお、本実施例では、キャリアチップや半
導体チップの形状に制限されるものではなく、本実施例
で示した方法により、チップ形状のような小さなものか
ら、チップに切り出す前のウエハ形状のような大きなも
のまで適用できることは自明である。
In the present embodiment, the shape of the carrier chip or the semiconductor chip is not limited, and the shape of the wafer before cutting into chips is reduced by the method described in the present embodiment. It is self-evident that it can be applied up to something as large as.

【0022】[0022]

【発明の効果】以上のように、本発明は、はんだ層を転
写する工程において、キャリアチップおよび半導体チッ
プにフラックスを塗布した後、はんだの融点以下の温度
で、かつ、前記キャリアチップや半導体チップより大き
な面積の柔軟性シ−トにより加圧面が構成され、密閉さ
れた構造であって内部が所望の圧力に制御された加圧治
で、所望の時間,圧力,温度に制御された条件のもと
で加圧・加熱処理を行う工程の後、前記はんだの融点以
上の温度で所望の温度および時間に制御された条件のも
ので熱処理をする工程の2段の熱処理工程を採っている
ため、加圧軸が前記キャリアチップや半導体チップの面
に垂直でなく、しかも、半導体チップに厚さのばらつき
があるとしても、キャリアチップ上に形成したはんだ層
を、対向する半導体チップの電極上にほぼ一様な圧力で
ギャップを生じることなく接触させることが期待でき
る。このような方法により、全てのはんだ層を半導体チ
ップの電極に転写することができ、転写用のはんだバン
プを形成することが可能である。
As described above, according to the present invention, in the step of transferring a solder layer, after a flux is applied to a carrier chip and a semiconductor chip, the flux is applied at a temperature lower than the melting point of the solder and the carrier chip or the semiconductor chip. Bigger
The pressurized surface is composed of a flexible sheet with a large area,
Pressurization with an internal structure controlled to a desired pressure
After the step of performing pressure and heat treatment under the conditions controlled to the desired time, pressure, and temperature with the tool , under the conditions controlled to the desired temperature and time at a temperature equal to or higher than the melting point of the solder Since the heat treatment step is performed in two stages, the pressing axis is not perpendicular to the surface of the carrier chip or the semiconductor chip, and even if the semiconductor chip has a thickness variation, It can be expected that the solder layer formed thereon is brought into contact with the electrodes of the opposing semiconductor chip at a substantially uniform pressure without generating a gap. By such a method, all the solder layers can be transferred to the electrodes of the semiconductor chip, and it is possible to form the transfer solder bumps.

【0023】また、半導体チップを配線基板あるいは他
の半導体チップにバンプ接続する工程においても、はん
だ層を転写する工程とほぼ同様にして、前記キャリアチ
ップや半導体チップより大きな面積の柔軟性シ−トによ
り加圧面が構成され、密閉された構造であって内部が所
望の圧力に制御された加圧治具で、所望の時間,半導体
チップあるいは配線基板を加圧する工程の後、はんだの
融点以上の温度で所望の時間熱処理をする工程を行うよ
うにしたので、半導体チップと配線基板あるいは他の半
導体チップとのバンプ接続を完全に行うことが可能であ
る。
Also, in the step of connecting a semiconductor chip to a wiring board or another semiconductor chip by a bump, the carrier chip is substantially similar to the step of transferring a solder layer.
Flexible sheet with a larger area than chips and semiconductor chips
The pressurized surface is composed of
After the step of pressing the semiconductor chip or the wiring board for a desired time with a pressing jig controlled to a desired pressure, a step of performing a heat treatment at a temperature higher than the melting point of the solder for a desired time is performed. The bump connection between the semiconductor chip and the wiring board or another semiconductor chip can be completely performed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の基本構成を示す図であり、ここでの
圧治具を用いた転写用のはんだバンプの形成工程の概略
を示す。
[1] is a diagram showing a basic configuration of the present invention, shows the outline of the formation process of the solder bumps for transcription with pressurizing jig here.

【図2】本発明の基本構成を示す図であり、ここでの
圧治具を用いた転写用のはんだバンプの形成工程の概略
を示す。
[Figure 2] is a diagram showing a basic configuration of the present invention, shows the outline of the formation process of the solder bumps for transcription with pressurizing jig here.

【図3】本発明の基本構成を示す図であり、ここでの
圧治具を用いたバンプ接続の概略工程を示す。
[Figure 3] is a diagram showing a basic configuration of the present invention, shows the schematic process of bump connection using the pressurizing jig here.

【図4】本発明の基本構成を示す図であり、ここでの
圧治具を用いたバンプ接続の概略工程を示す。
[Figure 4] is a diagram showing a basic configuration of the present invention, shows the schematic process of bump connection using the pressurizing jig here.

【図5】本発明と技術分野を同じくする関連技術にかか
るはんだバンプの形成方法の一実施例を示す図である。
FIG. 5 is a view showing one embodiment of a method of forming a solder bump according to the related art in the same technical field as the present invention.

【図6】本発明と技術分野を同じくする関連技術にかか
るはんだバンプの接続方法の一実施例を示す図である。
FIG. 6 is a view showing one embodiment of a method of connecting solder bumps according to a related technique in the same technical field as the present invention.

【図7】本発明にかかるはんだバンプの形成方法の実
例を示す図である。
7 is a diagram showing the real施例forming method according solder bumps to the present invention.

【図8】本発明にかかるはんだバンプの接続方法の実
例を示す図である。
8 is a diagram showing the real施例connection method according solder bumps to the present invention.

【図9】従来技術による転写用のはんだバンプの形成工
程の説明図である。
FIG. 9 is an explanatory diagram of a process of forming a solder bump for transfer according to a conventional technique.

【図10】従来技術による転写用のはんだバンプの形成
工程における加圧の状態を説明するための図である。
FIG. 10 is a view for explaining a state of pressurization in a process of forming a transfer solder bump according to a conventional technique.

【図11】従来技術による転写用のはんだバンプの形成
工程における加圧の状態を説明するための図である。
FIG. 11 is a view for explaining a state of pressurization in a step of forming a solder bump for transfer according to a conventional technique.

【図12】従来技術による転写用のはんだバンプの形成
工程における加圧の状態を説明するための図である。
FIG. 12 is a diagram for explaining a state of pressurization in a step of forming a solder bump for transfer according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 転写用キャリアチップ 2 はんだ層 3 半導体チップ 4 電極(半導体チップ上) 5 はんだバンプ 6 配線基板 7 電極(配線基板上) 8 凸形状の加圧治具 9 大形キャリアチップ 10 大形半導体チップ 11 ホルダ 12 柔軟性樹脂 13 加圧治具(柔軟性樹脂形) 14 柔軟性シート 15 加圧治具(柔軟性シート形) 16 フラックス 17 キャリア治具 18 ホットプレート DESCRIPTION OF SYMBOLS 1 Transfer carrier chip 2 Solder layer 3 Semiconductor chip 4 Electrode (on a semiconductor chip) 5 Solder bump 6 Wiring board 7 Electrode (on a wiring board) 8 Pressing jig of convex shape 9 Large carrier chip 10 Large semiconductor chip 11 Holder 12 Flexible resin 13 Pressure jig (flexible resin type) 14 Flexible sheet 15 Pressure jig (flexible sheet type) 16 Flux 17 Carrier jig 18 Hot plate

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 はんだとのぬれ性が劣るキャリアチップ
上に所望の形状,ピッチからなる複数のドット状のはん
だ層を形成し、当該はんだ層と対向する位置に半導体チ
ップの電極部を位置合わせし、前記はんだ層を加熱溶融
することにより、前記はんだ層を前記半導体チップの電
極部に転写してはんだバンプを形成するはんだバンプの
形成方法において、 前記はんだ層を転写する工程で、前記キャリアチップの
はんだ層と半導体チップの電極間を位置合わせし加圧に
より仮止めした後、フラックスを塗布する工程の後、前
記はんだの融点以下の温度で、かつ、前記キャリアチッ
プや半導体チップより大きな面積の柔軟性シ−トにより
加圧面が構成され、密閉された構造であって内部が所望
の圧力に制御された加圧治具で、所望の時間、前記キャ
リアチップや半導体チップを加圧・加熱する工程に引き
続き、前記はんだの融点以上の温度で所望の時間加熱す
る工程を行うことにより前記はんだ層を前記半導体チッ
プの電極に転写しはんだバンプを形成することを特徴と
するはんだバンプの形成方法。
A plurality of dot-shaped solder layers having a desired shape and pitch are formed on a carrier chip having poor wettability with solder, and an electrode portion of the semiconductor chip is positioned at a position facing the solder layer. In the method of forming a solder bump by transferring the solder layer to an electrode portion of the semiconductor chip by heating and melting the solder layer, in the step of transferring the solder layer, After aligning the solder layer and the electrodes of the semiconductor chip and temporarily fixing them by pressing, after a step of applying a flux, at a temperature equal to or lower than the melting point of the solder, and having an area larger than that of the carrier chip or the semiconductor chip . Flexible sheet
The pressurized surface is configured, the structure is sealed and the inside is desired
With a pressing jig controlled to a pressure of, for a desired time, following the step of pressing and heating the carrier chip or the semiconductor chip, by performing a step of heating for a desired time at a temperature equal to or higher than the melting point of the solder A method for forming a solder bump, comprising transferring the solder layer to an electrode of the semiconductor chip to form a solder bump.
【請求項2】 請求項1に記載のはんだバンプの形成方
法ではんだバンプを形成し、 前記はんだバンプが形成された半導体チップを配線基板
あるいは他の半導体チップにバンプ接続する際に、前記
半導体チップを配線基板あるいは他の半導体チップの電
極間を位置合わせし加圧により仮止めした後、フラック
スを塗布する工程の後、前記はんだの融点以下の温度
で、かつ、前記キャリアチップや半導体チップより大き
な面積の柔軟性シ−トにより加圧面が構成され、密閉さ
れた構造であって内部が所望の圧力に制御された加圧治
具で、所望の時間、前記半導体チップあるいは配線基板
を加圧・加熱する工程に引き続き、前記はんだの融点以
上の温度で所望の時間熱処理をする工程を行うことによ
りバンプ接続する ことを特徴とするはんだバンプの接続
方法。
2. A method of forming a solder bump according to claim 1 , wherein the solder bump is formed, and the semiconductor chip on which the solder bump is formed is mounted on a wiring board.
Or when connecting bumps to other semiconductor chips,
Connect the semiconductor chip to the wiring board or other semiconductor chip.
After positioning the gap and temporarily fixing by pressing,
After the step of applying solder, the temperature below the melting point of the solder
And larger than the carrier chip or the semiconductor chip.
The pressurized surface is composed of a flexible sheet with a large area,
Pressurization with an internal structure controlled to a desired pressure
Tool, for the desired time, the semiconductor chip or the wiring board
After the step of pressurizing and heating
By performing a heat treatment at the above temperature for a desired time.
Connection <br/> method of solder bumps, characterized by bump connection Ri.
【請求項3】 半導体チップにはんだを転写する時、あ
るいは半導体チップを配線基板に接続する時に用いる加
圧治具であって、剛体の基底部と柔軟性シートを基底部
に装着して密閉構造とした先端部とを備え、該密閉構造
内を所定の圧 力にしたことを特徴とする加圧治具。
3. When transferring solder to a semiconductor chip,
Or an additional element used to connect the semiconductor chip to the wiring board.
A pressure jig, with a rigid base and a flexible sheet
And a closed end that is attached to the
Pressing jig, characterized in that the inner to the predetermined pressure.
JP09029952A 1997-02-14 1997-02-14 Solder bump formation method, solder bump connection method and pressure jig Expired - Lifetime JP3123707B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09029952A JP3123707B2 (en) 1997-02-14 1997-02-14 Solder bump formation method, solder bump connection method and pressure jig

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09029952A JP3123707B2 (en) 1997-02-14 1997-02-14 Solder bump formation method, solder bump connection method and pressure jig

Publications (2)

Publication Number Publication Date
JPH10229087A JPH10229087A (en) 1998-08-25
JP3123707B2 true JP3123707B2 (en) 2001-01-15

Family

ID=12290332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09029952A Expired - Lifetime JP3123707B2 (en) 1997-02-14 1997-02-14 Solder bump formation method, solder bump connection method and pressure jig

Country Status (1)

Country Link
JP (1) JP3123707B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7833831B2 (en) 2007-02-22 2010-11-16 Fujitsu Limited Method of manufacturing an electronic component and an electronic device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370562B (en) * 2020-03-18 2021-03-09 京东方科技集团股份有限公司 Transfer printing method of micro light-emitting diode and micro light-emitting diode display panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7833831B2 (en) 2007-02-22 2010-11-16 Fujitsu Limited Method of manufacturing an electronic component and an electronic device

Also Published As

Publication number Publication date
JPH10229087A (en) 1998-08-25

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