JP3122644B2 - Method for manufacturing semiconductor light emitting device - Google Patents
Method for manufacturing semiconductor light emitting deviceInfo
- Publication number
- JP3122644B2 JP3122644B2 JP25624998A JP25624998A JP3122644B2 JP 3122644 B2 JP3122644 B2 JP 3122644B2 JP 25624998 A JP25624998 A JP 25624998A JP 25624998 A JP25624998 A JP 25624998A JP 3122644 B2 JP3122644 B2 JP 3122644B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light emitting
- emitting device
- semiconductor
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 description 8
- 239000010980 sapphire Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 230000007704 transition Effects 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- OTRPZROOJRIMKW-UHFFFAOYSA-N triethylindigane Chemical compound CC[In](CC)CC OTRPZROOJRIMKW-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910007541 Zn O Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- QBJCZLXULXFYCK-UHFFFAOYSA-N magnesium;cyclopenta-1,3-diene Chemical compound [Mg+2].C1C=CC=[C-]1.C1C=CC=[C-]1 QBJCZLXULXFYCK-UHFFFAOYSA-N 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0756—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Led Devices (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、高輝度、高精細の
半導体発光素子の製造方法に関する。The present invention relates to a method of manufacturing a high-brightness, high-definition semiconductor light emitting device.
【0002】[0002]
【従来の技術】発光ダイオード(LED)は、明るいと
ころでも見やすく、各種表示ランプなどのディスプレイ
装置に広く用いられている。緑、黄緑のLEDとしては
発光部にNをドープしたGaPを用いた素子、黄色のL
EDとしては発光部にNをドープしたGaAsPを用い
た素子、赤のLEDとしては発光部にZn−Oをドープ
したGaAsPまたはAlGaAsを用いた素子があ
り、それぞれ製品化されている。2. Description of the Related Art Light emitting diodes (LEDs) are easy to see even in bright places and are widely used in display devices such as various display lamps. For the green and yellow-green LEDs, an element using GaP doped with N in the light-emitting portion, a yellow L
As the ED, there is an element using GaAsP doped with N in the light-emitting part, and as the red LED, an element using GaAsP or AlGaAs doped with Zn-O in the light-emitting part.
【0003】しかし、上記LEDは、以下のような欠点
を有する。すなわち、GaP,GaAsPは間接遷移型
の半導体であり、不純物を添加して発光中心を形成して
いるため、この発光中心の濃度が低くなる。従って、電
流を増加すると発光出力がすぐに飽和してしまい、高輝
度が得られない。また、AlxGa1-xAs(0≦x≦
1)は、ストップランプなどの高輝度LEDとして使用
されているが、Al組成比xが0.45より大きくなる
と間接遷移となる。よって、Al組成比が増大するほ
ど、すなわち発光波長が短くなるほど効率が低下する。
さらに、GaP、GaAsP、AlGaAs系の半導体
では、青色発光が得られない。[0003] However, the above LED has the following disadvantages. That is, GaP and GaAsP are indirect transition type semiconductors, and the impurity is added to form the light emission center, so that the concentration of the light emission center becomes low. Therefore, when the current is increased, the light emission output is immediately saturated, and high luminance cannot be obtained. Also, Al x Ga 1-x As (0 ≦ x ≦
1) is used as a high-brightness LED such as a stop lamp, but when the Al composition ratio x exceeds 0.45, an indirect transition occurs. Therefore, the efficiency decreases as the Al composition ratio increases, that is, as the emission wavelength decreases.
Further, blue light emission cannot be obtained with GaP, GaAsP, and AlGaAs-based semiconductors.
【0004】全波長領域で直接遷移型である半導体材料
として、InGaN系材料の研究が進められている。I
nGaNでは、図7に示すようにIII族の組成を変え
ることにより赤から紫外の発光を得ることができる。特
に、サファイア基板とGaNを用いてなる素子の研究が
進められている。例えば、Appl.Phys.Lett.48(1986)p.3
53に示されるように、サファイア基板とGaNの間にA
lNからなるバッファ層を導入することにより、良好な
GaNの結晶が得られる。また、Jpn.J.Appl.Phys.30(1
991)L1705に示されるように、サファイア基板とGaN
との間に低温成長のGaNからなるバッファ層を導入す
ることにより良好なGaNの結晶が得られる。さらに、
Jpn.J.Appl.Phys.28(1989)L2112に示されるように、M
gドープGaNに電子線を照射することにより、p型G
aNが得られ、高輝度の青色LEDが得られている。[0004] InGaN-based materials have been studied as semiconductor materials which are of direct transition type in the entire wavelength region. I
In nGaN, red to ultraviolet light emission can be obtained by changing the group III composition as shown in FIG. In particular, research on devices using a sapphire substrate and GaN has been advanced. For example, Appl.Phys.Lett.48 (1986) p.3
As shown in FIG. 53, A between the sapphire substrate and GaN
By introducing a buffer layer made of 1N, a good GaN crystal can be obtained. Also, Jpn.J.Appl.Phys.30 (1
991) As shown in L1705, sapphire substrate and GaN
By introducing a buffer layer made of GaN grown at a low temperature between these steps, a good GaN crystal can be obtained. further,
As shown in Jpn. J. Appl. Phys. 28 (1989) L2112, M
By irradiating g-doped GaN with an electron beam, p-type G
aN was obtained, and a high-luminance blue LED was obtained.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記の
ような直接遷移型のInGaNを用いた発光素子を実現
するためには、複数の化合物半導体層を連続成長させる
必要がある。複数のIII族の組成の異なる半導体層を
連続成長させていくと、生じた格子歪が格子欠陥を誘発
し、ピット(穴)、クラック(ひび割れ)により発光効
率が低下する。特に、窒化物系化合物半導体層の場合に
は、原子間の結合力が強いので、積層すればするほど格
子歪みによる格子欠陥が多くなる問題があった。However, in order to realize a light emitting device using InGaN of the direct transition type as described above, it is necessary to continuously grow a plurality of compound semiconductor layers. When a plurality of semiconductor layers having different compositions of group III are continuously grown, the generated lattice strain induces lattice defects, and luminous efficiency is reduced due to pits (holes) and cracks (cracks). In particular, in the case of a nitride-based compound semiconductor layer, since the bonding force between atoms is strong, there is a problem that the number of lattice defects due to lattice distortion increases as the layers are stacked.
【0006】本発明は、上記問題点を解決しようとする
ものであり、化合物半導体層を連続成長させる時の格子
歪を緩和して積層させ、高輝度、高精細の半導体発光素
子の製造方法を提供することを目的とする。An object of the present invention is to solve the above-mentioned problems, and to provide a method for manufacturing a high-brightness, high-definition semiconductor light emitting device by relaxing and stacking lattice strains when compound semiconductor layers are continuously grown. The purpose is to provide.
【0007】[0007]
【課題を解決するための手段】本発明に係る半導体発光
素子の製造方法では、基板上にInGaN系材料からな
る半導体層を積層した半導体発光素子の製造方法であっ
て、InxGa1-xN(0≦x≦1)からなる第1半導体
層上に、前記第1半導体層よりも低い温度で成長させた
AlNあるいはInyGa1-yN(0≦y≦1)からなる
第2半導体層を形成させ、前記第2半導体層上に、前記
第2半導体層よりも高い温度で成長させたInzGa1-z
N(0≦z≦1)からなる第3半導体層を形成させるこ
とを特徴とする。A method for manufacturing a semiconductor light emitting device according to the present invention is a method for manufacturing a semiconductor light emitting device in which a semiconductor layer made of an InGaN-based material is laminated on a substrate, comprising the steps of: In x Ga 1 -x On a first semiconductor layer made of N (0 ≦ x ≦ 1), a second semiconductor made of AlN or In y Ga 1-y N (0 ≦ y ≦ 1) grown at a lower temperature than the first semiconductor layer. Forming a semiconductor layer, and forming an In z Ga 1-z on the second semiconductor layer at a higher temperature than the second semiconductor layer;
A third semiconductor layer made of N (0 ≦ z ≦ 1) is formed.
【0008】[0008]
【発明の実施の形態】以下、本発明の実施例を図面を参
照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0009】(実施例1)図3は本発明の実施例1の半
導体発光素子を示す断面図である。この半導体素子は、
サファイア基板1の(0001)面上に、AlNまたは
GaNからなるバッファ層2、Siドープn−InxG
a1-xN層3、Mgドープ高抵抗InxGa1-xN層4、
AlNまたはGaNからなるバッファ層2、Siドープ
n−InxGa1-xN層5、Mgドープ高抵抗InxGa
1-xN層6、AlNまたはGaNからなるバッファ層
2、Siドープn−InxGa1-xN層7およびMgドー
プ高抵抗InxGa1-xN層8が積層形成されている。該
AlNまたはGaNからなるバッファ層2、Siドープ
n−InxGa1-xN層5、Mgドープ高抵抗InxGa
1-xN層6、AlNまたはGaNからなるバッファ層
2、Siドープn−InN層7およびMgドープ高抵抗
InN層8は、Mgドープ高抵抗InxGa1-xN層4お
よびMgドープ高抵抗InxGa1-xN層6が露出するよ
うに部分的に除去されている。Mgドープ高抵抗Inx
Ga1-xN層8の一部、Mgドープ高抵抗InxGa1-x
N層4およびMgドープ高抵抗InxGa1-xN層6の露
出部分は、p型領域4a、6a、8aとして形成され、
p型領域4a、6a、8aの上には、p型Al電極1
0、11、12が設けられ、半導体を露出させなかった
方の側面には、n型Al電極9が設けられている。Embodiment 1 FIG. 3 is a sectional view showing a semiconductor light emitting device according to Embodiment 1 of the present invention. This semiconductor element
On a (0001) plane of a sapphire substrate 1, a buffer layer 2 made of AlN or GaN, Si-doped n-In x G
a 1-x N layer 3, Mg-doped high resistance In x Ga 1-x N layer 4,
Buffer layer 2 made of AlN or GaN, Si-doped n-In x Ga 1-x N layer 5, Mg-doped high resistance an In x Ga
A 1-x N layer 6, a buffer layer 2 made of AlN or GaN, a Si-doped n-In x Ga 1-x N layer 7, and a Mg-doped high-resistance In x Ga 1-x N layer 8 are laminated. Buffer layer 2 made of the AlN or GaN, Si-doped n-In x Ga 1-x N layer 5, Mg-doped high resistance an In x Ga
The 1-x N layer 6, the buffer layer 2 made of AlN or GaN, the Si-doped n-InN layer 7, and the Mg-doped high-resistance InN layer 8 are composed of the Mg-doped high-resistance In x Ga 1-x N layer 4 and the Mg-doped high - resistance layer. The resistance In x Ga 1 -xN layer 6 is partially removed so as to be exposed. Mg-doped high resistance In x
Part of the Ga 1-x N layer 8, Mg-doped high resistance In x Ga 1-x
The exposed portions of the N layer 4 and the Mg-doped high resistance In x Ga 1 -xN layer 6 are formed as p-type regions 4a, 6a, 8a,
The p-type Al electrode 1 is formed on the p-type regions 4a, 6a, and 8a.
0, 11, and 12 are provided, and an n-type Al electrode 9 is provided on the side surface on which the semiconductor is not exposed.
【0010】実施例1の半導体素子を図1から3を参照
して説明する。まず、図1に示すように、サファイア基
板1を基板温度1150℃でサーマルクリーニングし
た。その後、基板温度を600℃に下げ、サファイア基
板1の(0001)面上に、AlNまたはGaNからな
るバッファ層2を成長させ、続いて、基板温度を800
℃に上げ、Siドープn−InxGa1-xN層3およびM
gドープ高抵抗InxGa1-xN層4を成長させた。次
に、基板温度を600℃に下げ、AlNまたはGaNか
らなるバッファ層2を成長させ、続いて、基板温度を8
00℃に上げ、Siドープn−InxGa1-xN層5およ
びMgドープ高抵抗InxGa1-xN層6を成長させた。
さらに、基板温度を600℃に下げ、AlNまたはGa
Nからなるバッファ層2を成長させ、続いて、基板温度
を800℃に上げ、Siドープn−InxGa1-xN層7
およびMgドープ高抵抗InxGa1-xN層8を成長させ
た。A semiconductor device according to a first embodiment will be described with reference to FIGS. First, as shown in FIG. 1, the sapphire substrate 1 was thermally cleaned at a substrate temperature of 1150 ° C. Thereafter, the substrate temperature is lowered to 600 ° C., and a buffer layer 2 made of AlN or GaN is grown on the (0001) plane of the sapphire substrate 1.
° C, the Si-doped n-In x Ga 1-x N layer 3 and M
A g-doped high resistance In x Ga 1-x N layer 4 was grown. Next, the substrate temperature is lowered to 600 ° C., and a buffer layer 2 made of AlN or GaN is grown.
The temperature was raised to 00 ° C., and a Si-doped n-In x Ga 1-x N layer 5 and a Mg-doped high-resistance In x Ga 1-x N layer 6 were grown.
Further, the substrate temperature is lowered to 600 ° C., and AlN or Ga
A buffer layer 2 made of N is grown. Subsequently, the substrate temperature is raised to 800 ° C., and the Si-doped n-In x Ga 1 -x N layer 7 is formed.
And a Mg-doped high resistance In x Ga 1 -xN layer 8 was grown.
【0011】上記各半導体層の成長方法としては、MO
CVD法(有機金属化合物気相成長法)、ガスソースM
BE法(分子線エピタキシー法)が好ましい。上記各半
導体層を形成する原子のソースおよびドーパント材料と
しては、以下の化合物を用いることができる。As a method for growing each of the semiconductor layers, MO
CVD method (organic metal compound vapor phase epitaxy), gas source M
The BE method (molecular beam epitaxy method) is preferred. The following compounds can be used as a source and a dopant material of the atoms forming each semiconductor layer.
【0012】Gaソース:トリメチルガリウム(TM
G)またはトリエチルガリウム(TEG)など、Alソ
ース:トリメチルアルミニウム(TMA)またはトリエ
チルアルミニウム(TEA)など、Inソース:トリメ
チルインジウム(TMI)またはトリエチルインジウム
(TEI)など、Nソース:アンモニア(NH3)な
ど、ドーパント材料:シラン(SiH4)(n型ドーパ
ント用)およびビスシクロペンタジエニルマグネシウム
(Cp2Mg)(p型ドーパント用)など。Ga source: trimethylgallium (TM
G) or triethylgallium (TEG), etc. Al source: trimethylaluminum (TMA) or triethylaluminum (TEA), etc. In source: trimethylindium (TMI) or triethylindium (TEI), N source: ammonia (NH 3 ) And other dopant materials: silane (SiH 4 ) (for n-type dopant) and biscyclopentadienyl magnesium (Cp 2 Mg) (for p-type dopant).
【0013】次に、図2に示すようにドライエッチング
または選択エッチングにより、AlNまたはGaNから
なるバッファ層2、Siドープn−InxGa1-xN層
5、Mgドープ高抵抗InxGa1-xN層6、AlNまた
はGaNからなるバッファ層2、Siドープn−Inx
Ga1-xN層7およびMgドープ高抵抗InxGa1-xN
層8を、Mgドープ高抵抗InxGa1-xN層4およびM
gドープ高抵抗InxGa1-xN層6が露出するように部
分的に除去した。Next, as shown in FIG. 2, by dry etching or selective etching, a buffer layer 2 made of AlN or GaN, a Si-doped n-In x Ga 1 -xN layer 5, a Mg-doped high resistance In x Ga 1 -x N layer 6, buffer layer 2 made of AlN or GaN, Si-doped n-In x
Ga 1-x N layer 7 and Mg-doped high resistance In x Ga 1-x N
Layer 8 is composed of Mg-doped high resistance In x Ga 1 -x N layer 4 and M
The g-doped high resistance In x Ga 1 -xN layer 6 was partially removed so as to be exposed.
【0014】さらに、Mgドープ高抵抗InxGa1-xN
層8の一部、Mgドープ高抵抗InxGa1-xN層4およ
びMgドープ高抵抗InxGa1-xN層6の露出部分に、
電子の到達深さが0.5μm程度になるように電子線を
照射し、p型領域4a、6a、8aを形成した。Further, Mg-doped high resistance In x Ga 1 -xN
In a part of the layer 8, the exposed portions of the Mg-doped high-resistance In x Ga 1-x N layer 4 and the Mg-doped high-resistance In x Ga 1-x N layer 6,
An electron beam was irradiated so that the electron reached a depth of about 0.5 μm to form p-type regions 4a, 6a, and 8a.
【0015】続いて、図3に示すように、p型領域4
a、6a、8aの上に、500μmφのp型Al電極1
0、11、12を、また、半導体層を露出させなかった
方の側面に、n型Al電極9を蒸着する。各Al電極形
成後、ダイシングによりチップに分割し、半導体発光素
子とした。Subsequently, as shown in FIG.
a, 6a, 8a, 500 μmφ p-type Al electrode 1
An n-type Al electrode 9 is deposited on 0, 11, and 12 and on the side surface on which the semiconductor layer is not exposed. After each Al electrode was formed, the chip was divided into chips by dicing to obtain semiconductor light emitting devices.
【0016】上記のような直接遷移型のInGaNを用
いて多波長発光素子を実現するためには、III族の組
成が異なる半導体層を連続成長させる必要がある。しか
し、図7に示すように、格子定数に違いがあるため、連
続成長させた場合には格子歪が生じる。格子歪は格子欠
陥を誘発し、ピット(穴)、クラック(ひび割れ)によ
り発光効率が低下する。そこで、本発明の半導体素子は
各半導体層の間にAlNまたはGaNからなるバッファ
層を介装している。そのバッファ層により、上記格子歪
を緩和することができる。In order to realize a multi-wavelength light emitting device using the direct transition type InGaN as described above, it is necessary to continuously grow semiconductor layers having different Group III compositions. However, as shown in FIG. 7, since there is a difference in the lattice constant, lattice distortion occurs when the crystal is continuously grown. Lattice distortion induces lattice defects, and pits (holes) and cracks (cracks) lower luminous efficiency. Therefore, the semiconductor device of the present invention has a buffer layer made of AlN or GaN interposed between the semiconductor layers. The buffer layer can reduce the lattice strain.
【0017】また、各半導体層を連続成長させた場合、
各層の発光を分離、制御するための素子構造が必要であ
る。そこで、本発明の半導体発光素子の製造方法では、
上方の半導体層の一部を欠落させて下方の半導体層を露
出させるエッチング工程と、露出された部分に荷電粒子
を照射する工程とを含む。このため、各半導体層の発光
部が分離独立して形成され、よって、発光を分離制御す
ることができる。When each semiconductor layer is continuously grown,
An element structure for separating and controlling light emission of each layer is required. Therefore, in the method for manufacturing a semiconductor light emitting device of the present invention,
An etching step of exposing a lower semiconductor layer by removing a part of the upper semiconductor layer; and irradiating the exposed part with charged particles. For this reason, the light emitting portions of the respective semiconductor layers are formed separately and independently, so that the light emission can be separated and controlled.
【0018】各半導体層バッファ層の詳細は以下の通り
とした。Details of each semiconductor buffer layer are as follows.
【0019】AlNバッファ層2:厚み500オングス
トローム Siドープn−InxGa1-xN層3:In0.3Ga
0.7N、厚み2μm Mgドープ高抵抗InxGa1-xN層4:In0.3Ga0.7
N、厚み0.5μm Siドープn−InxGa1-xN層5:In0.7Ga
0.3N、厚み1μm Mgドープ高抵抗InxGa1-xN層6:In0.7Ga0.3
N、厚み0.5μm Siドープn−InxGa1-xN層7:InN、厚み1μ
m Mgドープ高抵抗InxGa1-xN層8:InN、厚み
0.5μm 各半導体層は、ピット、クラックなどの格子欠陥が見ら
れなかった。AlN buffer layer 2: 500 Å thick Si-doped n-In x Ga 1-x N layer 3: In 0.3 Ga
0.7 N, thickness 2 μm Mg-doped high resistance In x Ga 1 -xN layer 4: In 0.3 Ga 0.7
N, 0.5 μm thick Si-doped n-In x Ga 1-x N layer 5: In 0.7 Ga
0.3 N, 1 μm thick Mg-doped high resistance In x Ga 1 -xN layer 6: In 0.7 Ga 0.3
N, thickness 0.5 μm Si-doped n-In x Ga 1 -xN layer 7: InN, thickness 1 μ
mm Mg-doped high-resistance In x Ga 1 -xN layer 8: InN, 0.5 μm thickness In each semiconductor layer, lattice defects such as pits and cracks were not observed.
【0020】本実施例の半導体発光素子においては、
赤、緑、青の高効率、高輝度な発光が得られた。In the semiconductor light emitting device of this embodiment,
High-efficiency, high-luminance light emission of red, green, and blue was obtained.
【0021】(実施例2)図4(a)は本発明の実施例
2の半導体発光素子の露出部分を形成する前の状態を示
す断面図であり、図4(b)はその半導体発光素子のバ
ッファ層を示す断面図である。(Embodiment 2) FIG. 4A is a sectional view showing a state before an exposed portion of a semiconductor light emitting device according to Embodiment 2 of the present invention is formed, and FIG. FIG. 4 is a cross-sectional view showing a buffer layer of FIG.
【0022】実施例2の半導体発光素子のバッファ層4
0a、40b、40cは、20オングストロームのAl
N層41と20オングストロームのInyGa1-yN(0
≦y≦1)層42とを交互に積層してなる多層体であ
る。The buffer layer 4 of the semiconductor light emitting device of the second embodiment
0a, 40b and 40c are 20 angstrom Al
N layer 41 and 20 angstroms of In y Ga 1-y N (0
.Ltoreq.y.ltoreq.1) A multilayer body in which layers 42 are alternately laminated.
【0023】この実施例では、yの値は、バッファ層4
0aでは0.3、バッファ層40bでは0.7、バッフ
ァ層40cでは1.0としてある。In this embodiment, the value of y is
The value is 0.3 for 0a, 0.7 for the buffer layer 40b, and 1.0 for the buffer layer 40c.
【0024】この半導体発光素子は、バッファ層とし
て、AlNバッファ層41とInyGa1-yN(0≦y≦
1)バッファ層42とを交互に積層させた以外は、実施
例1と同様の構成とし、同様の成長方法で作成した。In this semiconductor light emitting device, an AlN buffer layer 41 and In y Ga 1-y N (0 ≦ y ≦
1) Except for alternately laminating the buffer layers 42, the structure was the same as that of Example 1 and was formed by the same growth method.
【0025】各半導体層は、ピット、クラックなどの格
子欠陥が見られなかった。In each semiconductor layer, no lattice defects such as pits and cracks were observed.
【0026】このバッファ層は超格子構造になっている
ため、実施例1のバッファ層より、さらに格子歪の緩和
効果が高く、また、サーマルクリーニングなどによって
除去されない不純物などが基板上に残留していても、そ
の不純物は超格子にトラップされるので、その悪影響を
除くことができる。Since this buffer layer has a superlattice structure, the effect of alleviating lattice distortion is higher than that of the buffer layer of the first embodiment, and impurities that are not removed by thermal cleaning or the like remain on the substrate. Even so, since the impurities are trapped in the superlattice, the adverse effects can be eliminated.
【0027】本実施例の半導体発光素子においては、
赤、緑、青の高効率、高輝度な発光が得られた。In the semiconductor light emitting device of this embodiment,
High-efficiency, high-luminance light emission of red, green, and blue was obtained.
【0028】(実施例3)図5(a)は本発明の実施例
3の半導体発光素子の露出部分を形成する前の状態を示
す断面図であり、図5(b)はその半導体発光素子のバ
ッファ層を示す断面図である。(Embodiment 3) FIG. 5A is a cross-sectional view showing a state before an exposed portion of a semiconductor light emitting device according to Embodiment 3 of the present invention is formed, and FIG. FIG. 4 is a cross-sectional view showing a buffer layer of FIG.
【0029】実施例3の半導体発光素子のバッファ層5
0a、50b、50cは、InGaN層の厚みを変えた
以外は実施例2の半導体発光素子のバッファ層40a、
40b、40cと同様の構成である。具体的には、以下
のような構成となっている。AlN層51の上のIny
Ga1-yN(0≦y≦1)層52は20オングストロー
ムであり、その上のAlN層51の上のInyGa1-yN
(0≦y≦1)層53は30オングストロームであり、
その上のAlN層51の上のInyGa1-yN(0≦y≦
1)層54は40オングストロームであり、その上のA
lN層51の上のInyGa1-yN(0≦y≦1)層55
は90オングストロームであり、その上のAlN層51
の上のInyGa1-yN(0≦y≦1)層56は100オ
ングストロームというように、AlN層51とInyG
a1-yN層(0≦y≦1)とを積層してなる。The buffer layer 5 of the semiconductor light emitting device of the third embodiment
0a, 50b and 50c are buffer layers 40a and 40b of the semiconductor light emitting device of Example 2 except that the thickness of the InGaN layer is changed.
It has the same configuration as 40b and 40c. Specifically, it has the following configuration. In y on AlN layer 51
The Ga 1-y N (0 ≦ y ≦ 1) layer 52 is 20 angstroms, and the In y Ga 1-y N layer on the AlN layer 51 thereon is formed.
(0 ≦ y ≦ 1) layer 53 is 30 angstroms,
In y Ga 1-y N (0 ≦ y ≦
1) Layer 54 is 40 Å and A
In y Ga 1-y N (0 ≦ y ≦ 1) layer 55 on the 1N layer 51
Is 90 Å, and the AlN layer 51 thereon is
The In y Ga 1-y N (0 ≦ y ≦ 1) layer 56 above the AlN layer 51 and the In y G
a 1-y N layers (0 ≦ y ≦ 1).
【0030】この半導体発光素子は、バッファ層とし
て、AlN層51とInyGa1-yN(0≦y≦1)層5
2、53、54・・・55、56とを交互に積層させた
以外は、実施例1と同様にして作成した。In this semiconductor light emitting device, an AlN layer 51 and an In y Ga 1 -y N (0 ≦ y ≦ 1) layer 5 are used as buffer layers.
55, 56 were alternately laminated, and the same as in Example 1 was prepared.
【0031】各半導体層は、ピット、クラックなどの格
子欠陥が見られなかった。このバッファ層は実施例2と
同様に、超格子構造になっているため、実施例1のバッ
ファ層より、さらに格子歪の緩和効果が高い。本実施例
の半導体発光素子においては、赤、緑、青の高効率、高
輝度な発光が得られた。In each semiconductor layer, no lattice defects such as pits and cracks were observed. Since this buffer layer has a superlattice structure similarly to the second embodiment, the buffer layer of the first embodiment is more effective in reducing lattice distortion. In the semiconductor light emitting device of this example, high-efficiency, high-luminance light emission of red, green, and blue was obtained.
【0032】(実施例4)図6(a)は本発明の実施例
4の半導体発光素子の露出部分を形成する前の状態を示
す断面図であり、図6(b)はその半導体発光素子のバ
ッファ層を示す断面図である。(Embodiment 4) FIG. 6 (a) is a sectional view showing a state before an exposed portion of a semiconductor light emitting device according to a fourth embodiment of the present invention is formed, and FIG. FIG. 4 is a cross-sectional view showing a buffer layer of FIG.
【0033】実施例4の半導体発光素子のバッファ層6
0a、60b、60cは、AlNまたはGaNからなる
層61とAlN層62およびInyGa1-yN(0≦y≦
1)層63とを積層してなる。この実施例では、yの値
は、バッファ層40aでは0.3、バッファ層40bで
は0.7、バッファ層40cでは1.0としてある。The buffer layer 6 of the semiconductor light emitting device of the fourth embodiment
0a, 60b, and 60c are a layer 61 and an AlN layer 62 made of AlN or GaN, and In y Ga 1-y N (0 ≦ y ≦
1) The layer 63 is laminated. In this embodiment, the value of y is 0.3 in the buffer layer 40a, 0.7 in the buffer layer 40b, and 1.0 in the buffer layer 40c.
【0034】この半導体発光素子は、バッファ層とし
て、AlN層61と、AlN層62およびInyGa1-y
N(0≦y≦1)層63とを交互に積層させた以外は、
実施例1と同様にして作成した。In this semiconductor light emitting device, an AlN layer 61, an AlN layer 62 and In y Ga 1-y are used as buffer layers.
Except that N (0 ≦ y ≦ 1) layers 63 are alternately laminated.
It was prepared in the same manner as in Example 1.
【0035】各半導体層は、ピット、クラックなどの格
子欠陥が見られなかった。In each semiconductor layer, no lattice defects such as pits and cracks were observed.
【0036】このバッファ層は実施例2と同様に、超格
子構造になっているため、実施例1のバッファ層より、
さらに格子歪の緩和効果が高い。Since this buffer layer has a superlattice structure similarly to the second embodiment, the buffer layer of the first embodiment is
Further, the effect of alleviating lattice distortion is high.
【0037】本実施例の半導体発光素子においては、
赤、緑、青の高効率、高輝度な発光が得られた。In the semiconductor light emitting device of this embodiment,
High-efficiency, high-luminance light emission of red, green, and blue was obtained.
【0038】なお、上記実施例では、赤、緑、青の三原
色の半導体発光素子について述べたが、半導体層のII
I族元素の組成を変えることにより、赤から紫外領域ま
での発光が得られる。例えば、x=0.75ならば、黄
色の半導体発光素子が、x=0.9ならば、オレンジ色
の半導体発光素子が、x=0ならば、紫外域の半導体発
光素子が得られる。In the above embodiment, the semiconductor light emitting devices of the three primary colors of red, green and blue have been described.
By changing the composition of the group I element, light emission from the red to the ultraviolet region can be obtained. For example, when x = 0.75, a yellow semiconductor light emitting element is obtained, when x = 0.9, an orange semiconductor light emitting element is obtained, and when x = 0, an ultraviolet semiconductor light emitting element is obtained.
【0039】また、基板としては、サファイア基板を用
いたが、それ以外に半絶縁性のZnO基板またはSiC
基板などを用いることができる。Although a sapphire substrate was used as the substrate, a semi-insulating ZnO substrate or SiC
A substrate or the like can be used.
【0040】[0040]
【発明の効果】以上の説明で明らかなように、本発明に
よれば、直接遷移型のInGaNを格子歪みを緩和して
積層できるので、高輝度、高効率の発光が得られる半導
体発光素子の製造方法を提供できる。As is apparent from the above description, according to the present invention, direct transition type InGaN can be stacked while relaxing lattice strain, so that a semiconductor light emitting device which can emit light with high luminance and high efficiency can be obtained. A manufacturing method can be provided.
【図1】本発明の実施例1の半導体発光素子の製造工程
を示す図である。FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor light emitting device according to a first embodiment of the present invention.
【図2】本発明の実施例1の半導体発光素子の製造工程
を示す図である。FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor light emitting device according to the first embodiment of the present invention.
【図3】本発明の実施例1の半導体発光素子を示す断面
図である。FIG. 3 is a cross-sectional view illustrating a semiconductor light emitting device according to Example 1 of the present invention.
【図4】(a)は本発明の実施例2の半導体発光素子の
露出部分を形成する前の状態を示す断面図であり、
(b)は本発明の実施例2の半導体発光素子のバッファ
層を示す断面図である。FIG. 4A is a cross-sectional view illustrating a state before an exposed portion of a semiconductor light emitting device according to a second embodiment of the present invention is formed;
(B) is a sectional view showing a buffer layer of the semiconductor light emitting device of Example 2 of the present invention.
【図5】(a)は本発明の実施例3の半導体発光素子の
露出部分を形成する前の状態を示す断面図であり、
(b)は本発明の実施例3の半導体発光素子のバッファ
層を示す断面図である。FIG. 5A is a cross-sectional view illustrating a state before an exposed portion of a semiconductor light emitting device according to a third embodiment of the present invention is formed;
(B) is a sectional view showing a buffer layer of the semiconductor light emitting device of Example 3 of the present invention.
【図6】(a)は本発明の実施例4の半導体発光素子の
露出部分を形成する前の状態を示す断面図であり、
(b)は本発明の実施例4の半導体発光素子のバッファ
層を示す断面図である。FIG. 6A is a cross-sectional view illustrating a state before an exposed portion of a semiconductor light emitting device according to a fourth embodiment of the present invention is formed;
(B) is a sectional view showing a buffer layer of the semiconductor light emitting device of Example 4 of the present invention.
【図7】InxGa1-xNのIII族元素の組成と格子定
数との関係およびエネルギーギャップとの関係を表す図
である。FIG. 7 is a diagram showing a relationship between a composition of a group III element of In x Ga 1 -xN and a lattice constant, and a relationship with an energy gap.
1 サファイア基板 2 AlNまたはGaNからなるバッファ層 3 Siドープn−In0.3Ga0.7N層 4 Mgドープ高抵抗In0.3Ga0.7N層 5 Siドープn−In0.7Ga0.3N層 6 Mgドープ高抵抗In0.7Ga0.3N層 7 Siドープn−InN層 8 Mgドープ高抵抗InN層 4a、6a、8a p型領域 10、11、12 p型Al電極 9 n型Al電極 40a、40b、40c AlN層/InyGa1-yN
(0≦y≦1)層の周期的多層体からなるバッファ層 50a、50b、50c AlN層/InyGa1-yN
(0≦y≦1)層の不規則多層体からなるバッファ層 60a、60b、60c AlNまたはGaNからなる
層とAlN層/InyGa1-yN(0≦y≦1)層の周期
的多層体とからなるバッファ層 41、51、61、63 AlNバッファ層 42、52、53、54、55、56、62 InyG
a1-yN(0≦y≦1)バッファ層Reference Signs List 1 sapphire substrate 2 buffer layer made of AlN or GaN 3 Si-doped n-In 0.3 Ga 0.7 N layer 4 Mg-doped high resistance In 0.3 Ga 0.7 N layer 5 Si-doped n-In 0.7 Ga 0.3 N layer 6 Mg-doped high resistance In 0.7 Ga 0.3 N layer 7 Si-doped n-InN layer 8 Mg-doped high-resistance InN layer 4 a, 6 a, 8 a p-type region 10, 11, 12 p-type Al electrode 9 n-type Al electrode 40 a, 40 b, 40 c AlN layer / In y Ga 1-y N
Buffer layer 50a, 50b, 50c composed of a periodic multilayer of (0 ≦ y ≦ 1) layers AlN layer / In y Ga 1-y N
Buffer layer 60a, 60b, 60c composed of an irregular multilayer body of (0 ≦ y ≦ 1) layers Periodical between AlN or GaN layer and AlN layer / In y Ga 1-y N (0 ≦ y ≦ 1) layer Buffer layers 41, 51, 61, 63 composed of a multilayer body AlN buffer layers 42, 52, 53, 54, 55, 56, 62 In y G
a 1-y N (0 ≦ y ≦ 1) buffer layer
フロントページの続き (72)発明者 細羽 弘之 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (72)発明者 大林 健 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (72)発明者 幡 俊雄 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (72)発明者 須山 尚宏 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (56)参考文献 特開 平3−203388(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 33/00 H01S 5/00 - 5/50 H01L 21/205 Continued on the front page (72) Inventor Hiroyuki Hosoha 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Ken Obayashi 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (72 Inventor Toshio Hata 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Naohiro Suyama 22-22 Nagaike-cho, Abeno-ku, Osaka-shi Osaka Prefecture Inside Sharp Corporation (56) References 3-203388 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 33/00 H01S 5/00-5/50 H01L 21/205
Claims (1)
体層を積層した半導体発光素子の製造方法であって、 InxGa1-xN(0≦x≦1)からなる第1半導体層上
に、前記第1半導体層よりも低い温度で成長させたAl
NあるいはInyGa1-yN(0≦y≦1)からなる第2
半導体層を形成させ、 前記第2半導体層上に、前記第2半導体層よりも高い温
度で成長させたInzGa1-zN(0≦z≦1)からなる
第3半導体層を形成させることを特徴とする半導体発光
素子の製造方法。1. A method for manufacturing a semiconductor light emitting device, comprising: laminating a semiconductor layer made of an InGaN-based material on a substrate, wherein the semiconductor layer is made of In x Ga 1 -xN (0 ≦ x ≦ 1). Al grown at a lower temperature than the first semiconductor layer
N or In y Ga 1-y N (0 ≦ y ≦ 1)
A semiconductor layer is formed, and a third semiconductor layer made of In z Ga 1 -zN (0 ≦ z ≦ 1) grown at a higher temperature than the second semiconductor layer is formed on the second semiconductor layer. A method for manufacturing a semiconductor light emitting device, comprising:
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US6881983B2 (en) | 2002-02-25 | 2005-04-19 | Kopin Corporation | Efficient light emitting diodes and lasers |
US6911079B2 (en) | 2002-04-19 | 2005-06-28 | Kopin Corporation | Method for reducing the resistivity of p-type II-VI and III-V semiconductors |
US6734091B2 (en) | 2002-06-28 | 2004-05-11 | Kopin Corporation | Electrode for p-type gallium nitride-based semiconductors |
JP4574417B2 (en) * | 2005-03-31 | 2010-11-04 | シャープ株式会社 | Light source module, backlight unit, liquid crystal display device |
EP2418696A4 (en) | 2009-04-09 | 2014-02-19 | Panasonic Corp | Nitride semiconductor light-emitting element, illuminating device, liquid crystal display device, method for producing nitride semiconductor light-emitting element and method for manufacturing illuminating device |
WO2011070770A1 (en) | 2009-12-09 | 2011-06-16 | パナソニック株式会社 | Nitride-based semiconductor light-emitting element, lighting device, liquid crystal display device, and method for producing lighting device |
TW202224205A (en) * | 2020-08-04 | 2022-06-16 | 英商普羅科技有限公司 | Led device and method of manufacture |
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1998
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