JP3121862B2 - Programmable logic device using ferroelectric memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device (PLD) using a ferroelectric memory as a configuration memory.

[0002]

2. Description of the Related Art Conventionally, programmable logic devices capable of setting operations such as contents of logical operations have been widely used. Then, in this programmable logic device, it is necessary to write data for operation setting after the device is manufactured, and it is necessary to rewrite stored contents for a test of operation contents and the like.
Therefore, as a configuration memory for setting operation contents, an EPROM (erasable ROM) capable of erasing stored data by irradiating ultraviolet rays or an EEPROM (electrically erasable RO) capable of electrically erasing stored data is provided.
M) and the like, which enables rewriting in the nonvolatile memory.

[0003]

SUMMARY OF THE INVENTION EPROM
In this technology, a large current flows between a drain and a source as a write current, charges are accumulated in a floating gate, and data is stored. For this reason, at the time of data writing, a high voltage corresponding to the writing current to the EPROM, for example, a 5 V system, and at the time of writing,
About 15 V is applied. Therefore, it is necessary to increase the breakdown voltage of each memory cell of the EPROM, and there is a problem that the memory cell becomes large and the degree of integration cannot be increased. In the EEPROM, the write voltage is higher than that in the EPROM. For this reason, there is a problem that it is difficult to secure a withstand voltage including peripheral circuits for making an electrical connection to the memory, the circuit cannot be highly integrated, and the program logic device becomes large. Further, in the conventional EPROM and the like, the writing speed is very slow, so that when data is rewritten many times during a test or the like, there is a problem that a long test time is required.

An object of the present invention is to provide a programmable logic device capable of storing and rewriting data in a configuration memory at a normal operating voltage.

[0005]

A programmable logic device according to the present invention is a programmable logic device that operates in accordance with the storage state of a configuration memory.
A volatile memory circuit that outputs an opposite polarity to both ends in accordance with an input signal and is stabilized, and is connected to the volatile memory circuit and is generated at both ends of the volatile memory circuit due to dielectric polarization of a ferroelectric substance. A ferroelectric capacitor made of a ferroelectric, wherein the dielectric layer for supplying the potential difference to be applied comprises a ferroelectric capacitor. It also outputs the opposite polarity of the volatile memory circuit.
Ferroelectric capacitors at each end
It is preferable that they are respectively connected via a. Ma
Further, both ends of the volatile memory circuit that output opposite polarities
Is preferably further provided.

[0006]

In a ferroelectric memory, when a voltage is applied, dielectric polarization occurs in the ferroelectric. Therefore, when the power is input, the polarity of the volatile memory is set according to the state of the dielectric polarization of the two ferroelectric memories, thereby operating as a nonvolatile memory. Since a large voltage is not required to cause dielectric polarization in the ferroelectric memory, the withstand voltage of the entire memory cell can be set low, the manufacturing conditions of the programmable logic device are relaxed, and the integration density is increased. can do.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the PLD, which includes a wiring block 1 and a plurality of unit cells 2.

The wiring block 1 has a crossbar switch corresponding to each unit cell 2 in order to achieve a desired connection between input / output terminals provided in the integrated circuit and each unit cell 2. The on / off of this switch is set by a nonvolatile configuration memory. That is, as shown in FIG. 2, a pass transistor Tr for turning on / off the signal transmission is provided as a crossbar switch, and the on / off of the pass transistor Tr is set by the configuration memory NVM. Therefore, on / off of the pass transistor Tr is set according to the data of the configuration memory NVM, and a desired signal is transmitted. Each of the unit cells 2 has a logic circuit, and this logic is set by the configuration memory NVM. For example, as shown in FIG. 3, the input signal of the logic gate NAND is determined by the configuration memory NVM,
The logic operation is set as desired.

The configuration memory NVM in this embodiment preferably has a configuration as shown in FIG. That is, two inverters 10
a, 10b, data input / output switches 12a, 12b connecting both ends of the SRAM 10 to a bit line and an inverted bit line and turned on and off by a word line, read / write switches 14a, 14b connected to both ends of the SRAM 10, Ferroelectric capacitors 16a, 16b connecting read / write switches 14a, 14b and control line PL and SRAM 10
, And a switch 18 which is turned on / off by a control line EQ.

Here, the ferroelectric capacitor 16 is a capacitor in which a ferroelectric is used as a dielectric layer, and the ferroelectric is PZT (lead zirconate titanate).
Are used. The ferroelectric substance causes dielectric polarization even when no electric field is applied. Therefore, when a voltage is applied to the ferroelectric capacitor 16 to cause dielectric polarization, the polarization continues even after the application of the voltage is stopped. Therefore, data can be stored using the ferroelectric capacitor 16.

The data storage mechanism will be described with reference to FIG. When a voltage of -VDD to + VDD is applied to the capacitor 16 by the variable power supply as shown in FIG. 5A, the electric charge resulting from the polarization in the capacitor 16 has a hysteresis as shown in FIG. When only one side is viewed, when VDD is applied, the polarization of the charge δq remains, and when -VDD is applied, the polarization of the charge -δq remains. Therefore, data can be stored using this polarization state. next,
A data set based on the electric charge δq caused by the dielectric polarization will be described with reference to FIGS. Here, FIG. 6 shows a case where data “1” is written, and FIG. 7 shows a case where data “0” is written. Assuming that the capacitance of the ferroelectric capacitor 16 is Cs, the Cs is considered to be composed of an amount C that changes according to the application of the voltage and an amount δC corresponding to the polarization remaining after the application of the voltage is removed. Accordingly, the electric charge stored in the capacitor includes the electric charge q stored in response to the application of the voltage and the electric charge δq corresponding to the above-mentioned polarization. Therefore, when the applied voltage is V, q + δq = (C + δC) V (where Cs = C + δC
And ) Have a relationship.

Therefore, as shown in FIG. 6A, when the voltage V is applied to the capacitor 16, the electric charge q + δq is accumulated on the positive electrode side, and the electric charge of -q-δq is accumulated on the negative electrode side. . As shown in FIG. 6B, when the power supply is turned off and the application of the voltage V is removed, the capacitor 1
6 shows a state in which the above-described electric charge is accumulated, and the potential difference is V, but a polarization of ± δq remains in the ferroelectric layer 116. Therefore, the dielectric polarization of the ferroelectric is used for storing data. That is, when both poles of the capacitor 16 are short-circuited as shown in FIG. 6C, the polarization in the ferroelectric layer 116 remains, and in the ferroelectric layer 116 of the capacitor 16, the upper side in the figure is -δq, The lower side is δ
The state of q has been written.

When connected to a bit line bit as shown in FIG. 6D, this bit line bit is
It is expressed as a capacitor having a capacity of Cbit. Therefore, when the lower electrode in the figure of the capacitor 16 is raised by the voltage V, charges corresponding to the two capacitor capacities are accumulated, and the potential of the bit line bit corresponds to the electric charge qb + accumulated here. .

On the other hand, when the direction of voltage application to the capacitor 16 is reversed, the accumulation and polarization of charges occur as described above as shown in FIGS. 7A to 7C. Is the opposite. Therefore, as shown in FIG. 7D, when the voltage V is increased, a charge corresponding to the charge qb- is taken out to the bit line bit.
Here, the voltage difference of the bit line bit in the case of FIG. 6D and the case of FIG. ΔV = (qb + −qb −) / Cbit = 2δq / (Cs +
Cbit).

Therefore, this potential difference ΔV is set to “0”,
If the signal is taken out as a signal representing "1", the written data can be read out.

Here, the above-mentioned potential difference ΔV is calculated as follows.

First, since the charge is stored, qb-qs = ± δq (1) Further, the voltage drop at the two capacitors is qb / Cbit + qs / Cs = V (2)

Therefore, from equations (1) and (2), qb = Cbit (CsV ± δq) / (Cs + Cbit). Then, + δq corresponds to the case of FIG.
Since q corresponds to the case of FIG. 7, ΔV can be expressed as described above.

Therefore, if this ΔV is used to determine the state when the SRAM 10 rises, data can be stored by the dielectric polarization of the ferroelectric capacitor 16. Therefore, normally, by reading the contents of the SRAM 10, data "0" and "1" can be written or read on the bit line.

Next, the initial operation of the nonvolatile memory shown in FIG. 1 when the power is turned on will be described with reference to FIGS.
First, as described above, predetermined data is written in each capacitor 16 (the ferroelectric is polarized). When the power is turned on, the SRAM
10 is an SRAM depending on the state (undefined) condition at that time.
Both ends of 10 are stabilized at either 0.5V or 5.0V (A). Next, the switch 18 is turned on, and S
The potentials at both ends of the RAM 10 are made equal (B). At this time,
If the characteristics of the inverters 10a and 10b constituting the SRAM 10 are the same, both ends of the SRAM 10 are 2.5V
And the SRAM 10 is configured in this way.

In this state, the plate voltage is set to 2.5
V, the read / write line RW is set to H, the switch 14 is turned on, and both ends of the SRAM 10 are connected to the capacitor 14, respectively. Therefore, the capacitor 1
6 are both 2.5V. Therefore, capacitor 1
The polarization state of the ferroelectric in 6 is not destroyed (C).
Then, the switch 18 is turned off, and the plate voltage is changed to -2.5 V (D). As a result, the difference between the voltages written in the capacitor 16 is
6 appears on the upper electrode. That is, a voltage Δv corresponding to 2δq is applied as a potential difference between both ends of the SRAM 10 to −2.5V. For this reason, the SRAM 10 operates according to the difference of Δv between both ends, and the left side where the high voltage is
V, the right side is stabilized at 0V (E). Thus, S
In the RAM 10, a state corresponding to the state of the capacitor 16 can be set, so that the RAM 10 functions as a nonvolatile memory.

However, in the above (E), voltages of 7.5 V and 2.5 V are applied to both ends of the capacitor 16. For this reason, the polarization state of the capacitor 16, particularly the capacitor 16 whose upper side is negatively polarized,
The stored content of b is destroyed. Therefore, it is necessary to restore the storage contents of the capacitor 16. Therefore, the plate voltage is set to 5 V (F). Thereby, the capacitor 16
b is restored to the state of-on the upper side. Thus, when the restoration of the storage state is completed, the read / write is set to L, and the capacitor 16 operating as a nonvolatile memory is disconnected (G). As a result, the SRA
M10 can be set. Therefore, it functions as a nonvolatile memory.

As described above, in the memory of this embodiment, a voltage of -2.5 V to 5 V is applied to the capacitor 16, but only 0 to 5 V is used for the SRAM 10 and other circuits. Therefore, writing is performed at a normal operating potential (5 V system). Rewriting can be performed, and there is no need to consider a special withstand voltage in the memory and its peripheral circuits. Therefore, the transistors constituting the circuit need only be the same as those of a normal logic, so that the area can be reduced as a whole and the degree of integration can be increased.

Next, FIG. 10A shows the configuration of a system using this configuration memory. In this example, four (2 × 2) non-volatile memories NVM are provided, and a decoder 20 and a read / write unit 22 are connected to each of them. That is, the decoder 20 has an input side connected to an address bus and control lines, and an output side connected to a word line, an EQ line, a RW line, and a plate line PL. The read / write section 22 has a data bus connected to its input side and a bit line b and an inverted bit line rb connected to its output side. FIG.
0 (B) shows a symbolized version of the nonvolatile memory NVM of the present embodiment, and each nonvolatile memory NVM in FIG. 9 has the configuration of FIG.

When writing data to the nonvolatile memory NVM, as shown in FIG.
With the RW at H and the plate PL at L, the address to be written is placed on the address bus. by this,
The corresponding word line W becomes H, and the bit line b and the inverted bit line rb are connected to both ends of the corresponding SRAM 10. Therefore, bit line data is set in the SRAM. At this time, since RW is at H, the ferroelectric capacitor 16 is also provided with the SRAM.
The dielectric polarization according to the state of 10 occurs. Here, since the ferroelectric capacitor 16 on the 0 side has the same potential on both sides, no dielectric polarization occurs here. Therefore, the plate is set to H (5 V) while RW is set to H,
Here, the opposite dielectric separation occurs as described above. In this manner, data can be written to the ferroelectric capacitor 16. In this example, since two nonvolatile memories NVM are provided in one column, two NVMs are used.
, The data of the corresponding bit line is written.

When the power is turned on, the state of the SRAM 10 is set in accordance with the state of the dielectric isolation of the ferroelectric capacitor 16. Therefore, as shown in FIG. 12, while the word lines and bit lines are both at L level, the respective control lines are operated to perform the initialization as shown in FIGS.

After such initialization, R
Since W is set to L, the corresponding word line becomes H by designating the address, and this data is output to the data bus via the data supply unit.

[0028]

[0029]

[0030]

[0031]

As described above, the PL according to the present invention is
According to D, since the dielectric polarization of the ferroelectric capacitor can be used for nonvolatile data storage, a high voltage is not required for writing or the like, and the withstand voltage of the memory can be reduced.
The memory can be miniaturized, and the degree of integration can be increased.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a PLD.

FIG. 2 is a configuration diagram of a configuration memory that controls pass transistors.

FIG. 3 is a configuration diagram of a configuration memory that controls a logic circuit.

FIG. 4 is a circuit diagram showing a configuration of an embodiment of a nonvolatile memory according to the present invention.

FIG. 5 is a circuit diagram showing dielectric polarization of the ferroelectric capacitor of the example.

FIG. 6 is an explanatory diagram showing an operation of the ferroelectric capacitor of the example.

FIG. 7 is an explanatory diagram showing the operation of the ferroelectric capacitor of the example.

FIG. 8 is an explanatory diagram showing the operation of the embodiment.

FIG. 9 is an explanatory diagram showing the operation of the embodiment.

FIG. 10 is a configuration diagram of a memory cell using a nonvolatile memory according to an embodiment.

FIG. 11 is a chart showing a write operation of the memory cell.

FIG. 12 is a chart showing an initialization operation of the memory cell.

[Explanation of symbols]

 Reference Signs List 10 SRAM 12, 14, 18 Switch 16 Ferroelectric capacitor

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-165725 (JP, A) JP-A-2-30217 (JP, A) JP-A-3-66090 (JP, A) JP-A-3- 35499 (JP, A) JP-A-4-192173 (JP, A) JP-A-4-295690 (JP, A) JP-B-41-15895 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 19/098-19/23 G11C 11/22

Claims (3)

(57) [Claims] 1. A programmable logic device that operates according to a storage state of a configuration memory, the configuration memory comprising: a volatile memory circuit that outputs an opposite polarity to both ends thereof in accordance with an input signal and is stable; A ferroelectric capacitor connected to the volatile memory circuit and comprising a ferroelectric capacitor having a dielectric layer at both ends of the volatile memory circuit for supplying a potential difference generated due to dielectric polarization of the ferroelectric; A programmable logic device using a ferroelectric memory, comprising: 2. The programmable logic device according to claim 1,
In the memory device, both ends of the volatile memory circuit that output opposite polarities are provided.
A ferroelectric capacitor is connected to each through a switch.
Programmable logic that is connected
Device. 3. The programmable logic according to claim 2,
In the memory device, both ends of the volatile memory circuit that output the opposite polarity are connected.
Further comprising a switch connected thereto.
Ramable logic device.