JPH0457291A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To easily reload data at high speed by transferring the data stored in a memory cell to a dielectric capacitor when power supply is cut off, and transferring the data stored in the ferro-dielectric capacitor to the memory cell when a power source is turned on. CONSTITUTION:When power supply is cut off, the data is transferred from a memory cell 1 to ferrodielectric capacitors Z1 and Z0. When the power source is turned on, the data is transferred from the ferrodielectric capacitors Z1 and Z0 to the memory cell 1. Therefore, the semiconductor memory is operated as a non-volatile memory. Further, since the data can be reloaded by controlling the potentials of bit lines BL1 and BL0 and of a word line WL similarly to a normal SRAM, it can be easily executed at high speed differentially from a conventional EPROM or EEPROM etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a nonvolatile memory using a ferroelectric capacitor.

[Conventional technology]

Semiconductor storage devices include volatile memory, which can store information only while the power is turned on, and non-volatile memory, which can store information even after the power is turned off. is S RAM (Stat
ic Random Access Memory) and DRAM (Dynamic RAM), and as nonvolatile memory, Mask ROM (Mask Re
ad 0nly Memory).

PROM (Programmable ROM)
, Erasable PROM
, EEPROM (Electrical
yErasable and Programmable
e ROM), etc.

Among non-volatile memories, EPROM is an RO which can rewrite the memory contents as many times as RAM.
MOS-FET with a floating gate formed between the control gate and the channel (M
O3 type field effect transistor) is a radiation type transistor, which discharges the charge in the floating gate by irradiating it with ultraviolet rays to erase the memory contents, and then applies a high voltage between the control gate and the drain. Writing takes advantage of the fact that hot electrons generated by the breakdown phenomenon remain in the floating gate.

Further, EEFROM is a ROM whose stored contents can be electrically rewritten, and has the advantage that the contents can be erased without irradiation with ultraviolet rays.

[Problem to be solved by the invention]

However, the floating gate type MOS-
Writing and erasing information in a FET requires a time on the order of 100% and a high electric field on the order of 10'V/Ω.
The disadvantage of EEPROM is that it takes much longer to write information than normal RAM, so these conventional nonvolatile memories cannot write and erase information in the same cycle like normal RAM. I couldn't do it.

This invention was made by focusing on the unresolved problems of the conventional technology, and provides a nonvolatile memory that can easily and quickly rewrite information like a conventional SRAM. It is intended to.

[Means to solve the problem]

To achieve the above object, a semiconductor memory device according to claim (1) includes a memory cell in which a memory node is connected to a bit line via a switching transistor, and one electrode is connected to the memory cell via a pass transistor. and a ferroelectric capacitor whose other electrode is connected to the drive line, a power disconnection detection means for detecting that the power supply is disconnected, and a power disconnection detection means that detects that the power supply is disconnected. and drive line control means that starts up the drive line after a predetermined time has elapsed since the pass transistor control means turned on the pass transistor.

The semiconductor memory device according to claim (2) also includes a memory cell in which a memory node is connected to a bit line via a switching transistor, and one electrode is connected to the memory node via a pass transistor and the other electrode is connected to the bit line via a switching transistor. The electrodes include a ferroelectric capacitor connected to the drive line, a power-on detection means for detecting that the power is turned on, and a potential of the bit line when the power-on detection means detects that the power is turned on. bit line potential control means for setting the potential of the bit line to a low level; switching transistor control means for making the switching transistor conductive after a predetermined time has elapsed since the bit line potential control means has set the potential of the bit line to a low level; pass transistor control means for making the pass transistor conductive after a predetermined period of time has elapsed since the means has made the switching transistor conductive; and driveline control means for starting up.

The semiconductor memory device according to claim (3) includes a memory cell in which a memory node is connected to a bit line via a switching transistor, and one electrode is connected to the memory node via a pass transistor and the other electrode is connected to the bit line via a switching transistor. The electrode includes a ferroelectric capacitor connected to the drive line, a power cutoff detection means for detecting that the power supply is cut off, and a power cutoff detection means that conducts the pass transistor when the power cutoff detection means detects that the power supply is cut off. a first pass transistor control means for starting up the drive line after a predetermined period of time has elapsed since the first pass transistor control means made the pass transistor conductive; power-on detection means for detecting that the power has been turned on; bit line potential control means for setting the potential of the bit line to a low level when the power-on detection means detects that the power has been turned on; switching transistor control means for making the switching transistor conductive after a predetermined time has elapsed since the means has made the potential of the bit line low level; a second pass transistor control means that makes the transistor conductive; and a second drive line control means that starts up the drive line after a predetermined time has elapsed since the second pass transistor control means made the pass transistor conductive; Equipped with

[Effect]

In the invention set forth in claim (1), when the power cutoff detection means detects that the power supply is cut off, the pass transistor control means makes the pass transistor conductive, so that the potential of the storage node of the memory cell becomes ferroelectric. is supplied to one electrode of the body capacitor.

Since the drive line control means starts up the drive line after a predetermined time has elapsed since the pass transistor becomes conductive, the ferroelectric capacitor immediately after the potential of the storage node is supplied to one electrode of the ferroelectric capacitor The potential at the other electrode of the capacitor remains at a low level.

Therefore, if the potential of the storage node is at a low level, there will be no potential difference between the two electrodes of the ferroelectric capacitor, but if the potential of the storage node is at a high level, there will be no potential difference between the two electrodes of the ferroelectric capacitor. ferroelectric capacitor, and charge is accumulated in the ferroelectric capacitor.

Then, when a predetermined period of time has elapsed after the pass transistor became conductive, the drive line control means turns on the drive line, so that the potential of the other electrode of the ferroelectric capacitor becomes a high level.

At this time, if the potential of the storage node is at a low level, a potential difference occurs between the two electrodes of the ferroelectric capacitor, so a certain amount of charge is accumulated, and if the potential of the storage node is at a high level, the ferroelectric capacitor The potential difference between the two electrodes of the ferroelectric capacitor becomes zero, but the polarization of a ferroelectric material draws a hysteresis curve with respect to alternating current, so even if the potential difference becomes zero, a certain amount of charge is accumulated. maintain.

After that, even if the power supply is completely cut off and the drive line is at a low level, the polarization of the ferroelectric material draws a hysteresis curve with respect to the alternating current as described above, so the ferroelectric capacitor has only one electrode. Charges corresponding to the potential of the storage node supplied to the storage node are accumulated.

Since the charges that are ultimately accumulated in the ferroelectric capacitor are opposite to each other depending on the potential of the storage node, this means that information is stored in the ferroelectric capacitor, and even if the power is turned off, the charge remains strong. Charges stored in dielectric capacitors are stored for long periods of time (typically 10 years or more).

On the other hand, in the semiconductor memory device according to claim (2), when the power-on detection means detects that the power is turned on, the bit line potential control means lowers the bit line potential to a low level. After a predetermined period of time has elapsed since the switching transistor reaches the level, the switching transistor control means turns on the switching transistor, so that a low level potential is supplied to the storage node of the storage cell.

Then, after a predetermined period of time has elapsed since the switching transistor became conductive, the pass transistor control means makes the pass transistor conductive, so the potential of one electrode of the ferroelectric capacitor becomes a low level, and after that, the drive line control means starts driving When the line is turned on, the potential of the other electrode of the ferroelectric capacitor becomes high level.

Then, the potentials of the storage node and bit line change depending on the charge stored in the ferroelectric capacitor. In other words, the information stored in the ferroelectric capacitor is transferred to the storage node and bit line of the memory cell. That means that.

The semiconductor storage device according to claim (3) is the semiconductor storage device according to claim (1) and the semiconductor storage device according to claim (2).
Since it has the functions of both of the semiconductor storage devices described above,
When the power is turned off, the same effect as the semiconductor memory device according to the above claim (1) is obtained, and when the power is turned on, the same effect as the semiconductor memory device according to the above claim (2) is obtained.

(Example〕 Embodiments of the present invention will be described below based on the drawings.

1 to 6 are diagrams showing one embodiment of the present invention.

First, to explain the configuration, in FIG. 1, a memory cell 1 consisting of a flip-flop in which the input and output of a pair of inverters 2 and 3 are cross-connected to each other has two memory nodes Q and Qo, and - The storage node Q, on the other hand, is a transistor (NMO3) as a switching transistor.
The channel MO3 type transistor) Nl is connected to the bit line BL, and the other storage node Q0 is connected to the NMO3 type transistor Nl as a switching transistor.
2 to the bit line BL.

The gates of NMO3) transistors N and N2 are connected to the word line WL, and the gates of the transistors N and N2 are connected to the word line WL.
L is connected to an address decoder (not shown) which is activated when writing or reading data to or from the memory cell 1 at an arbitrary address.

Further, the bit lines B L and BL are connected to a sense amplifier (not shown) that operates when reading data stored in the memory cell 1 and a bit line driver that operates when writing data to the memory cell 1. (not shown) and NMO3) transistors N3 and N
4 and connected to ground GND through NM'
O3) The gates of transistors N3 and N4 are connected to equalization line EL.

One storage node Q1 is connected to one electrode of a ferroelectric capacitor Z via an NMOS transistor N5 as a pass transistor, and the other storage node Q0 is connected via an NMOS transistor N6 as a pass transistor. The ferroelectric capacitor Z0 is connected to one electrode of the ferroelectric capacitor Z0, and the other electrode of the ferroelectric capacitor Z0 is connected to the drive line DL.

Furthermore, the gates of the NMOS transistors Ns and N6 are connected to the control line CL.

Here, the memory cell 1 has the following characteristics due to the characteristics of a flip-flop.
It is a memory that stores 1 bit of information in two stable states in which the storage nodes Q and Qo take values in opposite phases to each other, and can hold information while the power supply VCC is supplied. After the power supply VCC is cut off, storage nodes Q and Q.

Since the state cannot be maintained, the information will be lost and will not be reproduced even if the power is turned on again.

In other words, the memory cell 1 alone cannot function as a nonvolatile memory.

On the other hand, ferroelectric capacitors Z1 and Z. As shown in Figure 2, when a positive voltage is gradually applied from a state where there is no charge and the voltage applied between both electrodes is zero (point A), the domains arranged in the applied electric field become The charge increases rapidly, and for voltages above a certain value, the charge increases relatively smoothly, and curve A
-Draw B (.

Since the polarization of a ferroelectric material draws a hysteresis curve with respect to an alternating electric field, even if the voltage is gradually lowered from the state at point B and the potential difference between the electrodes becomes zero, the charge will not become zero and the residual Takes the state of polarization point C.

To make the charge zero, it is necessary to apply a voltage in the negative direction, and if the voltage in the negative direction is further increased, the charge also increases in the opposite direction, drawing curves B-, C, -D, and D If we gradually increase the voltage from a point to zero the potential difference between the electrodes,
If the state of the remanent polarization point E is taken and the voltage is further increased, a curve D-E-B will be drawn.

In other words, ferroelectric capacitors Z and Z. When a voltage is applied and then the applied voltage is reduced to zero, it takes on either the state of the remanent polarization point C or E, so it is possible to store 1 bit of information depending on these two states, and that information It can also be used as nonvolatile memory because it can be retained for a very long time (usually 10 years or more).

And control line CL and drive line D
L is connected to the controller 4 that operates when the power supply VCC is cut off, and is connected to the equalization line EL and the word line W.
L, control line CL and drive line D
L is connected to a controller 5 that is activated when the power supply VCC is turned on.

FIG. 3 is a circuit diagram showing an example of the controller 4. As shown in FIG.

That is, the controller 4 includes a power supply detection circuit 4a that outputs a high-level signal when the power supply VCC falls below a predetermined voltage (for example, 4V), and a control line CL in response to the output of this power supply detection circuit 4a. A control line driver 4b to start up, and a dry line driver 4 to which the output of the control line driver 4b is supplied via a delay circuit 4d and starts up the drive line DL.
It is equipped with c.

The power supply detection circuit 4a includes a plurality of stages (two stages in this embodiment) of PMOs whose gates are supplied with the potential on their drain side.
3) Transistor (P channel MO8 type transistor) P
1 and P2, and odd-numbered stages (three stages in this embodiment) of inverters 6a, 6b, and 6c connected in series, and the first inverter 6a is connected to the power supply VCC via PMO3) transistors P+ and P2. is supplied, and the output of the last inverter 6c is the output of the power supply detection circuit 4a.

Then, while the power supply vce is turned on, that is, the power supply V
When CC exceeds a predetermined voltage (for example, 4V), the PMO3) transistor of the inverter 6a is turned off and the NMO3
) transistor is turned on and the output of the power supply detection circuit 4a becomes low level (ground GND level), while the power supply VCC
When the inverter 6 is disconnected and the potential becomes lower than the predetermined potential, the inverter 6
The sizes (channel width and channel length) of the PMO3I transistors P1 and P2 are selected so that the PMOS transistor a is turned on, the NMO3I transistor is turned off, and the output of the power supply detection circuit 4a is at a low level.

The control line driver 4b is composed of a plurality of stages (two stages in this embodiment) of inverters 7a and 7b connected in series, and the output of the power detection circuit 4a is supplied to the input side of the inverter 7a. , the output of the inverter 7b is supplied to the control line CL.

The dry pline driver 4c also includes a plurality of stages (two stages in this embodiment) of inverters 8a and 8b connected in series, and on the input side of the inverter 8a,
Control line driver 4b via delay circuit 4d
The output of the inverter 8b is supplied to the drive line DL.

The delay circuit 4d also includes a resistor R1 interposed between the inverters 7b and 8a, and a ground G on the input side of the inverter 8a.
The output of the control line driver 4b is connected to the drive line 4c with a delay time of about 10 to 20 ns, although it varies slightly depending on the size of the ferroelectric capacitor 2 and Zo. Allow it to be entered. Therefore, the resistance R,
is about Ω in number, and the capacitor C1 has a size of about 10PF to 20pF.

FIG. 4 is a circuit diagram showing an example of the controller 5. FIG.

That is, the controller 5 includes a power-on reset circuit 5a that transmits a low-level signal that continues for a predetermined period of time immediately after power is turned on, and this power-on reset circuit 5.
an equalize line driver 5b that receives the output of the equalize line driver 5b and raises the equalize line EL; a word line driver 5C that receives the output of the equalize line driver 5b via a delay circuit 5d and raises the word line WL; A control line driver 5e is supplied with the output of the word line driver 5C via a delay circuit 5f and starts up the control line CL, and a control line driver 5e is supplied with the output of the control line driver 5e via a delay circuit 5h and drives It is equipped with a dry line driver 5g for starting up the line DL.

The power-on reset circuit 5a is an oscillation circuit that includes a PMO transistor P3 whose gate is supplied with the potential on its drain side, and odd-numbered stages (three stages in this embodiment) of inverters 10a, 10b, and 10C connected in series. 10 and
a delay circuit 11 having a resistor Rt and a capacitor C2;
NMO3) transistor N, and inverters 12a, 12b, 1 of even number stages (four stages in this embodiment) connected in series.
2c and 12d.

In the oscillation circuit 10, a power supply V is connected to the input side of the first inverter 10a via the PMO3l-transistor P3.
CC is supplied, and the output of the last inverter 10c becomes the output of the oscillation circuit 10, and the power supply ■. , the PMO of the inverter 10a is lower than the predetermined potential of the inverter 10a.
3) When the transistor is on, the NMO3) transistor is turned off and the output of the oscillation circuit 10 becomes the power supply VCC, but when the power supply VCC rises and exceeds a predetermined voltage, the PMO3) transistor of the inverter and the bark 10a is turned off. The NMOS transistor is turned on and the output of the oscillation circuit 10 is grounded G.
The size of PMO3) transistor P3 is selected so that it becomes ND.

The output of the oscillation circuit 10 is an equalization line driver 5b.
It is also supplied to the input side of the NMOS transistor N7 of the oscillation circuit 12 via the delay circuit 11, and the output of the oscillation circuit 10 is delayed several times to the gate of the NMOS transistor N7 of the oscillation circuit 12. The sizes of the resistor R2 and capacitor C2 of the delay circuit 11 are selected so that the input signal is inputted to the input signal.

In the oscillation circuit 12, NMO3) transistor N7
Power supply VCC is supplied to the input side of the first inverter 12a through the inverter 12a, and the output of the last inverter 12d is the output of the oscillation circuit 12.

Therefore, the output of the power-on reset circuit 5a is the output of the oscillation circuits 10 and 12, that is, the output of the inverters 10c and 1
Determined by the output of 2d.

However, for example, even if the output of inverter 10c is high level, if the output of inverter 12d is low level,
The output of the power-on reset circuit 5a may be pulled by the inverters 10c and 12d, and the output may become unstable.

Therefore, in this embodiment, the higher output of the outputs of the inverters 10c and 12d is output from the power-on reset circuit 5a.
The inverters 10c and 12
The size (channel width/channel length) of each transistor constituting d is selected.

That is, even when the PMOS transistor of the inverter 10c is on and the NMOS transistor of the inverter 12d is on, the on-resistance of the PMOS transistor is reduced (channel width/channel length is increased), and the NMOS transistor of the NMOS transistor is reduced. Increase on-resistance
(Small the channel width/channel length), the output of the power-on reset circuit 5a becomes the power supply VCC, and conversely, the NMOS transistor of the NMO5) transistor of the inverter 10c is turned on, and the NMOS transistor of the NMO3) transistor 12d is turned on. If the on-resistance of the NMOS transistor is reduced and the on-resistance of the PMOS transistor is increased even when
The output becomes the power supply VCC.

Note that the output tension occurs between the control line driver 4b of the controller 4 and the control line driver 5e of the controller 5, and between the control line driver 4b of the controller 4 and the control line driver 5e of the controller 5.
This also occurs between the dry pline driver 4c of the controller 5 and the dry pline driver 5g of the controller 5, but as described above, it can be solved by adjusting the size of the transistor.

The output of the power-on reset circuit 5a is connected to an equalization line driver 5 composed of one inverter.
The output of the equalize line driver 5b is supplied to the equalize line EL, and is also supplied to the word line driver 5c via a delay circuit 5d.
is supplied to.

Furthermore, the output of the word line driver 5c is supplied to the word line WL, and is also supplied to the control line driver 5e via the delay circuit 5f, and the output of the control line driver 5e is supplied to the control line CL. At the same time, it is supplied to the dry pline driver 5g via the delay circuit 5h, and the output of the dry plyline driver 5g is supplied to the drive line DL.

Note that the delay time of each delay circuit 5d, 5f, and 5h is Ions to 20, similarly to the delay circuit 4d of the controller 4.
Resistors R configuring these delay circuits 5d, 5f, and 5h are set such that the delay time is approximately 1.0 ns. Select R4 and Rs and capacitors Cs, Ca and C3.

Next, the operation of this embodiment will be explained.

Note that writing and reading data to and from the memory cell 1 is similar to that of a conventional SRAM, and will therefore be briefly described.

That is, in order to store data in the memory cell 1, an address decoder (not shown) is driven to raise the word line WL, and a bit line driver (not shown) is driven to raise one of the bit lines BL and BL. One potential is set to high level and the other potential is set to low level.

When the word line WL rises, NMO3) transistors N1 and N are turned on, so that the storage node Q and the bit line BL become conductive, and the bit line B L
The potential of t is supplied to the storage node Q, and the storage node Q
, and bit line B L .

The bit line BL becomes conductive, and the potential of the bit line BL is supplied to the storage node Q0.

Then, the potential of one of storage nodes Q1 and Q becomes high level, and the potential of the other becomes low level.

Thereafter, by lowering the word lines W and L and turning off the NMOS transistors N and N2, the storage node Q and the bit line BL are separated, and the storage node Qo and the bit line BLo are disconnected. Even when separated, as long as power supply VCC is supplied to inverters 2 and 3 of memory cell 1, inverters 2 and 3 restrict each other's input/output. becomes a stable state, and data is stored in the memory cell 1.

Further, in order to read data stored in the memory cell 1, the word line WL is raised and the potentials of the bit lines B L + and BL are set to a low level.

Then, NMO3) transistors N1 and N2 are turned on, and the storage node Q and the bit line BL become conductive, and the storage node Qo and the bit line BL0 become conductive, so that the storage nodes Q1 and Q become conductive. Since a potential difference occurs between the bit lines BL and B Lo depending on the potential difference between the bit lines BL and BL o, if this potential difference is detected by a sense amplifier (not shown),
Data stored in memory cell 1 is read out.

Next, the operation when the power supply VCC that has been turned on is turned off will be described.

That is, in the power supply detection circuit 4a of the controller 4,
Since the power supply VCC is supplied to the input side of the inverter 6a via the two PMO3) transistors PI and P2, the input side of the inverter 6a is supplied with a predetermined voltage (PMO3) transistor P and P2 from the power supply VCC to the input side of the inverter 6a. A potential dropped by the threshold voltage (total bone) is supplied.

Then, while the power supply VCC is supplied, PMO3)
The sizes of the PMOS transistors P and P2 are selected so that even if the voltage drops across the transistors P1 and P2, the potential on the input side of the inverter 6a remains at a high level.
The output of inverter 6a becomes low level.

Therefore, the output of the inverter 6b is at a high level, the output of the inverter 6c is at a low level, and the output of the power supply detection circuit 4a is at a low level.

Therefore, the output of this power supply detection circuit 4a is connected to the inverter 7a.
and control line driver 4 that rotates countersunk at 7b.
Since the output of b is also at a low level, the control line C
L does not rise and NMOS transistors N5 and N6
maintains an off state, and the storage node Q and one electrode of the ferroelectric capacitor ZI and the storage node Q0 and one electrode of the ferroelectric capacitor Z0 remain disconnected. .

Furthermore, if the output of the control line driver 4b is at a low level, the input of the dry line driver 4C also remains at a low level, so the input is connected to the inverters 8a and 8b.
The output of the dry line driver 4c, which reverses the plate rotation, is also at a low level, and the drive line DL does not rise.

Therefore, the potentials of the other electrodes of the ferroelectric capacitors Z and Zo are at a low level;
1 and Z. Since no potential difference is generated between the two electrodes of the ferroelectric capacitors Z and Zo, the charges of the ferroelectric capacitors Z and Zo do not vary.

If the power supply ■ce is disconnected in such a state, the power supply V
When the potential of CC gradually decreases and becomes below a predetermined potential, the potential at the input side of inverter 6a becomes a low level, and the output of inverter 6a becomes power supply VCC.

Then, the output of the inverter 6b becomes the ground GND, and the output of the inverter 6c becomes the power supply VCC, but since the power supply VCC is gradually decreasing, the output of the inverter 6c is also gradually decreasing.

Therefore, the output of the power supply detection circuit 4a rises immediately after the power supply VCC is cut off, as shown in FIG. It becomes a pulse-like waveform that continues until it drops completely.

The output of the control line driver 4b to which the output of the power supply detection circuit 4a is supplied has a waveform that is in phase with the output of the power supply detection circuit 4a, as shown in FIG. 5(b).
Control line CL rises.

When the control line CL rises, the NMo5 transistors N5 and N6 turn on, and the storage node Q1 and one electrode of the ferroelectric capacitor Zl are electrically connected, and the storage node Q and one electrode of the ferroelectric capacitor z0 are connected. There is continuity between the two.

On the other hand, the dry line driver 4c includes a delay circuit 4d.
Since the output of the control line driver 4b is supplied through the control line driver 4b, the output of the dry ply line driver 4c rises after the output of the control line driver 4b, as shown in FIG. 5(C).

Therefore, immediately after the control line CL rises, the drive line DL does not rise, and the potentials of the other electrodes of the ferroelectric capacitors Z1 and Zo are at a low level.

Here, for example, assume that the potential of the storage node Q is at a high level and the potential of the storage node Q0 is a low level (the data stored in the memory cell 1 has a logical value of ``'1'''').
Ferroelectric capacitors Z1 and Z.

Considering the electrodes of one example of a memory cell as a reference, the memory node Q
A positive voltage is applied to the ferroelectric capacitor ZI to which the potential of is supplied, and therefore, the charge at point B in FIG. 2 is accumulated in the ferroelectric capacitor Z1.

On the other hand, ferroelectric capacitor Z. Since no potential difference occurs between the two electrodes of , the charge of the ferroelectric capacitor Z0 maintains its previous state, which is the point A in Figure 2.

Take the state of point C or point E.

Then, as shown in FIGS. 5(b) and (C), after a predetermined period of time has elapsed since the control line CL rose, the drive line DL rises, and the potential of the other electrodes of the ferroelectric capacitors Z and Zo rises. reach a high level.

Then, the potential difference between the two electrodes of the ferroelectric capacitor Z becomes zero, but as shown in Figure 2, the polarization of the ferroelectric draws a hysteresis curve with respect to the alternating electric field, so the ferroelectric capacitor The charge at the residual polarization point C remains in z1.

On the other hand, since one electrode of the ferroelectric capacitor Z0 is supplied with the potential of the storage node Q0, that is, a low level potential, when the drive line DL rises, a negative voltage is applied to the ferroelectric capacitor Z0. is applied, and therefore, the charge at the second point is accumulated in the ferroelectric capacitor Z0.

As time further elapses, as shown in FIG. 5, each waveform gradually decreases as the power supply Vcc decreases, and the potentials of the control line CL and drive line DL become low levels.

Further, the power supply VCC supplied to the inverters 2 and 3 of the storage cell 1 also decreases, but when the control line CL becomes low level, the NMO3) transistors N and N6 are turned off, and the storage node Q is turned off.

and the ferroelectric capacitor Z1, and the storage node Q
o and the ferroelectric capacitor Z0 are separated.

Then, when the potential of the drive line DL becomes a low level, the potential of the other electrode of each of the ferroelectric capacitors z1 and Zo becomes a low level. The potential difference becomes zero.

Therefore, the charge at the remanent polarization point C shown in FIG. 2 remains accumulated in the ferroelectric capacitor zI, and as the ferroelectric capacitor z0 moves from the second polarization point to the remanent polarization point E, its The dielectric capacitor Z0 has a residual polarization point E
This means that a charge of .

Note that if the potential of the storage node Q1 is at a low level and the potential of the storage node Q0 is at a high level (the data stored in the memory cell 1 has a logic value of "0"), the ferroelectric capacitor Z
The charge at the remanent polarization point E is accumulated in the ferroelectric capacitor Z0, and the charge at the remanent polarization point C is accumulated in the ferroelectric capacitor Z0.

In other words, since the charges stored in the ferroelectric capacitors ZI and zo have opposite values, the 1-bit information stored in the memory cell 1 is transferred to the ferroelectric capacitors Z1 and Zo. It means that it was done.

And ferroelectric capacitors C and Z. The charge accumulated in these ferroelectric capacitors C and Z is stored for a very long time (generally more than 10 years) even if the power supply VCC is completely disconnected.

becomes essentially non-volatile memory.

Next, the operation when the power is turned on again will be explained.

That is, when the power is turned on and the potential of the power supply ■cC rises,
In the power-on reset circuit 5a of the controller 5, the potential at the input side of the inverter 10a of the oscillation circuit 10 supplied via the transistor P3 (PMO 3) also gradually rises, but until the potential rises sufficiently, it is determined to be at a low level. Therefore, the PMO3I transistor of the inverter 10a is on and the NMOS transistor is off, and its output is the power supply V CC%.The output of the inverter 10b is the ground GND,
The output of the inverter 10c becomes the power supply VCC.

And power supply ■. When the potential of , further increases and the potential of the input side of the inverter 10a becomes high level, the PMO3 transistor of the inverter 10a is turned off and the NMO3) transistor is turned on, its output is connected to the ground GND, and the output of the inverter 10b is connected to the power supply VCC. % The output of the inverter 10c becomes the ground GND.

Therefore, as shown in FIG. 6(a), the output waveform of the oscillating circuit 10 immediately after the power is turned on rises slightly from a low level, then becomes a low level again, and thereafter remains at a low level.

On the other hand, in the oscillation circuit 12, the output of the oscillation circuit 10 is supplied to the gate of the NMO3) transistor N7 via the delay circuit 11, so that the NMO3) transistor N7 is initially off and the input side of the inverter 12a is The potential is at a low level.

The oscillation circuit 12 includes an even-numbered stage inverter 12a,
12b, 12c and 12d, its output is at a low level.

Thereafter, when the delay time in the delay circuit 11 has elapsed, NM
O3) Since the output of the oscillation circuit 10 is supplied to the gate of the transistor N, NMO3I-transistor N is turned on, and the power supply ■cC is supplied to the input side of the inverter 12a, and the output of the inverter 12a is connected to the ground GND. Because it will be,
The output of the final stage inverter 12d is the power supply ■. , becomes.

The output of the inverter 12d is also supplied to the delay circuit 11, and when the output of the inverter 12d becomes high level, the capacitor C2 is already charged, so the output of the oscillation circuit 10 becomes low level. Even though, NMO
3I - transistor N.

The gate potential of is maintained at a high level.

Therefore, as shown in FIG. 6, etc., the output waveform of the oscillation circuit 12 rises with a delay of the delay time caused by the delay circuit 11 from the rise of the output of the oscillation circuit 10, and thereafter maintains a high level.

Since the output of the power-on reset circuit 5a is the logical sum of the output of the oscillation circuit 10 and the output of the oscillation circuit 12, it continues for a predetermined period of time immediately after the power is turned on, as shown in FIG. 6(C). This results in a negative pulse-like waveform.

Therefore, since the output of the equalization line driver 5b has the opposite phase to the output of the power-on reset circuit 5a,
As shown in Figure (d), the waveform rises immediately after the power is turned on, maintains a high level for the delay time of the delay circuit 11, and then falls, and when this output waveform is at a high level, the equalize line EL rises. Te, NMO
3) Transistors N3 and N4 are turned on.

Then, the bit lines BL+ and BL are grounded GN
D, so those bit lines BL1 and B
The potential of L becomes a low level.

On the other hand, the output of the equalize line driver 5b is also supplied to the word line driver 5c via the delay circuit 5d, so the output of the word line driver 5c is
As shown in Figure (e), the equalization line driver 5b
When the output of the word line W rises, it rises with a delay of the delay time of the delay circuit 5d, maintains the high level for the delay time of the delay circuit 11, and then falls.When this output waveform is at the high level, the word line W
When L rises, NMO3) transistors NI and N
2 is turned on.

Then, the bit line BL and the storage node Q.

and the bit line BL and the storage node Q
0 is electrically connected.

Furthermore, since the output of the word line driver 5C is also supplied to the control line driver 5e via the delay circuit 5f, the output of the control line driver 5e is as shown in FIG. 6(f). When the output waveform of the word line driver 5C rises with a delay of the delay time caused by the delay circuit 5f, and then falls after maintaining the high level for the delay time of the delay circuit 11, and this output waveform is at a high level. The control line CL rises and the NMOS transistors N and Nh are turned on.

Then, one electrode of the ferroelectric capacitor Z1 and the storage node Q1 are electrically connected, and one electrode of the ferroelectric capacitor Z0 and the storage node Q0 are electrically connected, but at this time,
NMO3) transistor N.

and N2 are on, and the bit line BL
Since the potentials of , and BL are at a low level, the potentials of the ferroelectric capacitors Z1 and Z. The potential of one electrode of each becomes a low level.

Since the output of the control line driver 5e is also supplied to the dry line driver 5g via the delay circuit 5h, the output of the dry line driver 5g is as shown in FIG. After the output of the bar 5e rises, it rises with a delay of the delay time caused by the delay circuit 5h, maintains a high level for the delay time of the delay circuit 11, and then falls.
When this output waveform is at a high level, the drive line D
L rises, the potential of the other electrode of each of ferroelectric capacitors ZI and Zo becomes high level, and these ferroelectric capacitors Z1 and Z. This means that a negative voltage is applied to.

At this time, the charge accumulated in the ferroelectric capacitor Z1 is the charge at the residual polarization point C, and the ferroelectric capacitor Z0
If the charge stored in is the charge at the residual polarization point E (the data stored in the ferroelectric capacitors Z1 and Zo has a logical value of "°1"), the bit line BL becomes the point shown in FIG. Since the charge on the bit line BL changes from point C to point E, the potential of the bit line BL becomes a high level and the potential of the bit line BL becomes a low level. and BL, the potential difference between them is latched by a sense amplifier.

As a result, the potential of storage node Q becomes high level and the potential of storage node Q0 becomes low level, so that memory cell 1
This means that the logical value "1" is stored in the memory.

Furthermore, the charge accumulated in the ferroelectric capacitor Z is the charge at the remanent polarization point E, and the charge accumulated in the ferroelectric capacitor Z0 is the charge at the remanent polarization point C (ferroelectric capacitor Z and If the data stored in Zo is a logical value of "0''), the charge on the bit line BL changes from point E to the dot shown in FIG. 2, and the charge on the bit line BLo changes from point C to dot. From, contrary to the above, storage node Q1
Since the potential of the storage node Q0 becomes a low level and the potential of the storage node Q0 becomes a high level, it means that a logical value "0" is stored in the memory cell 1.

Then, when the delay time by the delay circuit 11 has elapsed and the output of the power-on reset circuit 5a becomes high level, the sixth
As shown in Figures (d), (e), (6), the equalize line EL, word line WL, control line CL, and drive line DL fall in sequence.

Then, the NMOS transistors N3 and N4 are turned off, and the bit lines BL and BLo are disconnected from the ground GND. , storage node Q0 and bit line BL are disconnected, NMO3) transistors N and N6 are turned off, and between storage node Q and ferroelectric capacitor ZI,
Then, storage node Q0 and ferroelectric capacitor Z0 are separated, and ferroelectric capacitors Z1 and Z
The potential of the other electrode of each electrode becomes a low level.

In other words, if some time passes after the output of the power-on reset circuit 5a becomes high level, the normal SRAM
Similarly, bit line BL,.

The data in the memory cell 1 can be read and written by B Lo and the word line WL.

In this way, with the configuration of this embodiment, when the power is cut off, the ferroelectric capacitors Z1 and Z are removed from the memory cell 1.

Data is transferred to the memory cell 1, and when the power is turned on, data is transferred from the ferroelectric capacitors ZI and Zo to the memory cell 1, so it operates as a nonvolatile memory.

Furthermore, data can be rewritten by controlling the potentials of the bit lines BL, , BL, and word line WL, as in a normal SRAM, and therefore, unlike conventional EPROMs, EEPROMs, etc., data can be rewritten easily and at high speed.

In this embodiment, the power supply detection circuit 4a corresponds to the power cutoff detection means, and the control line driver 4b and the control line CL correspond to the pass transistor control means (
The dry line driver 4c and the delay circuit 4d correspond to the drive line control means (first drive line control means),
The power-on reset circuit 5a corresponds to power-on detection means, the equalize line driver 5b, equalize line EL and NMO3) transistors N3 and N4 correspond to bit line potential control means, and the word line driver 5c, word line WL and The delay circuit 5d corresponds to switching transistor control means, the control line driver 5e, control line CL and delay circuit 5f correspond to pass transistor control means (second pass transistor control means), and the dry line driver 5g and delay circuit 5h corresponds to the drive line control means (second drive line control means).

〔Effect of the invention〕

As explained above, according to the present invention, when the power is turned off, the data stored in the memory cell is transferred to the ferroelectric capacitor, and when the power is turned on, the data stored in the ferroelectric capacitor is transferred to the ferroelectric capacitor. Since the data is transferred to the memory cell, it operates as a non-volatile memory, and data can be rewritten easily and quickly.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a graph showing polarization characteristics of a ferroelectric material, FIG. 3 is a circuit diagram showing an example of a controller that operates when the power is turned off, and FIG. Figure 4 is a circuit diagram showing an example of a controller that operates when the power is turned on, Figure 5 is a time chart showing internal waveforms and output waveforms of the controller shown in Figure 3, and Figure 6 is a circuit diagram of the controller shown in Figure 4. 5 is a time chart showing internal waveforms and output waveforms. ■...Storage cell, 4,5...Controller, 4a.
...Power supply detection circuit, 4b, 5e... Control line driver, 4c, 5g... Dry line driver, 4d, 5d, 5 f, 5h, 11-... Delay circuit,
5a... Power-on reset circuit, 5b... Equalize line driver, 5C... Word line driver, 10.12... Transmission circuit, 2. ．． 2. ...Ferroelectric capacitor, Q,,Q,...Storage node, BL,...
BL. ...Bit line, CL...Control line,
DL...drive line, WL...word line,
EL...Equalize line, N, -N7...NMO
3) Transistor, P, ~P,...PMO3 transistor 4cPler-f7 ('A'' 74bar)

Claims (3)

[Claims] (1) A memory cell in which a memory node is connected to a bit line via a switching transistor, and a ferroelectric cell in which one electrode is connected to the memory node via a pass transistor and the other electrode is connected to a drive line. A capacitor, a power cutoff detection means for detecting that the power supply is cut off, a pass transistor control means for making the pass transistor conductive when the power cutoff detection means detects that the power supply is cut off, and the pass transistor control means. A semiconductor memory device comprising: drive line control means for starting up the drive line after a predetermined period of time has elapsed since the means turned on the pass transistor. (2) A memory cell whose memory node is connected to a bit line via a switching transistor, and a ferroelectric whose one electrode is connected to the memory node via a pass transistor and the other electrode is connected to a drive line. a capacitor, a power-on detection means for detecting that the power is turned on, and a bit-line potential control means that sets the potential of the bit line to a low level when the power-on detection means detects that the power is turned on. , switching transistor control means for making the switching transistor conductive after a predetermined time has elapsed since the bit line potential control means lowered the potential of the bit line to a low level;
pass transistor control means for making the pass transistor conductive after a predetermined period of time has passed since the switching transistor control means has made the switching transistor conductive; A semiconductor memory device comprising: drive line control means for starting up the drive line. (3) A memory cell in which a memory node is connected to a bit line via a switching transistor, and a ferroelectric cell in which one electrode is connected to the memory node via a pass transistor and the other electrode is connected to a drive line. a capacitor, a power cutoff detection means for detecting that the power supply is cut off, a first pass transistor control means that makes the pass transistor conductive when the power cutoff detection means detects that the power supply is cut off; a first drive line control means for starting up the drive line after a predetermined period of time has elapsed since the first pass transistor control means has made the pass transistor conductive; and a power-on detection means for detecting that the power has been turned on. , a bit line potential control means that sets the potential of the bit line to a low level when the power-on detection means detects that the power is turned on, and a bit line potential control means that sets the potential of the bit line to a low level a switching transistor control means for making the switching transistor conductive after a predetermined time has elapsed from the switching transistor; and a second pass transistor control means for making the pass transistor conductive after a predetermined time has elapsed since the switching transistor control means has made the switching transistor conductive. and second drive line control means that starts up the drive line after a predetermined time has elapsed since the second pass transistor control means made the pass transistor conductive. .