JPH08147983A - Ferroelectric memory device - Google Patents

Abstract

PURPOSE: To prevent malfunction of a ferroelectric memory device by reducing influence of an in-print effect of a ferroelectric capacitor. CONSTITUTION: In the ferroelectric memory device of a 1T1C type in which a memory cell is constituted with one transistor and one capacitor per one bit, a capacity value of a dummy memory cell capacitor DC0, that is, its area is decided in accordance with a capacity characteristic when a regular memory cell capacitor C0 is operated in both poles repeatedly until a capacitor characteristic is not varied any longer. Moreover, not only the regular memory cell capacitor C0 but also the dummy memory cell capacitor DC0 is operated in a both poles by making dummy memory cell capacitor reset voltage RSTDT as not ground voltage but power source voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device.

[0002]

2. Description of the Related Art In recent years, a ferroelectric memory device has been devised which realizes non-volatility of stored data by using a ferroelectric material for a capacitor of a memory cell. The ferroelectric capacitor has a hysteresis characteristic, and remnant polarization having different polarities depending on history remains even when the electric field is zero. A nonvolatile memory device is realized by expressing stored data by a remanent polarization of a ferroelectric capacitor.

US Pat. No. 4,873,664 discloses two types of ferroelectric memory devices. First
Memory cell is composed of one transistor and one capacitor (1T1C) per bit, for example, 256 main body memory cells (normal cells)
One dummy memory cell (reference cell) is provided for each. In the second type, memory cells are provided with 2 transistors and 2 bits per bit without providing dummy memory cells at all.
It is composed of a capacitor (2T2C), and a pair of complementary data is stored in a pair of ferroelectric capacitors.

Ferroelectric materials forming the capacitor include potassium nitrate (KNO ₃ ), PLZT (PbLa _{2
O 3 -ZrO 2 -TiO 2),} PZT (PbTiO 3 -
PbZrO ₃ ) and the like are known. According to PCT International Publication WO93 / 12542, a ferroelectric material suitable for a ferroelectric memory device and having extremely less fatigue than PZT is also known.

1T of the above-mentioned US Pat. No. 4,873,664
According to the 1C type ferroelectric memory device, the dummy memory cell capacitor has at least twice the capacitance of the main body memory cell capacitor, that is, at least twice the area. Moreover, the main body memory cell capacitor returns to the original polarization state after the polarization is inverted or retains the original polarization state without being inverted according to the stored data at the time of reading. On the other hand, the dummy memory cell capacitor is
The original polarization state is maintained without being inverted regardless of the stored data in the main body memory cell. That is, the main body memory cell capacitor operates the voltage applied between the electrodes with both positive and negative poles, while the dummy memory cell capacitor operates the voltage applied between the electrodes with one pole at all times. The applied voltage of the cell plate electrode of the main body memory cell capacitor, the applied voltage of the cell plate electrode (dummy cell plate electrode) of the dummy memory cell capacitor, the applied voltage of the word line connected to the gate electrode of the main body memory cell transistor, and the dummy The applied voltage to the word line (dummy word line) connected to the gate electrode of the memory cell transistor was 5 V, which was equal to the power supply voltage. Moreover, regardless of the stored data of the main body memory cell, the voltage of the word line and the dummy word line is lowered after the voltage of the cell plate electrode of the main body memory cell capacitor is lowered, and the voltage of the word line and the dummy word line is lowered. The voltage of the cell plate electrode of the dummy memory cell capacitor is lowered at the same time when the voltage is lowered.

[0006]

In the conventional 1T1C type ferroelectric memory device, since the dummy memory cell capacitor is operated in one pole as described above, the hysteresis of the dummy memory cell capacitor is reduced during use due to the so-called imprint effect. A large change occurs in the characteristics. As a result, the operation margin of the ferroelectric memory device becomes small, and malfunction occurs. Also,
Since the dummy memory cell capacitor having an area many times larger than that of the main body memory cell capacitor is provided as the reference cell, the capacitance value of the dummy memory cell capacitor may vary due to manufacturing variations, and the operation margin may decrease.

[0007] Regardless of whether it is the 1T1C type or the 2T2C type, when the power supply voltage decreases, the charge due to the remanent polarization of the memory cell capacitor decreases, and the operation margin decreases. . Further, when the logic voltage “H” is rewritten to the memory cell capacitor, the rewrite voltage of the memory cell capacitor is lower than the potential of the gate electrode of the memory cell transistor by the threshold voltage Vt of the transistor, so-called “Vt”. Since the “drop” occurs, there is a problem that the charge due to remanent polarization is reduced and the operation margin is reduced.

An object of the present invention is to increase the operation margin of the ferroelectric memory device so as to prevent malfunction and realize stable operation and low voltage operation.

[0009]

In order to achieve the above object, the inventions of claims 1 to 3 repeat the main body memory cell capacitor in the ferroelectric memory device of 1T1C type until the capacitance characteristic no longer changes. The capacitance value of the dummy memory cell capacitor, that is, its area, is determined according to the capacitance characteristic when the dummy memory cell capacitor is operated. In order to effectively suppress the imprint effect, not only the main body memory cell capacitor but also the dummy memory cell capacitor are operated in both polarities.

The present invention is applied to a main body memory cell capacitor so that a dummy memory cell capacitor having an area substantially equal to that of the main body memory cell capacitor can be adopted in a 1T1C type ferroelectric memory device. The voltage and the voltage applied to the dummy memory cell capacitor are made different. Specifically, when reading data or rewriting data,
The voltage applied to the cell plate electrode of the main body memory cell capacitor is made different from the voltage applied to the cell plate electrode of the dummy memory cell capacitor.

According to the present invention, the 1T1C type or 2T2C type ferroelectric memory device is applied to the cell plate electrode of the memory cell capacitor at the time of reading data so as to increase the read charge amount of the memory cell capacitor. At least one of the applied voltage and the voltage applied to the cell plate electrode of the memory cell capacitor at the time of rewriting data is set to be higher than the power supply voltage.

According to the fourteenth and fifteenth aspects of the present invention, the Vt of the memory cell transistor at the time of rewriting data in the 1T1C type or 2T2C type ferroelectric memory device.
In order to prevent the drop, the word line connected to the gate electrode of the memory cell transistor is selected by the logic voltage “H” or “L”, and then the word line is set to the floating state, so that the self-boot of the rewriting voltage is performed. It was realized.

According to the sixteenth and seventeenth aspects of the present invention, in the 1T1C type ferroelectric memory device, the body memory cell transistor is rewritten when the data of the body memory cell is rewritten so as to increase the rewrite charge amount of the body memory cell capacitor. The order of lowering the voltage of the word line connected to the gate electrode and lowering the voltage of the cell plate electrode of the main body memory cell capacitor is changed according to the data stored in the main body memory cell.

According to the eighteenth and nineteenth aspects of the present invention, in the 1T1C type ferroelectric memory device, the dummy memory cell transistor is easily reinitialized so that the state of the dummy memory cell capacitor can be easily initialized. Changing the order of the voltage fall of the dummy word line connected to the gate electrode of the dummy memory cell and the voltage fall of the cell plate electrode (dummy cell plate electrode) of the dummy memory cell capacitor according to the stored data of the dummy memory cell. It was done.

According to the twentieth to twenty-third aspects of the present invention, in the 2T2C type ferroelectric memory device, each complementary memory cell capacitor is provided with an individual cell plate electrode or a complementary memory cell so as to increase the rewriting charge amount. The gate electrodes of the transistors are connected to individual word lines.

[0016]

According to the present invention, in the 1T1C type ferroelectric memory device, the dummy memory according to the capacitance characteristic when the main body memory cell capacitor is repeatedly operated until the capacitance characteristic does not change. Since the capacitance value of the cell capacitor is decided, the influence of the imprint effect is mitigated and a large operation margin is secured. In particular, according to the third aspect of the invention, not only the main body memory cell capacitor but also the dummy memory cell capacitor are operated in both polarities, so that the imprint effect is prevented from occurring.

According to the present invention, the applied voltage of the main body memory cell capacitor and the applied voltage of the dummy memory cell capacitor are made different in the 1T1C type ferroelectric memory device. A dummy memory cell capacitor having an area equivalent to that of the capacitor can be adopted, variation in capacitance value of the dummy memory cell capacitor is reduced, and a large operation margin is secured.

According to the invention of claims 8 to 13, 1T1C
Type or 2T2C type ferroelectric memory device, in which at least one of the voltage applied to the cell plate electrode at the time of reading data and the voltage applied to the cell plate electrode at the time of rewriting data is set higher than the power supply voltage. Therefore, sufficient remanent polarization can be obtained even when the power supply voltage drops, and a large operation margin can be secured.

According to the inventions of claims 14 and 15, 1T
In the ferroelectric memory device of 1C type or 2T2C type, the self-booting of the rewriting voltage is realized by setting the word line connected to the gate electrode of the memory cell transistor to a floating state after the word line is selected. When the logic voltage "H" is rewritten in the capacitor, Vt drop of the memory cell transistor is prevented, sufficient remanent polarization is obtained, and a large operation margin is secured.

According to the invention of claims 16 and 17, 1T
In the 1C type ferroelectric memory device, when the data of the main body memory cell is rewritten, the voltage of the word line connected to the gate electrode of the main body memory cell transistor and the voltage of the cell plate electrode of the main body memory cell capacitor are lowered. Since the order of is changed according to the data stored in the main body memory cell, the amount of rewrite charges of the main body memory cell capacitor is increased and a large operation margin is secured.

According to the invention of claims 18 and 19, 1T
In the 1C type ferroelectric memory device, at the time of rewriting the data of the dummy memory cell, the order of the voltage fall of the dummy word line and the voltage fall of the dummy cell plate electrode is changed according to the stored data of the dummy memory cell. Therefore, the state of the dummy memory cell capacitor can be easily initialized.

According to the invention of claims 20 to 23, 2T2
In the C-type ferroelectric memory device, the complementary memory cell capacitor is provided with an individual cell plate electrode, or the gate electrode of the complementary memory cell transistor is connected to an individual word line, so that the rewrite charge amount is increased. It is possible to secure a large operation margin.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A ferroelectric memory device according to an embodiment of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a circuit configuration of a ferroelectric memory device according to the first embodiment, and FIG. 2 is a diagram showing operation timing of the ferroelectric memory device of FIG. Curve 4 in FIG. 3 is the hysteresis characteristic of the ferroelectric capacitor forming the main body memory cell, and curve 3 is the hysteresis characteristic of the ferroelectric capacitor forming the dummy memory cell. FIG. 4 shows a method of determining the curve 4 in FIG.

In FIG. 1, WL0 to WL255 are word lines, DWL0 and DWL1 are dummy word lines, and BL, /
BL is a bit line, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DCRST is a dummy memory cell data initialization control signal, SAE is a sense amplifier control signal, and VSS is a ground voltage. SA is a sense amplifier, C0 to C255 are main body memory cell capacitors, DC0 and DC1 are dummy memory cell capacitors, Qn0 to Qn255, QnD0 and QnD.
1, QnR0, QnR1 and QnBP0, QnBP
1 is an N-channel MOS transistor,
0-Qn255 is the main memory cell transistor, QnD
0 and QnD1 are called dummy memory cell transistors. In FIG. 3, QL is a main memory cell “L” data read charge amount, QH is a main memory cell “H” data read charge amount, and QD is a dummy memory cell data read charge amount.

First, the circuit configuration diagram of FIG. 1 will be described. Bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA is a sense amplifier control signal S
It is controlled by AE. Dummy memory cell capacitor DC0
The first electrode of the gate electrode is the dummy word line DWL0.
Is connected to the bit line / BL via the dummy memory cell transistor QnD0 connected to, and the second electrode is connected to the dummy cell plate electrode DCP. The first electrode of the dummy memory cell capacitor DC1 is connected to the bit line BL through the dummy memory cell transistor QnD1 whose gate electrode is connected to the dummy word line DWL1, and the second electrode is connected to the dummy cell plate electrode DCP. ing. Also, both dummy memory cell capacitors DC
The first electrodes of 0 and DC1 are N to which the dummy memory cell data initialization control signal DCRST is applied to the gate electrodes.
It is connected to the ground voltage VSS, which is a dummy memory cell data initializing voltage, via the channel type MOS transistors QnR0 and QnR1. On the other hand, the gate electrode of the first electrode of the main body memory cell capacitor C0 is the word line WL.
It is connected to the bit line BL via the body memory cell transistor Qn0 connected to 0, and the second electrode is connected to the cell plate electrode CP. The first electrode of the main body memory cell capacitor C1 is connected to the bit line / BL via the main body memory cell transistor Qn1 whose gate electrode is connected to the word line WL1, and the second electrode is connected to the cell plate electrode CP. ing.

The horizontal axis of FIG. 3 represents the electric field applied to the memory cell capacitor, and the vertical axis represents the accumulated charge of the memory cell capacitor. Point A4 to Point B4, Point D4 and Point E4
A curve 4 forming a loop passing through to the point A4 is a hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and remnant polarization remains at points B4 and E4 even when the electric field is zero. In this way, the non-volatile memory device is realized by utilizing the residual polarization remaining in the ferroelectric capacitor even after the power is turned off as non-volatile data. The main body memory cell capacitor is in the state of point B4 in FIG. 3 when the data of the memory cell is “H”, and in the state of point E4 in FIG. 3 when the data of the memory cell is “L”. . Also, from point A3 through point B3, point D3, and point E3, point A
The curve 3 forming the loop returning to 3 is the hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell, which is the point B4.
The curve 4 is enlarged in the vertical axis direction by a predetermined magnification so as to pass through the origin O between the point E4 and the point E4, thereby forming the curve 3.
The slopes of the curves 3 and 4 in FIG. 3 indicate the capacitance of the capacitor.

FIG. 2 shows the operation timing for reading the data held in the main body memory cell capacitor C0. First, as an initial state, the bit line precharge control signal B
By setting P to the logical voltage "H", the bit line B
L and / BL are set to the logical voltage "L". Also, the word line W
L0 to WL255, dummy word lines DWL0 and DWL
1, cell plate electrode CP, dummy cell plate electrode D
CP is set to a logic voltage "L". Further, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "H", and both dummy memory cell capacitors DC0 and DC1 are initialized to the state of the point E3 of the curve 3 in FIG. Next, the bit line precharge control signal BP is set to the logic voltage "L" to bring the bit lines BL and / BL into a floating state, and the dummy memory cell data initialization control signal D is set.
By setting CRST to the logic voltage "L", the first electrodes of both dummy memory cell capacitors DC0 and DC1 are brought into a floating state. Next, the word line WL0, the dummy word line DWL0, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the logical voltage “H”, so that the data of the main body memory cell capacitor C0 is set to the bit line BL and the dummy memory cell capacitor DC0 is set. Data is read to the bit line / BL. Here, the state of the main body memory cell capacitor C0 transits from the point B4 in FIG. 3 to the point D4 when the data is “H”, and the charge QH, and when the data is “L”, the point in FIG. The electric charge QL is read out to the bit line BL by transiting from E4 to the point D4. The state of the dummy memory cell capacitor DC0 transits from the point E3 in FIG. 3 to the point D3 to read the charge QD to the bit line / BL. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. As a result, the state of the main body memory cell capacitor C0 transits from the point D4 of FIG. 3 to the point E4 when the data is “H”, and changes to the state of the point D4 of FIG. 3 when the data is “L”. keeping. As for the state of the dummy memory cell capacitor DC0, when the data is “H”, the state of the point D3 of FIG. 3 is held,
When the data is "L", the transition is made from point D3 to point E3 in FIG. Next, the cell plate electrode CP is set to the logic voltage "L".
By doing so, the data of the main body memory cell capacitor C0 is rewritten. As a result, the state of the main body memory cell capacitor C0 is as shown in FIG. 3 when the data is “H”.
Point E4 to point A4, and when the data is "L", point D4 to point E4 in FIG. Next, the word line WL0 and the dummy word line DWL0 are set to the logic voltage "L", so that the main body memory cell capacitor C0 and the dummy memory cell capacitor DC0 are connected to the bit lines BL, / B.
Separate from L. As a result, no voltage is applied to the main body memory cell capacitor C0 and the dummy memory cell capacitor DC0. As a result, the state of the main body memory cell capacitor C0 transits from the point A4 of FIG. 3 to the point B4 when the data is “H”, and changes to the state of the point E4 of FIG. 3 when the data is “L”. Hold. Next, by setting the dummy cell plate electrode DCP to the logical voltage "L", the dummy memory cell capacitor DC0 is set to the state of point E3 in FIG. 3, and the sense amplifier control signal SAE is set to the logical voltage "L". The operation of the sense amplifier SA is stopped. Next, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL, / BL
Is the ground voltage VSS. Moreover, the voltage applied to the dummy memory cell capacitor DC0 is set to zero by setting the dummy memory cell data initialization control signal DCRST to the logical voltage “H”, and as a result, the state of the dummy memory cell capacitor DC0 is changed to point E3 in FIG. Make sure to return to the state of. In this way, reading and rewriting of data is completed.

The characteristic of the ferroelectric memory device of this embodiment is the setting of the capacitance value of the dummy memory cell capacitor. First, in FIG. 4, a curve 1 is the hysteresis characteristic of the ferroelectric capacitor of the conventional main body memory cell. This curve 1 is obtained by measuring positive and negative voltages between both electrodes of the main body memory cell capacitor several times. However, when the number of times the positive and negative voltages are applied between both electrodes is increased, the hysteresis characteristic is shifted by the imprint effect in the direction in which the electric charge increases as shown by the curve 4 in FIG.
It becomes saturated soon. Since the dummy memory cell capacitor is repeatedly used for the same operation many times, unless the capacitance value is set by the data in the state where the hysteresis characteristic is saturated as shown by the curve 4 in FIG. Therefore, in the ferroelectric memory device of the present embodiment, the ferroelectric capacitor of the main body memory cell having the characteristics obtained in the state where the number of times the voltage is applied between both electrodes of the capacitor is increased is adopted. The hysteresis characteristic is shown by the curve 4 in FIG. Here, the read charge amount when the data of the memory cell is "H" is QH, and the read charge amount when the data of the memory cell is "L" is QL. Next, a point B4 in which the data of the memory cell is in the "H" state and a point E in which it is in the "L" state
A curve 3 obtained by vertically enlarging the curve 4 at a predetermined magnification so as to pass through the center point of 4 is set as the hysteresis characteristic of the dummy memory cell capacitor. The curves 4 and 3 in FIG. 3 indicate the capacitance of the capacitor. Therefore, here, the ideal setting is that the capacitance value of the dummy memory cell capacitor is 3.5 times the capacitance value of the main body memory cell capacitor. The operation of the dummy memory cell capacitor is an operation in which a positive or negative voltage is applied between both electrodes. If the capacitance value of the dummy memory cell capacitor is set to twice the capacitance value of the main body memory cell capacitor as in the prior art, the difference in charge amount for reading the data “L” of the memory cell is 40% of that in the present embodiment. You can see that it was only possible.

By designing to maximize the difference in the amount of read charges as in the first embodiment, no malfunction occurs even when the sense sensitivity of the sense amplifier varies and the power supply voltage is low. Thus, the ferroelectric memory device operates even when the difference in the amount of read charges becomes small, and operates at a lower voltage.

(Embodiment 2) In the second embodiment, data of hysteresis characteristics when the voltage applied between both electrodes of the dummy memory cell capacitor is repeatedly operated either positively or negatively many times. To set the capacitance value of the dummy memory cell capacitor. The circuit configuration diagram and the operation timing diagram are the same as those in the first embodiment.
FIG. 2 is an operation timing chart of FIG. Curve 4 in FIG. 6 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and curve 6 is the hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell. FIG. 7 shows a method of determining the curve 6 in FIG.

Here, the ferroelectric memory device of the present embodiment is characterized in that when the voltage applied to the dummy memory cell capacitor is repeatedly operated either positively or negatively many times, the optimum capacitance is obtained by the data. By setting the value,
That is, it is possible to set the capacitance value in a state closer to the ideal state than in the above embodiment. Compared to the first embodiment, the hysteresis characteristic of the dummy memory cell capacitor has a hysteresis characteristic curve 4 of FIG. 7 which is obtained by repeatedly operating the voltage both positively and negatively by the imprint effect. The slope becomes smaller as shown by the curve 7. The optimum capacitance value of the dummy memory cell capacitor is determined using the data of this curve 7. The determination method is such that the curve 7 in FIG. 7 is predetermined in the vertical direction so as to pass through the center point between the point B4 in the "H" state of the data in the memory cell and the point E4 in the "L" state. The curve 6 in FIG. 6 enlarged by the magnification is set as the hysteresis characteristic of the dummy memory cell capacitor. The slopes of the curve 7 in FIG. 7 and the curve 6 in FIG. 6 indicate the capacitance of the capacitor. Therefore, here, the capacitance value of the dummy memory cell capacitor is ideally set to 7 times the capacitance value of the main body memory cell capacitor. If the capacitance value of the dummy memory cell capacitor is set to be twice the capacitance value of the main body memory cell capacitor as in the conventional case, the difference in charge amount for reading the data “L” of the memory cell becomes zero and the memory cell does not operate normally. .

As in the second embodiment, it is designed to maximize the read charge amount difference by the hysteresis characteristic corresponding to the operating state of the dummy memory cell capacitor.
This is important for the ferroelectric memory device to operate normally.

(Third Embodiment) In the third embodiment, as in the first embodiment, the voltage applied between both electrodes of the body memory cell capacitor is operated both positively and negatively and applied to the body memory cell capacitor. The voltage value applied between both electrodes sets the capacitance value of the dummy memory cell capacitor with the hysteresis characteristic data when the voltage is repeatedly operated both positive and negative. Is operated in both positive and negative. FIG. 8 is a circuit configuration diagram, and FIG. 9 is an operation timing diagram of FIG. FIG.
Curve 4 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and curve 3 is the hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell.

WL0 to WL255 are word lines, DWL
0 and DWL1 are dummy word lines, BL and / BL are bit lines, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DC
RST is a dummy memory cell data initialization control signal, S
AE is a sense amplifier control signal, VSS is a ground voltage, SA
Is a sense amplifier, C0 to C255 are main body memory cell capacitors, DC0 and DC1 are dummy memory cell capacitors, Qn0 to Qn255, QnD0, QnD1 and QnR.
0, QnR1, QnBP0, QnBP1 are N-channel MOS transistors, QpR0 to QpR1 are P-channel MOS transistors, QL is a main memory cell “L” data read charge amount, QH is a main memory cell “H” data read charge amount, QD is the dummy memory cell data read charge amount, and RSTDT is the dummy memory cell capacitor reset voltage.

First, the circuit configuration diagram of FIG. 8 will be described. This circuit configuration is almost the same as that of FIG. 1 of the first embodiment, and the bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA is controlled by the sense amplifier control signal SAE. The first electrode of the dummy memory cell capacitor is connected to the bit line through the dummy memory cell transistor whose gate electrode is connected to the dummy word line, and the second electrode is connected to the dummy cell plate electrode DCP. The first electrode of the main body memory cell capacitor is connected to the bit line via the main body memory cell transistor whose gate electrode is connected to the word line, and the second electrode is connected to the cell plate electrode CP. Further, the first electrode of the dummy memory cell capacitor is an N-channel type MOS transistor QnR0, QnR1 having a gate electrode of the dummy memory cell data initialization control signal DCRST and a P-channel type having an inverted signal of the signal DCRST as a gate electrode. It is connected to a dummy memory cell capacitor reset voltage RSTDT which is a dummy memory cell data initializing voltage via the MOS transistors QpR0 and QpR1.

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing diagram of FIG. 9 and the hysteresis characteristic diagram of the main body memory cell capacitor and the dummy memory cell ferroelectric capacitor of FIG. First, in order to read the data of the memory cell, as an initial state,
By setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L". Also, word lines WL0 to WL255, dummy word lines DWL0 and DWL1, cell plate electrode C
P and the dummy cell plate electrode DCP are set to the logic voltage "L". Further, the dummy memory cell data initialization control signal DCRST is set to the logical voltage "H", the dummy memory cell capacitor reset voltage RSTDT is set to the logical voltage "L", and the dummy memory cell is initialized to the state of the point E3 of the curve 3 in FIG. Turn into. Next, by setting the bit line precharge control signal BP to the logical voltage "L", the bit lines BL, / BL
Is set to a floating state, and the dummy memory cell data initialization control signal DCRST is set to the logic voltage "L", whereby the first electrode of the dummy memory cell capacitor is set to a floating state. Next, the word line WL0, the dummy word line DWL0, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the logical voltage "H", the data of the main body memory cell is set to the bit line BL, and the data of the dummy memory cell is set to the bit line / BL. Read to. Here, when the data is "H", the state of the main body memory cell transits from the point B4 to the point D4 in FIG. 3 to change the charge QH and the data to "L".
In the case of, the transition from point E4 to point D4 in FIG.
Is read to the bit line BL, the state of the dummy memory cell transits from point E3 to point D3 (D4) in FIG.
Read D to bit line / BL. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. As a result, when the data is "H",
The state of the main body memory cell transits from point D4 of FIG. 3 to point E4, and the dummy memory cell holds the state of point D3 of FIG.
When the data is "L", the main body memory cell holds the state of point D4 in FIG. 3, and the state of the dummy memory cell transits from point D3 to point E3 in FIG. Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. As a result, when the data is "H", the state of the main body memory cell changes from point E4 to point A4 in FIG.
When the data is "L", the transition is made from point D4 to point E4 in FIG. In addition, the dummy cell plate electrode DC
P is also a logical voltage "L". Next, the word line WL0 and the dummy word line DWL0 are set to the logical voltage "L" so that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the sense amplifier control signal SAE is set to the logic voltage "L" to stop the operation of the sense amplifier SA. Further, the dummy memory cell data initialization control signal DCRST is set to the logical voltage “H”, the dummy memory cell capacitor reset voltage RSTDT is set to the logical voltage “H”, and the state of the dummy memory cell is changed from point E3 to point A3 in FIG. Let Thereafter, the dummy cell plate electrode DCP is set to the logic voltage "H", the dummy memory cell capacitor reset voltage RSTDT is set to the logic voltage "L",
The state of the dummy memory cell is changed from the point A3 in FIG. 3 to the point D3, the dummy cell plate electrode DCP is set to the logic voltage “L”, and the state of the dummy memory cell is changed to the point D3 in FIG.
The state of the dummy memory cell is set to the initial state by transiting from the point E3 to the point E3. Further, by setting the bit line precharge control signal BP to the logical voltage “H”,
The bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the third embodiment, in the operation of the dummy memory cell capacitor, the voltage applied between the two electrodes is always operated with both positive and negative, so that the dummy memory cell capacitor is operated with less influence of the imprint effect. It is possible to obtain a ferroelectric memory device that does not malfunction due to the reduction of the operating margin.

(Embodiment 4) In the fourth embodiment, a dummy value is set by setting the voltage value applied between both electrodes of the dummy memory cell capacitor to a value different from the voltage value applied between both electrodes of the main body memory cell capacitor. The amount of charges read from the memory cell capacitor is set. First, in the fourth embodiment, at the time of rewriting charges, the voltage value applied between both electrodes of the dummy memory cell capacitor and the voltage value applied between both electrodes of the main body memory cell capacitor are set to be the same, and the charge is read out. The reference charge amount from the dummy memory cell capacitor is set by making the voltage value applied between both electrodes of the dummy memory cell capacitor smaller than the voltage value sometimes applied between both electrodes of the main body memory cell capacitor. 10 is an overall circuit configuration diagram, and FIG. 11 is an operation timing diagram of FIG. 12 is a hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, a curve 12 is a hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell, and FIG. 13 (a) and FIG.
(B) is a signal generation circuit configuration diagram of the cell plate electrode CP and the dummy cell plate electrode DCP.

WL0 to WL255 are word lines, DWL
0 and DWL1 are dummy word lines, BL and / BL are bit lines, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DC
RST and DCRST2 are dummy memory cell data initialization control signals, SAE is a sense amplifier control signal, VSS is a ground voltage, VDD is a power supply voltage, SA is a sense amplifier, C
0 to C255 are main body memory cell capacitors, DC0, D
C1 is a dummy memory cell capacitor, Qn0 to Qn25
5, QnD0, QnD1, QnBP0, QnBP1, Q
nC131 to QnC135 and QnR0 to QnR3
Is an N-channel MOS transistor, QpC131-Q
pC134 is a P-channel MOS transistor, QL is a main memory cell “L” data read charge amount, QH is a main memory cell “H” data read charge amount, QD is a dummy memory cell data read charge amount, and CPC is a cell plate electrode control. The signal, DCPC, is a dummy cell plate electrode control signal.

First, the circuit configuration diagram of FIG. 10 will be described. Bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA is a sense amplifier control signal S
It is controlled by AE. First dummy memory cell capacitor
The gate electrode is connected to the bit line through the dummy memory cell transistor whose gate electrode is connected to the dummy word line, and the second electrode is connected to the dummy cell plate electrode DCP. The third electrode of the body memory cell capacitor is connected to the bit line through the body memory cell transistor whose gate electrode is connected to the word line, and the fourth electrode is connected to the cell plate electrode CP. The first electrode of the dummy memory cell capacitor is a power supply which is a dummy memory cell data initialization voltage via a P-channel type MOS transistor QpR1 whose gate electrode is an inverted signal of the dummy memory cell data initialization control signal DCRST. It is connected to the voltage VDD. Further, the circuit configuration of FIG. 13A is a circuit in which the cell plate electrode control signal CPC is used as an input signal and the cell plate electrode signal CP having the same phase as the ground voltage VSS and the power supply voltage VDD is used as an output signal. is there. In the circuit configuration of FIG. 13B, the dummy cell plate electrode control signal DCPC is used as an input signal, and in phase with this, the amplitude is VSS and “VDD−Vtn”.
(Vtn is the threshold voltage of the N-channel type MOS transistor) ", which is a circuit that outputs the dummy cell plate electrode signal DCP as an output signal. Here, the logic voltage" H "of the dummy cell plate electrode signal DCP is" VDD ". −
Although Vtn ”is set, a predetermined voltage value is set according to the hysteresis characteristic of the ferroelectric capacitor used. For example, a voltage of“ VDD-2Vtn ”or“ VDD-3Vtn ”can be easily created. (QH + Q
The voltage of the dummy cell plate electrode signal DCP that can realize the relationship of L) / 2 is ideal.

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing chart of FIG. 11 and the hysteresis characteristic diagram of the ferroelectric capacitors of the main body memory cell and the dummy memory cell of FIG. In the hysteresis characteristic diagram of the ferroelectric capacitor of FIG. 12, the horizontal axis represents the electric field applied to the memory cell capacitor, and the vertical axis represents the electric charge at that time. Curve 4 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell. In the ferroelectric capacitor, remanent polarization remains at points B4 and E4 even when the electric field is zero. A curve 12 is the hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell, and is set so that the electric field is not applied to the ferroelectric in the initial state, and the point B12 is set when the electric field is zero. First, in order to read the data of the memory cell, the dummy memory cell data initialization control signals DCRST, DC
Both RST2 are set to the logic voltage "H", and the dummy memory cell is brought to the state of the point A12 on the curve 12 in FIG. Also,
By setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L". Also, word lines WL0 to WL255, dummy word lines DWL0 and DWL1, cell plate electrode C
P and the dummy cell plate electrode DCP are set to the logic voltage "L". Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "L" to initialize the dummy memory cell to the state of the point B12 on the curve 12 in FIG. Next, the bit line precharge control signal BP is set to the logic voltage "L" to bring the bit lines BL and / BL into the floating state, and the dummy memory cell data initialization control signal DCRST2 is set to the logic voltage "L". As a result, the first electrode of the dummy memory cell capacitor is brought into a floating state. Next, the word line WL0, the dummy word line DWL0, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the logical voltage "H", the data of the main body memory cell is set to the bit line BL, and the data of the dummy memory cell is set to the bit line / BL. Read to. Here, when the data is "H", the state of the main body memory cell transits from the point B4 to the point D4 in FIG.
In the case of, the transition from point E4 to point D4 in FIG.
When L is read to the bit line BL, the state of the dummy memory cell transits from point B12 to point D12 in FIG.
Is read to the bit line / BL. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. As a result, when the data is "H", the state of the main body memory cell transits from the point D4 of FIG. 12 to the point E4, the state of the dummy memory cell holds the state of the point D12 of FIG. In the case of L ″, the state of the main body memory cell retains the state of point D4 of FIG. 12, and the state of the dummy memory cell transits from point D12 of FIG. 12 to point E12.
Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. This allows
The state of the main body memory cell transits from point E4 in FIG. 12 to point A4 when the data is “H”, and transits from point D4 to point E4 in FIG. 12 when the data is “L”. Next, the word line WL0 and the dummy word line DWL0 are set to the logical voltage "L" so that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the dummy cell plate electrode DCP is also set to the logical voltage "L" and the sense amplifier control signal SAE is set to the logical voltage "L" to stop the operation of the sense amplifier SA. Next, the dummy memory cell data initialization control signal DCRS
T and DCRST2 are set to the logic voltage "H", and the state of the dummy memory cell is transited from point E12 to point A12 in FIG. Further, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the fourth embodiment, when the dummy memory cell capacitor is operated, the voltage applied between the two electrodes is always positive and negative, so that the dummy memory cell capacitor is operated with less influence of the imprint effect. It is possible to obtain a ferroelectric memory device that does not malfunction due to the reduction of the operating margin. In addition, the size of the main body memory cell capacitor and the dummy memory cell capacitor are set to be approximately the same, and the reference voltage is created by appropriately setting the voltage applied between both electrodes of the dummy memory cell capacitor for reading data. There is almost no deviation of the reference voltage due to manufacturing variations of the memory cell capacitor. Further, since the voltage applied between both electrodes of the dummy memory cell capacitor is smaller than the power supply voltage VDD, the power consumption is reduced accordingly.

(Embodiment 5) In the fifth embodiment, as in the fourth embodiment, the voltage value applied between both electrodes of the dummy memory cell capacitor is the same as the voltage value applied between both electrodes of the main memory cell capacitor. By setting different values, the amount of charge read from the dummy memory cell capacitor is set. In the fifth embodiment, the voltage value applied between both electrodes of the dummy memory cell capacitor at the time of reading charges is the same as the voltage value applied between both electrodes of the main body memory cell capacitor, and dummy voltage is applied at the time of rewriting charges. The reference charge amount from the dummy memory cell capacitor is set by making the voltage value applied between both electrodes of the memory cell capacitor smaller than the voltage value applied between both electrodes of the main body memory cell capacitor. 14 is an overall circuit configuration diagram, and FIG. 15 is an operation timing diagram of FIG. Curve 4 in FIG. 16 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and curve 16 is the hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell.

WL0 to WL255 are word lines, DWL
0 and DWL1 are dummy word lines, BL and / BL are bit lines, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DC
RST and DCRST2 are dummy memory cell data initialization control signals, SAE is a sense amplifier control signal, VSS is a ground voltage, VDD is a power supply voltage, SA is a sense amplifier, C
0 to C255 are main body memory cell capacitors, DC0, D
C1 is a dummy memory cell capacitor, Qn0 to Qn25
5, QnD0, QnD1, QnBP0, QnBP1, Q
nR0 to QnR3 are N-channel MOS transistors,
QL is the amount of charge for reading data from the main body memory cell “L”, Q
H is the main memory cell “H” data read charge amount, QD
Is the amount of charges read from the dummy memory cell data.

First, the circuit configuration diagram of FIG. 14 will be described. Bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA is a sense amplifier control signal S
It is controlled by AE. First dummy memory cell capacitor
The gate electrode is connected to the bit line through the dummy memory cell transistor whose gate electrode is connected to the dummy word line, and the second electrode is connected to the dummy cell plate electrode DCP. The third electrode of the body memory cell capacitor is connected to the bit line through the body memory cell transistor whose gate electrode is connected to the word line, and the fourth electrode is connected to the cell plate electrode CP. The first electrode of the dummy memory cell capacitor is supplied with the power supply voltage VDD which is the dummy memory cell data initializing voltage through the N-channel type MOS transistor QnR1 having the dummy memory cell data initializing control signal DCRST as a gate electrode. N connected and having the control signal DCRST2 as a gate electrode
It is connected to the ground voltage VSS which is the dummy memory cell data initializing voltage via the channel type MOS transistor QnR3. In this circuit, the first electrode of the dummy memory cell capacitor can be set to "VDD-Vtn (Vtn is the threshold voltage of the N-channel MOS transistor)".

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing diagram of FIG. 15 and the hysteresis characteristic diagram of the main body memory cell capacitor and the dummy memory cell ferroelectric capacitor of FIG. FIG.
In the hysteresis characteristic diagram of the ferroelectric capacitor of No. 6, the horizontal axis shows the electric field applied to the memory cell capacitor, and the vertical axis shows the electric charge at that time. Curve 4 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell. In the ferroelectric capacitor, remanent polarization remains at points B4 and E4 even when the electric field is zero. A curve 16 is a hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell so that no electric field is applied to the ferroelectric in the initial state, and the point B1 is set when the electric field is zero.
6 First, in order to read data in a memory cell, a dummy memory cell data initialization control signal DCRS
T is a logic voltage "H" and DCRST2 is a logic voltage "L", and a dummy memory cell is provided in the state of the point A16 of the curve 16 in FIG. In addition, the bit line precharge control signal BP
To the logic voltage "H", the bit lines BL,
/ BL is a logical voltage "L". Also, word line WL0
˜WL255, dummy word lines DWL0 and DWL1, cell plate electrode CP, and dummy cell plate electrode DCP are set to logic voltage “L”. Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "L", the control signal DCRST2 is set to the logic voltage "H", and the curve 1 in FIG.
The dummy memory cell is initialized to the state of point B16 of 6.
Next, the bit line precharge control signal BP is set to the logic voltage "L" to bring the bit lines BL and / BL into the floating state, and the dummy memory cell data initialization control signal DCRST2 is set to the logic voltage "L". As a result, the first electrode of the dummy memory cell capacitor is brought into a floating state. Next, the word line WL0, the dummy word line DWL0, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the logical voltage "H", the data of the main body memory cell is set to the bit line BL, and the data of the dummy memory cell is set to the bit line / BL. Read to. Here, when the data is "H", the state of the main body memory cell transits from the point B4 to the point D4 in FIG. 16 to change the charge QH and the data "L".
In the case of, the transition from point E4 to point D4 in FIG.
When L is read to the bit line BL, the state of the dummy memory cell transits from point B16 to point D16 in FIG.
Is read to the bit line / BL. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. As a result, when the data is "H", the state of the main body memory cell transits from the point D4 in FIG. 16 to the point E4, the state of the dummy memory cell retains the state of the point D16 in FIG. 16, and the data is " In the case of L ″, the state of the main body memory cell holds the state of point D4 in FIG. 16, and the state of the dummy memory cell transits from point D16 in FIG. 16 to point E16.
Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. This allows
The state of the body memory cell transits from point E4 in FIG. 16 to point A4 when the data is “H”, and transits from point D4 to point E4 in FIG. 16 when the data is “L”. Next, the word line WL0 and the dummy word line DWL0 are set to the logical voltage "L" so that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the dummy cell plate electrode DCP is also set to the logical voltage "L" and the sense amplifier control signal SAE is set to the logical voltage "L" to stop the operation of the sense amplifier SA. Next, the dummy memory cell data initialization control signal DCRS
T and DCRST2 are set to the logic voltage "H", and the state of the dummy memory cell is transited from the point E16 in FIG. 16 to the point A16. Further, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the fifth embodiment, when the dummy memory cell capacitor is operated, the voltage applied between both electrodes is always positive and negative, so that the dummy memory cell capacitor is operated with less influence of the imprint effect. It is possible to obtain a ferroelectric memory device that does not malfunction due to the reduction of the operating margin. In addition, the size of the main body memory cell capacitor and the dummy memory cell capacitor are set to be approximately the same, and the reference voltage is created by appropriately setting the voltage applied between both electrodes of the dummy memory cell capacitor for reading data. There is almost no deviation of the reference voltage due to manufacturing variations of the memory cell capacitor. Further, the voltage applied between both electrodes of the dummy memory cell capacitor is the power supply voltage VDD as in the fourth embodiment.
Since it is smaller, it consumes less power.

(Embodiment 6) In the sixth embodiment, as in the fourth embodiment, the voltage value applied between both electrodes of the dummy memory cell capacitor is the same as the voltage value applied between both electrodes of the main memory cell capacitor. By setting different values, the amount of charge read from the dummy memory cell capacitor is set. In the sixth embodiment, the voltage value applied between both electrodes of the dummy memory cell capacitor at the time of reading charges is made larger than the voltage value applied between both electrodes of the main body memory cell capacitor, so that the dummy memory cell capacitor The reference charge amount of is set. In addition, the charge is not rewritten in the dummy memory cell capacitor, and only one remanent polarization state is used. The overall circuit configuration diagram is similar to that of FIG. 1 of the first embodiment, FIG. 17 is a dummy cell plate signal generation circuit, and FIG. 18 is FIG.
3 is an operation timing chart of FIG. A curve 4 in FIG. 19 shows the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and a curve 19 shows the hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell.

WL0 to WL255 are word lines, DWL
0 and DWL1 are dummy word lines, BL and / BL are bit lines, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DC
RST is a dummy memory cell data initialization control signal, S
AE is a sense amplifier control signal, S1 is a control signal, N17
01 to N1703 are node names, VDD is power supply voltage, VS
S is a ground voltage, SA is a sense amplifier, C0 to C255 are main body memory cell capacitors, DC0 and DC1 are dummy memory cell capacitors, C1701 is a capacitor, Qn0.
~ Qn255, QnD0, QnD1, QnBP0, Qn
BP1, QnR0 and QnR1 are N-channel type MOS transistors, QL is a main memory cell "L" data read charge amount, QH is a main memory cell "H" data read charge amount, and QD is a dummy memory cell data read charge amount.

The overall circuit configuration diagram is similar to that of FIG. 1 of the first embodiment. First, the dummy cell plate signal generating circuit of FIG. 17 for supplying the signal of the dummy cell plate DCP of FIG. 1 will be briefly described. Dummy cell plate electrode DC
The signal of P has the same phase as the control signal S1 and the amplitude is the ground voltage VSS.
And a voltage higher than the power supply voltage VDD. Here, "2 x
VDD "is generated. When the control signal S1 is the logic voltage" L ", the node N1701 is VDD and the transistor Qn1 is generated.
702 is on, the transistor Qp1701 is off, and the signal of the electrode DCP is VSS. Also, the transistor Qp
1702 is on and node N1703 is at VDD. Next, when the control signal S1 becomes the logic voltage "H", the node N1701 becomes VSS and the transistor Qn1702.
Is off, the transistor Qp1703 is on and the node N1
The voltage of 703 is transmitted to the signal DCP. At this time, the voltage of the node N1703 is initially VDD, but is boosted by the capacitor C1701 and ideally “2 × VDD”.
Becomes

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing chart of FIG. 18 and the hysteresis characteristic diagram of the main body memory cell capacitor and the dummy memory cell ferroelectric capacitor of FIG. FIG.
In the hysteresis characteristic diagram of the ferroelectric capacitor of No. 9, the horizontal axis represents the electric field applied to the memory cell capacitor, and the vertical axis represents the electric charge at that time. Curve 4 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell. In the ferroelectric capacitor, remanent polarization remains at points B4 and E4 even when the electric field is zero. A curve 19 is a hysteresis characteristic of the ferroelectric capacitor of the dummy memory cell so that no electric field is applied to the ferroelectric in the initial state, and the point B1 is set when the electric field is zero.
Set to 9. First, in order to read data in a memory cell, a dummy memory cell data initialization control signal DCRS
T is a logical voltage "H", and a point B19 of the curve 19 in FIG.
The dummy memory cell is set in the state of. Further, the bit line precharge control signal BP is set to the logical voltage "H", so that the bit lines BL and / BL are set to the logical voltage "L".
In addition, the word lines WL0 to WL255 and the dummy word line D
The WL0, DWL1, the cell plate electrode CP, and the dummy cell plate electrode DCP are connected to the ground voltage V which is the logical voltage "L".
It is SS. By setting the dummy memory cell data initialization control signal DCRST to the logical voltage "L", setting the first electrode of the dummy memory cell to the floating state, and setting the bit line precharge control signal BP to the logical voltage "L". , The bit lines BL and / BL are brought into a floating state. Next, the word line WL0 and the dummy word line DWL
0, cell plate electrode CP, and dummy cell plate electrode D
CP is set to the logic voltage "H", and the data of the main body memory cell is read to the bit line BL and the data of the dummy memory cell is read to the bit line / BL. Here, the dummy cell plate electrode D
The logical voltage “H” of CP is a voltage (2 × VDD) boosted from the power supply voltage VDD. The state of the main body memory cell is
When the data is “H”, the charge changes from the point B4 to the point D4 in FIG. 19 and the charge QH, and when the data is “L”, the charge is QH.
From the point E4 to the point D4 and the charge QL is transferred to the bit line BL.
The state of the dummy memory cell is read at point B in FIG.
19 to the point D19 to transfer the charge QD to the bit line / BL
Read to. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. As a result, when the data is "H", the state of the main body memory cell transits from the point D4 in FIG. 19 to the point E4, the state of the dummy memory cell retains the state of the point D19 in FIG. 19, and the data is " In the case of L ″, the state of the main body memory cell is point D in FIG.
4, the state of the dummy memory cell transits from point D19 in FIG. 19 to point B19. Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. As a result, the state of the main body memory cell transits from point E4 in FIG. 19 to point A4 when the data is “H” and point D in FIG. 19 when the data is “L”.
The transition from point 4 to point E4. Next, the word line WL0 and the dummy word line DWL0 are set to the logical voltage "L" so that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the dummy cell plate electrode DCP is also set to the logical voltage "L", and the sense amplifier control signal SAE is set to the logical voltage "L" to set the sense amplifier SA.
Stop the operation of. Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "H", and the state of the dummy memory cell is set to the state of point B19 in FIG.
Further, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the sixth embodiment, in the operation of the dummy memory cell capacitor, the sizes of the main body memory cell capacitor and the dummy memory cell capacitor are set to be substantially the same, and the dummy memory cell capacitor for reading data is provided between both electrodes of the dummy memory cell capacitor. Since the reference voltage is created by making the applied voltage larger than the voltage applied between both electrodes of the main body memory cell capacitor, there is an effect that there is almost no deviation of the reference voltage due to manufacturing variations of the memory cell capacitor.

(Embodiment 7) In a seventh embodiment, a large amount of read charge is read out when reading data from the main body memory cell. In this embodiment, the voltage of the cell plate electrode CP is read out when reading data. Power supply voltage VDD
By making it higher, the voltage value applied between both electrodes of the main body memory cell capacitor is increased to increase the read charge amount. The overall circuit configuration is the same as that of the first embodiment shown in FIG. 1, and the cell plate signal generation circuit is also the same as that of the sixth embodiment shown in FIG.
Similar to 7, the dummy cell plate signal DCP of FIG. 17 becomes the cell plate signal CP. FIG. 20 is an operation timing chart. 21 is a hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of the first embodiment, and a curve 21 is a hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of the present embodiment.

WL0 to WL255 are word lines, DWL
0 and DWL1 are dummy word lines, BL and / BL are bit lines, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DC
RST is a dummy memory cell data initialization control signal, S
AE is a sense amplifier control signal, S1 is a control signal, N14
01 to N1403 are node names, VDD is power supply voltage, VS
S is a ground voltage, SA is a sense amplifier, C0 to C255 are main body memory cell capacitors, DC0 and DC1 are dummy memory cell capacitors, C1401 is a capacitor, Qn0.
~ Qn255, QnD0, QnD1, QnBP0, Qn
BP1, QnR0, QnR1 are N-channel MOS transistors, and QL is the main body memory cell "L" of the first embodiment.
Data read charge amount, QH is the main memory cell "H" data read charge amount of the first embodiment, QS is "L" data read charge amount QL of the main memory cell of the first embodiment.
And "H" data read charge amount QH, QL21 is the main body memory cell "L" data read charge amount of this embodiment,
QH21 is the body memory cell "H" data read charge amount of this embodiment, and QS21 is the difference between the "L" data read charge amount QL21 and "H" data read charge amount QH21 of the body memory cell of this embodiment.

The overall circuit configuration diagram is similar to that of FIG. 1 of the first embodiment. The cell plate signal generating circuit is similar to that of the sixth embodiment shown in FIG. Regarding the operation of the circuit of this ferroelectric memory device, the operation timing chart of FIG. 20 and FIG.
The description will be made with reference to the hysteresis characteristic diagram of the ferroelectric capacitor of the main body memory cell of No. 1. In the hysteresis characteristic diagram of the ferroelectric capacitor in FIG. 21, the horizontal axis represents the electric field applied to the memory cell capacitor, and the vertical axis represents the electric charge at that time. The operation timing of FIG. 20 is almost the same as that of FIG. 2 of the first embodiment, but the cell plate signal CP
The logic voltage "H" level of is higher than the power supply voltage VDD. In FIG. 21, a curve 21 indicates a hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and points B21 and E of the ferroelectric capacitor even when the electric field is zero.
As shown in 21, residual polarization remains. First, in order to read the data of the memory cell, the dummy memory cell data initialization control signal DCRST is set to the logical voltage “H”, and the dummy memory cell is set to the initial state so that the voltage is not applied. Further, the bit line precharge control signal BP is set to the logical voltage "H", so that the bit lines BL and / BL are set to the logical voltage "L". Also, word lines WL0 to WL25
5, the dummy word lines DWL0 and DWL1, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the ground voltage VSS which is the logical voltage "L". Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "L", the first electrode of the dummy memory cell is set to the floating state, and the bit line precharge control signal BP is set to the logic voltage "L". Bit line B
L and / BL are set in a floating state. Next, the word line WL0, the dummy word line DWL0, the cell plate electrode CP and the dummy cell plate electrode DCP are set to the logic voltage "H".
Then, the data of the main body memory cell is read to the bit line BL, and the data of the dummy memory cell is read to the bit line / BL. Here, it is assumed that the cell plate electrode CP has a logic voltage “H” that is a voltage boosted from the power supply voltage VDD (2 × VDD). When the data is "H", the state of the main body memory cell transits from point B21 to point D21 in FIG.
When the data is "L", the point QL in FIG. 21 transits to the point D21 and the charge QL is read out to the bit line BL. Further, the dummy memory cell is set so that the charge (QH21 + QL21) / 2 is read from the dummy memory cell as in the first embodiment. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. As a result, when the data is "H", the states of the main body memory cells change from point D21 to point E in FIG.
21, and the state of the dummy memory cell is point D in FIG.
21, the state of the main body memory cell holds the state of point D21 in FIG. 21, and the state of the dummy memory cell holds the state of 21 in FIG.
Transitions to. Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. As a result, the state of the main body memory cell transits from point E21 in FIG. 21 to point A21 when the data is “H”, and transits from point D21 in FIG. 21 to point E21 when the data is “L”. To do. Next, the word line WL0 and the dummy word line DWL0 are set to the logical voltage "L" so that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the dummy cell plate electrode DC
P is also set to the logic voltage "L" and the sense amplifier control signal SAE is set to the logic voltage "L" to stop the operation of the sense amplifier SA. Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "H" to initialize the dummy memory cells. Further, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the seventh embodiment, in the operation of the main body memory cell capacitor, the voltage value applied to both electrodes of the main body memory cell capacitor is increased by making the voltage of the cell plate electrode CP higher than the power supply voltage VDD during data reading. The characteristic feature is that the read charge amount is increased and the read charge amount difference is increased to enable stable operation or low voltage operation. Specifically, the read charge amount difference between the data “H” and the data “L” is approximately the charge amount difference QS21 in the present embodiment, whereas the charge amount difference QS in the first embodiment in FIG. 20% larger.

(Embodiment 8) Similar to the seventh embodiment, the eighth embodiment increases the amount of read charges when reading data from a memory cell. In the eighth embodiment, a 1-bit memory cell is composed of two ferroelectric capacitors and two transistors, and complementary data is stored in each ferroelectric capacitor. First, FIG. 22 is an overall circuit configuration diagram, and the cell plate generating circuit is similar to that of FIG. 17 of the sixth embodiment. FIG. 23 is an operation timing chart. Curve 4 in FIG. 24 shows the hysteresis characteristic of data reading / writing of the memory cell of the first embodiment, and curve 24 shows the hysteresis characteristic of data reading / writing of the memory cell of this embodiment.

WL0 to WL255 are word lines, BL, /
BL is a bit line, CP0 to CP255 are cell plate electrodes, BP is a bit line precharge control signal, SAE is a sense amplifier control signal, VSS is a ground voltage, SA is a sense amplifier, C0 to C255 and C0B to C255B are memory cell capacitors. , Qn0 to Qn255, Qn0B to Qn
255B, QnBP0 to QnBP2 are N-channel MO
S transistor, QL is the "L" data read charge amount of the first embodiment, QH is the "H" data read charge amount of the first embodiment, and QS is the "L" data read charge amount of the first embodiment. The charge amount difference between QL and the “H” data read charge amount QH, QL24 is the “L” data read charge amount of the present embodiment, QH24 is the “H” data read charge amount of the present embodiment, and QS24 is the present embodiment. This is the charge amount difference between the “L” data read charge amount QL24 and the “H” data read charge amount QH24.

First, the circuit configuration diagram of FIG. 22 will be described. Bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA is a sense amplifier control signal S
It is controlled by AE. The first electrode of the memory cell capacitor C0 is connected to the bit line BL via the memory cell transistor Qn0 whose gate electrode is connected to the word line WL0, and the second electrode is connected to the cell plate electrode CP0. The first electrode of the memory cell capacitor C0B forming a pair with the memory cell capacitor C0 has a gate electrode connected to the word line WL0.
It is connected to the bit line / BL via n0B, and the second electrode is connected to the cell plate electrode CP0. Other memory cell capacitors C1 to C255 and C1B to C255
The connection of B is similar to that of the memory cell capacitors C0 and C0B. The bit lines BL and / BL are connected by an N-channel MOS transistor QnBP2, and the bit line B
L and ground voltage VSS, bit line / BL and ground voltage VSS
Are N-channel MOS transistors QnBP
0 and QnBP1 are connected, and the gate electrodes of the N-channel type MOS transistors QnBP0 to QnBP2 are connected to the bit line precharge control signal BP. Further, the cell plate signal generation circuit is a circuit in which the potential level of the logic voltage "H" is boosted higher than the power supply voltage VDD as in the case of FIG. 17 of the sixth embodiment.

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing diagram of FIG. 23 and the hysteresis characteristic diagram of the ferroelectric capacitor of the memory cell of FIG. In the hysteresis characteristic diagram of the ferroelectric capacitor of FIG. 24, the horizontal axis represents the electric field applied to the memory cell capacitor, and the vertical axis represents the electric charge at that time. The operation timing of FIG. 23 is almost the same as that of the seventh embodiment of FIG. In FIG. 24, a curve 24 is the hysteresis characteristic of the ferroelectric capacitor of the memory cell, and in the ferroelectric capacitor, the point B24, even when the electric field is zero,
Remanent polarization remains as at point E24. The memory cell is composed of two ferroelectric capacitors that store complementary data,
Points B24 and E24 show remnant polarization, which is the stored complementary data.

First, in order to read the data of the memory cell, the bit line precharge control signal BP is set to the logical voltage "H", and the bit lines BL and / BL are set to the logical voltage "L". Also, word lines WL0 to WL25
5. The cell plate electrode CP is set to the ground voltage VSS which is the logic voltage "L". Next, the bit line precharge control signal BP is set to the logical voltage "L" to bring the bit lines BL and / BL into a floating state. Next, the word line WL0 and the cell plate electrode CP are set to the logical voltage “H”, and the data of the memory cell capacitors C0 and C0B are read to the bit line BL and the bit line / BL. Here, the logic voltage "H" is applied to the cell plate electrode CP as the power supply voltage VDD.
The voltage is increased. Memory cell capacitor C0
As for the states of C0B and C0B, regarding the memory cell capacitor C0, when the data is "H", the point B24 in FIG.
To D24, the charge QH24 is read, and when the data is "L", the charge QL24 is read to the bit line BL by transitioning from the point E24 to the point D24 in FIG. As for the memory cell capacitor C0B, the memory cell capacitor C0 operates in the opposite data state. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. As a result, when the data is "H", the state of the memory cell capacitor C0 transits from the point D24 of FIG. 24 to the point E24, and the state of the memory cell capacitor C0B holds the state of the point D24 of FIG. 24 is "L", the state of the memory cell capacitor C0 holds the state of the point D24 in FIG. 24, and the state of the memory cell capacitor C0B transits from the point D24 in FIG. 24 to the point B24. Next, the cell plate electrode CP is set to the logic voltage "L" to set the memory cell capacitors C0 and C0B.
Rewrite the data of. As a result, when the data is "H", the state of the memory cell capacitor C0 transits from the point E24 in FIG. 24 to the point A24, and the state of the memory cell capacitor C0B changes from the point D24 to the point E24 in FIG.
Transitions to. When the data is "L", the state of the memory cell capacitor C0 changes from point D24 to point E in FIG.
24, and the state of the memory cell capacitor C0B transits from point E24 to point A24 in FIG. Next, the word line WL0 is set to the logical voltage "L" so that the voltage is not applied to the memory cell capacitors C0 and C0B. next,
The sense amplifier control signal SAE is set to the logic voltage "L" to stop the operation of the sense amplifier SA. Next, the bit line precharge control signal BP is set to the logic voltage "H" to set the bit lines BL and / BL to the logic voltage "L" to be in the initial state.

In the eighth embodiment, as in the seventh embodiment, in the operation of the memory cell capacitor, the voltage of the cell plate electrode CP is set to the power supply voltage VDD when reading data.
The feature is that the voltage value applied between both electrodes of the memory cell capacitor is increased to increase the read charge amount and the read charge amount difference is increased to enable stable operation or low voltage operation. Specifically, the read charge amount difference between the data “H” and the data “L” is about the charge amount difference QS24 in the present embodiment, whereas the charge amount difference QS in the first embodiment in FIG. 20% larger.

(Embodiment 9) Like the seventh embodiment, the ninth embodiment is designed so that a large amount of read charge can be read out when reading data from the main body memory cell.
In this embodiment, the voltage level applied to both electrodes of the main body memory cell capacitor is increased by increasing the voltage level of the bit line whose logic voltage becomes “H” at the time of data rewriting to be higher than the power supply voltage VDD to increase the amount of retained charge. It does a lot. The overall circuit configuration diagram is similar to that of FIG. 1 of the first embodiment. As a method of increasing the amount of retained charges at the time of rewriting data, here, the power supply voltage level of the sense amplifier SA is set to the voltage source VPP higher than the power supply voltage VDD. Figure 25
6 is a circuit diagram in which the voltage source level of the sense amplifier SA is a voltage source VPP. FIG. 26 is an operation timing chart. Curve 4 in FIG. 27 shows the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of the first embodiment, and curve 27 shows the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of the present embodiment.

WL0 to WL255 are word lines, DWL
0 and DWL1 are dummy word lines, BL and / BL are bit lines, CP is a cell plate electrode, DCP is a dummy cell plate electrode, BP is a bit line precharge control signal, DC
RST is a dummy memory cell data initialization control signal, S
AE is a sense amplifier control signal, S1 is a control signal, N14
01 to N1403, SAP and SAN are node names, VDD
Is a power supply voltage, VSS is a ground voltage, SA is a sense amplifier,
C0 to C255 are main body memory cell capacitors, DC0,
DC1 is a dummy memory cell capacitor, C1401 is a capacitor, Qn0 to Qn2513, QnD0, QnD.
1, QnBP0, QnBP1, QnR0, QnR1 is N
Channel type MOS transistors, Qp2501 to Qp2
513 is a P channel type MOS transistor, VLS is a voltage level shifter, VPP is a voltage source, QL is a main body memory cell “L” data read charge amount of the first embodiment, and QH is a main body memory cell “H” of the first embodiment. "Data read charge amount, QS is the difference between" L "data read charge amount QL and" H "data read charge amount QH of the main body memory cell of the first embodiment, and QL27 is the main body memory cell" L "of the present embodiment.
Data read charge amount, QH27 is the main memory cell "H" data read charge amount of this embodiment, QS27 is the "L" data read charge amount QL of the main memory cell of this embodiment.
27 and "H" data read charge amount QH27.

The overall circuit configuration diagram is similar to that of the first embodiment shown in FIG. First, the circuit diagram of FIG. 25 in which the voltage source level of the sense amplifier SA is the voltage source VPP will be briefly described. This circuit receives the sense amplifier control signal SAE as an input, and the signal S whose input voltage level is the power supply voltage VDD.
AE is a signal SA whose output voltage level is the power supply voltage VCC
The voltage level shifter VLS outputs P and SAN, and the sense amplifier SA whose voltage source is VPP and is controlled by the signals SAP and SAN. The signal SAN is a signal whose logical voltage is in phase with the signal SAE, the signal SAP is a signal whose logical voltage is opposite in phase to the signal SAE, and the sense amplifier SA operates when the signal SAE is a logical voltage "H".

Next, the operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing diagram of FIG. 26 and the hysteresis characteristic diagram of the ferroelectric capacitor of the main body memory cell of FIG. In the hysteresis characteristic diagram of the ferroelectric capacitor in FIG. 27, the horizontal axis represents the electric field applied to the memory cell capacitor, and the vertical axis represents the electric charge at that time. The operation timing of FIG. 26 is almost the same as that of FIG. 2 of the first embodiment, but is characterized in that the logic voltage “H” level of the bit lines BL and / BL is higher than the power supply voltage VDD. In FIG. 27, a curve 27 indicates the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and in the ferroelectric capacitor, points B27 and E27 even when the electric field is zero.
Remnant polarization remains as shown in. First, in order to read the data of the memory cell, the dummy memory cell data initialization control signal DCRST is set to the logical voltage “H”, and the dummy memory cell is set to the initial state so that the voltage is not applied. Further, the bit line precharge control signal BP is set to the logical voltage "H", so that the bit lines BL and / BL are set to the logical voltage "L". Also, word lines WL0 to WL255, dummy word lines DWL0 and DWL1, cell plate electrode C
P and the dummy cell plate electrode DCP are set to the ground voltage VSS which is the logic voltage "L". Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "L", the first electrode of the dummy memory cell is set to the floating state, and the bit line precharge control signal BP is set to the logic voltage "L". Bit lines BL, / B
Let L be in a floating state. Next, word line WL0
The dummy word line DWL0, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the logical voltage "H", and the data of the main body memory cell is read to the bit line BL and the data of the dummy memory cell is read to the bit line / BL. The state of the main body memory cell is point B in FIG. 27 when the data is “H”.
The charge QH is transferred from 27 to the point D27, and when the data is "L", the charge QL is read to the bit line BL by transiting from the point E27 to the point D27 in FIG. In addition, charges (QH) are applied from the dummy memory cell as in the first embodiment.
The dummy memory cell is set so that 27 + QL27) / 2 is read. Next, the sense amplifier control signal S
AE is set to the logic voltage “H”, and the sense amplifier SA is operated. Here, the voltage source of the sense amplifier SA is the power supply voltage V
Since it is VPP which is the voltage boosted by DD, the voltage level of the bit line whose logic voltage becomes "H" when the sense amplifier SA operates is also VPP. As a result, when the data is "H", the state of the main body memory cell is as shown in FIG.
27, the state of the dummy memory cell retains the state of the point D27 of FIG. 27, and when the data is “L”, the state of the main body memory cell is the point D of FIG.
27, and the state of the dummy memory cell is as shown in FIG.
Transition from point D27 to point B27. Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. As a result, the state of the main body memory cell transits from point E27 in FIG. 27 to point A27 when the data is "H", and when the data is "L" in FIG.
Transition from point D27 to point E27. Next, the word line W
L0 and the dummy word line DWL0 are set to the logical voltage “L”,
Make sure that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the dummy cell plate electrode DCP is also set to the logical voltage "L" and the sense amplifier control signal SAE is set to the logical voltage "L" to stop the operation of the sense amplifier SA. Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "H".
Then, the state of the dummy memory cell is set to the initial state. Further, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the ninth embodiment, in the operation of the main body memory cell capacitor, the voltage level of the bit line whose logic voltage becomes "H" at the time of data rewriting is set to the power supply voltage VDD.
By making it higher, the voltage value applied between both electrodes of the main body memory cell capacitor is increased and the read charge amount is increased.
The feature is that the difference in the amount of read charges is increased to enable stable operation or low voltage operation. Specifically, the read charge amount difference between the data “H” and the data “L” is shown in FIG.
In contrast to the charge amount difference QS in the first embodiment, the charge amount difference QS27 in this embodiment is about 20% larger.

(Embodiment 10) Like the ninth embodiment, the tenth embodiment enables a large amount of read charge to be read when data is read from the main body memory cell. By raising the voltage level of the bit line whose voltage becomes “H” higher than the power supply voltage VDD, the voltage value applied between both electrodes of the main body memory cell capacitor is increased and the amount of retained charge is increased. The overall circuit configuration diagram is shown in FIG. As a method of increasing the amount of retained charges at the time of rewriting data, here, the voltage level of the bit line whose logic voltage becomes “H” after the operation of the sense amplifier SA is set to a power supply voltage level higher than the power supply voltage VDD. The sense amplifier SA in the overall circuit configuration diagram of FIG.
In the sense amplifier SA of FIG. 25 shown in the embodiment, the voltage source level does not have to be the voltage source VPP. FIG. 29 is an operation timing chart. The hysteresis characteristic diagram of the ferroelectric capacitor is similar to that of the ninth embodiment and is shown in FIG. Curve 4 in FIG. 27 shows the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of the first embodiment, and curve 27 shows the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of the present embodiment.

Only new symbols for the ninth embodiment will be described. 28 is a bit line boosting circuit, BBS is a bit line boosting control signal, and CB0 to CB1 are bit line boosting capacitors.

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing diagram of FIG. 29 and the hysteresis characteristic diagram of the ferroelectric capacitor of the main body memory cell of FIG. In the hysteresis characteristic diagram of the ferroelectric capacitor in FIG. 27, the horizontal axis represents the electric field applied to the memory cell capacitor, and the vertical axis represents the electric charge at that time. Figure 2
The operation timing of 9 is almost the same as that of FIG. 2 of the first embodiment, but when the bit line boost control signal BBS becomes the logical voltage "H", the logical voltage "H" of the bit line BL or / BL is changed. The feature is that the voltage level of the other bit line is boosted and becomes higher than the power supply voltage VDD. In FIG. 27, a curve 27 indicates the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell, and in the ferroelectric capacitor, remanent polarization remains at points B27 and E27 even when the electric field is zero. First, in order to read the data of the memory cell, the dummy memory cell data initialization control signal DCRST is set to the logical voltage “H”, and the dummy memory cell is set to the initial state so that the voltage is not applied. Further, the bit line precharge control signal BP is set to the logical voltage "H", so that the bit lines BL and / BL are set to the logical voltage "L". The bit line boost control signal BBS is the logic voltage "L". In addition, word lines WL0 to WL255, dummy word lines DWL0,
The DWL1, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the ground voltage VSS which is the logical voltage "L". Next, the dummy memory cell data initialization control signal D
By setting CRST to the logical voltage "L", setting the first electrode of the dummy memory cell to the floating state, and setting the bit line precharge control signal BP to the logical voltage "L", the bit lines BL and / BL are floated. State. Next, the word line WL0 and the dummy word line DWL0
And cell plate electrode CP and dummy cell plate electrode DC
P is a logic voltage "H", the data of the main body memory cell is on the bit line BL, and the data of the dummy memory cell is on the bit line /
Read to BL. When the data is "H", the state of the main body memory cell transits from point B27 to point D27 in FIG. 27 to charge QH, and when the data is "L" from point E27 to point D27 in FIG. Transition to charge QL to bit line BL
Read out. Further, the dummy memory cell is set so that the charge (QH27 + QL27) / 2 is read from the dummy memory cell as in the first embodiment. Next, the sense amplifier control signal SAE is set to the logic voltage "H",
The sense amplifier SA is operated. As a result, the bit lines BL and / BL become the logical voltage "L" and the logical voltage "H". Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. Next, the sense amplifier control signal SAE is set to the logic voltage "L", the sense amplifier SA is stopped, and the bit lines BL and / BL are brought into a floating state. Next, the bit line boost control signal BBS
Is set to the logic voltage "H", and the bit line having the logic voltage "H" is boosted. As a result, when the data is "H", the state of the main body memory cell changes from point E27 to point A27 in FIG.
And the data is "L", point D27 in FIG.
To the point E27. Next, the word line WL0 and the dummy word line DWL0 are set to the logical voltage "L" so that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the dummy cell plate electrode DCP is also set to the logic voltage "L", and the bit line boost control signal BBS is set to the logic voltage "L". Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "H" to initialize the dummy memory cells. Further, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the tenth embodiment, in the operation of the main body memory cell capacitor, the voltage level of the bit line whose logic voltage becomes "H" at the time of data rewriting is the power supply voltage V.
By making the voltage higher than DD, the voltage value applied between both electrodes of the main body memory cell capacitor is increased to increase the read charge amount, and the read charge amount difference is increased to enable stable operation or low voltage operation. . Specifically, the read charge amount difference between the data “H” and the data “L” is shown in FIG.
In contrast to the charge amount difference QS in the first embodiment, the charge amount difference QS27 in this embodiment is about 20% larger. Compared to the ninth embodiment, the tenth embodiment does not require the voltage source VPP and has a simple circuit configuration.

(Embodiment 11) The eleventh embodiment is a combination of the seventh embodiment and the ninth embodiment. A large amount of read charge is read out when reading data from the main body memory cell. By increasing the voltage of the cell plate electrode CP higher than the power supply voltage VDD when reading data, the voltage applied between both electrodes of the main body memory cell capacitor. The voltage value applied between both electrodes of the main body memory cell capacitor by increasing the value to increase the read charge amount and increasing the voltage level of the bit line whose logic voltage becomes “H” at the time of data rewriting to higher than the power supply voltage VDD. To increase the retained charge amount. The overall circuit configuration diagram is the same as that of the first embodiment and is FIG. Cell plate electrode CP
FIG. 17 shows a booster circuit that raises the voltage of the power supply voltage higher than the power supply voltage VDD.
Is. FIG. 25 shows a sense amplifier circuit for increasing the voltage level of the bit line whose logic voltage becomes “H” at the time of data rewriting to be higher than the power supply voltage VDD. FIG. 30 is an operation timing chart. FIG. 31 is a hysteresis characteristic diagram of the ferroelectric capacitor, and curve 4 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of the first embodiment, curve 3
1 is the hysteresis characteristic of the ferroelectric capacitor of the main body memory cell of this embodiment.

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing chart of FIG. 30 and the hysteresis characteristic chart of the ferroelectric capacitor of the main body memory cell of FIG. First, in order to read data in a memory cell, a dummy memory cell data initialization control signal D
CRST is set to the logic voltage "H", and the dummy memory cell is set to the initial state so that the voltage is not applied. Further, the bit line precharge control signal BP is set to the logical voltage "H", so that the bit lines BL and / BL are set to the logical voltage "L". Further, the word lines WL0 to WL255, the dummy word lines DWL0 and DWL1, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the ground voltage VSS which is the logical voltage “L”. Next, the dummy memory cell data initialization control signal DCRST is set to the logic voltage "L", the first electrode of the dummy memory cell is set to the floating state, and the bit line precharge control signal BP is set to the logic voltage "L". By doing so, the bit lines BL and / BL are brought into a floating state. Next, the word line WL0, the dummy word line DWL0, the cell plate electrode CP, and the dummy cell plate electrode DCP are set to the logical voltage "H", the data of the main body memory cell is set to the bit line BL, and the data of the dummy memory cell is set to the bit line / BL. Read to. Here, the logic voltage "H" applied to the cell plate electrode CP is a voltage boosted from the power supply voltage VDD. When the data is “H”, the state of the main body memory cell transits from the point B31 to the point D31 in FIG. 31 to change the charge QH, and when the data is “L”, from the point E31 to the point D31 in FIG. Transition to charge QL to bit line B
Read to L. The first from the dummy memory cell
The dummy memory cell is set so that the charge (QH31 + QL31) / 2 is read out as in the embodiment of FIG. Next, set the sense amplifier control signal SAE to the logical voltage "H".
Then, the sense amplifier SA is operated. Here, the voltage source of the sense amplifier SA is a voltage boosted from the power supply voltage VDD. Thereby, when the data is "H", the state of the main body memory cell transits from the point D31 of FIG. 31 to the point E31, the state of the dummy memory cell holds the state of the point D31 of FIG. 31, and the data is " In the case of L ″, the state of the main body memory cell holds the state of point D31 in FIG. 31, and the state of the dummy memory cell transits from point D31 in FIG. 31 to point B31. Next, the cell plate electrode CP is set to the logic voltage "L", and the data of the main body memory cell is rewritten. As a result, the state of the main body memory cell transits from point E31 in FIG. 31 to point A31 when the data is “H”, and transits from point D31 in FIG. 31 to the point E31 when the data is “L”. To do. Next, the word line WL0 and the dummy word line DWL0
Is set to a logic voltage "L" so that no voltage is applied to the main body memory cell capacitor and the dummy memory cell capacitor. Next, the dummy cell plate electrode DCP is also set to the logical voltage "L" and the sense amplifier control signal SAE is set to the logical voltage "L" to stop the operation of the sense amplifier SA. Next, the dummy memory cell data initialization control signal D
CRST is set to the logic voltage "H" to set the dummy memory cell to the initial state. Further, by setting the bit line precharge control signal BP to the logical voltage "H", the bit lines BL and / BL are set to the logical voltage "L" to be in the initial state.

In the eleventh embodiment, in the operation of the main body memory cell capacitor, the read charge amount is increased at the time of data read, the held charge amount is increased at the time of data rewrite, and the read charge amount difference is increased to stabilize. The feature is that it enables operation or low voltage operation. Specifically, the read charge amount difference between the data “H” and the data “L” is approximately equal to the charge amount difference QS31 in the present embodiment, whereas the charge amount difference QS in the first embodiment in FIG. 60
% Is getting bigger. A larger effect is obtained by combining the seventh embodiment and the ninth embodiment.

(Embodiment 12) In the twelfth embodiment, when the word line of the main body memory cell is set to the logic voltage "H" and then brought into the floating state, the cell plate electrode CP is set to the logic voltage "H", or the sense amplifier SA is used. So that when the bit line of data “H” becomes the logical voltage “H”, the voltage of the word line is boosted and increased by the voltage of the cell plate electrode and the capacitance between the bit line and the word line. It was done.

The overall circuit configuration diagram is similar to that of the first embodiment shown in FIG. FIG. 32 shows a word line drive circuit of the twelfth embodiment. FIG. 33 is an operation timing chart. WL0 is a word line, CP is a cell plate electrode, SAE is a sense amplifier control signal, WLG1 and WLS are control signals, and Qn320.
Reference numeral 1 is an N-channel type MOS transistor. In the word line driver circuit, the word line is connected to the drain of the transistor Qn3201, the source is connected to the signal in phase with the control signal WLS, and the gate electrode is connected to the control signal WLG1.

The operation of the word line drive circuit of the twelfth embodiment will be briefly described. First, in the initial state, the control signals WLS and SAE are at the logic voltage “L”, and the control signal WL is
G1 is the logic voltage "H", the word line WL0, and the cell plate electrode CP is the logic voltage "L". Next, the control signal WL
S is a logical voltage "H". Next, the control signal WLG1 is set to a logic voltage "H" having a higher voltage, and then the control signal WL
The original logic voltage “H”, which is the same voltage as the logic voltage “H” of S, is set. At this time, the word line WL0 has the logic voltage “H” that is the same as the logic voltage “H” of the control signal WLS, and the transistor Qn3201 is in the floating state because it is off. Next, when the cell plate electrode CP is set to the logic voltage “H”, the main body memory cell capacitor composed of the ferroelectric film is connected between the cell plate electrode CP and the word line WL0 via the memory cell transistor. Therefore, the voltage level of the logic voltage "H" of the word line WL0 becomes high due to the coupling due to the capacitance. Next, when the sense amplifier control signal SAE is set to the logic voltage “H” and the sense amplifier SA is operated,
If the bit line has the logical voltage "H", the word line WL0
The voltage level of the logic voltage "H" becomes even higher. next,
The cell plate electrode CP is set to the logic voltage "L" for rewriting data to the body memory cell capacitor. At this time, the voltage level of the logic voltage "H" of the word line WL0 also drops due to the coupling, but is higher than the voltage level of the original logic voltage "H". In this way, the voltage level of the logic voltage "H" of the word line WL0 becomes sufficiently high, so there is no voltage drop (Vt drop) due to the threshold voltage of the memory cell transistor, and there is no voltage drop between both electrodes of the main body memory cell capacitor. Since sufficient voltage is applied, sufficient data rewriting can be performed on the main body memory cell capacitor. After that, the control signal WLS is set to the logical voltage “L”,
The word line WL0 is at the logical voltage "L", and the sense amplifier control signal SAE is at the logical voltage "L" to be in the initial state.

(Embodiment 13) The thirteenth embodiment is similar to the twelfth embodiment, in which the word line of the main body memory cell is set to the logic voltage "H" and then brought into the floating state, and the cell plate electrode CP is set to the logic voltage "H". "When the sense amplifier S
When the bit line of the data “H” is set to the logic voltage “H” by operating A, the voltage of the word line is boosted by the cell plate electrode and the capacitance between the bit line and the word line to be high. It is a thing. The difference from the twelfth embodiment is that the voltage level when the word line first becomes the logic voltage "H" is set to a high voltage in advance by using the booster circuit.

The overall circuit configuration diagram is similar to that of the first embodiment shown in FIG. FIG. 34 shows a word line drive circuit of the thirteenth embodiment. FIG. 35 is an operation timing chart. WL0 is a word line, CP is a cell plate electrode, SAE is a sense amplifier control signal, WLG2 to WLG3 and WLS are control signals,
Qn3401 to Qn3404 are N-channel MOS transistors, C3401 is a capacitor, and N3401 to N3.
Reference numeral 404 is a node name. The word line drive circuit sets the inverted signal of the control signal WLS to the node N3401 and
The inverted signal of 3401 is set to the node N3402, and the node N
In phase with 3402, the output of the two-stage NOT circuit is applied to the node N34.
03, the capacitor C3401 is connected between the node N3403 and the node N3404.
Transistor Qn3401 is connected between the word line WL0 and the word line WL0, the gate electrode of the transistor Qn3401 receives the control signal WLG3, and the node N3402 and the control signal WLG.
3 is connected to the transistor Qn3404, and the gate electrode of the transistor Qn3404 is connected to the control signal WLG2.
Therefore, the transistor Qn3403 is connected between the word line WL0 and the ground voltage VSS, and the transistor Qn340
3 has a gate electrode at a node N3401 and a node N340.
4 and the power supply voltage VDD between the transistor Qn3402
Are connected, and the gate electrode of the transistor Qn3402 is at the power supply voltage VDD.

The operation of the word line drive circuit of the thirteenth embodiment will be briefly described. The operation is almost the same as that of the twelfth embodiment, and the control signal WLG of the thirteenth embodiment is used.
2 may be considered to operate at the timing of the control signal WLG1 of the twelfth embodiment. First, in the initial state, the control signals WLS and SAE are at the logic voltage “L”, and the control signal WL is
G2 is the logic voltage "H", the word line WL0, and the cell plate electrode CP is the logic voltage "L". Next, the control signal WL
S is a logical voltage "H". Next, the control signal WLG2 is set to a logic voltage "H" having a higher voltage, and then the control signal WL
The original logic voltage “H”, which is the same voltage as the logic voltage “H” of S, is set. At this time, the node N3404 and the word line WL0 have a voltage "VDD lower than the power supply voltage VDD by the threshold voltage Vtn of the N-channel MOS transistor.
-Vtn ". Next, the node N3403 transitions from the logic voltage" L "to the logic voltage" H "with a delay from the signal transition of the control signal WLS. Then, the node N3404 is driven to the voltage (VDD- by the capacitor C3401). Vtn)
To (2 × VDD-Vtn). At this time, since the transistor Qn3401 is off, the word line WL0 is in a floating state. Next, when the cell plate electrode CP is set to the logic voltage “H”, the main body memory cell capacitor composed of the ferroelectric film is connected between the cell plate electrode CP and the word line WL0 via the memory cell transistor. Therefore, the voltage level of the logic voltage "H" of the word line WL0 becomes high due to the coupling due to the capacitance. Next, the cell plate electrode CP is set to the logic voltage "L" for rewriting data to the main body memory cell capacitor. At this time, the voltage level of the logic voltage "H" of the word line WL0 also drops due to the coupling, but is higher than the voltage level of the original logic voltage "H". In this way, the voltage level of the logic voltage “H” of the word line WL0 becomes sufficiently high, so that there is no voltage drop (Vt drop) due to the threshold voltage of the memory cell transistor,
Since a sufficient voltage is applied between both electrodes of the main body memory cell capacitor, it is possible to sufficiently rewrite data to the main body memory cell capacitor. After this, the control signal WL
S is set to the logical voltage "L", and the word line WL0 is set to the logical voltage "L" to be in the initial state.

Incidentally, 1 according to the ninth to thirteenth embodiments
The fact that the T1C type ferroelectric memory device can be easily modified to the 2T2C type is similar to the relationship between the seventh embodiment and the eighth embodiment.

(Embodiment 14) In the fourteenth embodiment, when the main body memory cell capacitor selected at the time of rewriting the data of the main body memory cell is the logical voltage "L" of the bit line electrically connected, the word After the line is set to the non-selected state of the logic voltage "L", the cell plate electrode is set to the logic voltage "L" to increase the charge amount for rewriting the data "L" so that a large amount of the read charge amount can be read at the time of reading. It is a thing.

The overall circuit configuration diagram is the same as that of FIG. 1 of the first embodiment. FIG. 36 shows a control circuit for generating the word line drive signal WL and the cell plate electrode signal CP, and FIG.
Is a control circuit for generating signals to the word lines WL0 and WL1 from the word line drive signal WL and the address signal A0. FIG. 38 is an operation timing chart of these circuits. FIG. 39 is a hysteresis characteristic diagram of the ferroelectric capacitor of the main body memory cell.

The overall circuit configuration diagram is the same as that of the first embodiment shown in FIG. 36 and 37
The control circuit will be described. WLCP is a control signal, W
L is a drive signal for a word line, CP is a cell plate electrode and its signal, WL0 to WL1 are word lines, A0 is an address signal, BL is a bit line and its signal, INV3601 to
INV3703 is a negative circuit, NAND 3601 to NAN
D3702 is a logical product negation circuit, NOR 3601 to NO
R3602 is a logical sum negation circuit, EXNOR3601 is an exclusive logical sum negation circuit, and N3601 to N3703 are node names. The circuit configuration is an exclusive OR negation circuit E.
XNOR3601 is a bit line signal BL and an address signal A.
0 is an input, node N3601 is an output, and NOT circuit INV3606 receives N3601 as an input and node N360
2 is an output, the control signal WLCP is an input, and a NOT circuit I
The outputs of the five-stage NOT circuits of NV3601 to INV3605 are set to the node N3603, and the AND circuit NAND3
A node 601 receives the node N3602 and the node N3603 as input, outputs the node N3604, and outputs a logical product NOT circuit N.
AND3602 is a node N3601 and a node N3603.
Is input and the node N3605 is output. The logical sum negation circuit NOR3601 outputs the control signal WLCP and the node N3.
604 as an input, a node N3606 as an output, a logical sum NOR circuit NOR3602 as inputs with a control signal WLCP and a node N3605 as an output, and a NOT circuit INV3607 with N3606 as an input and a word line drive signal WL as an output. And negation circuit INV36
08 receives N3607 as an input and cell plate electrode signal C
P is output. Further, the NOT circuit INV3701 receives the address signal A0 as an input and outputs the node N3701, and the NAND circuit NAND3701 receives the drive signal WL of the word line and the node N3701 as an input and the node N3.
702 as an output and a NAND circuit NAND3702 for the logical product
Receives the drive signal WL of the word line and the address signal A0, outputs the node N3703, and outputs the NOT circuit INV37.
02 inputs N3702 and outputs the word line WL0, and the NOT circuit INV3703 inputs N3703 and outputs the word line WL1. In this circuit, the word line WL0 is selected when the address signal A0 is the logical voltage "L", and the word line WL1 is selected when the address signal A0 is the logical voltage "H". In addition, at the time of data rewriting and when the selected main body memory cell capacitor has the logic voltage “L” of the bit line electrically connected to it, the word line is set to the non-selected state of the logic voltage “L”. After that, the cell plate electrode is set to the logic voltage "L".
FIG. 38 is an operation timing diagram, and the operation will be briefly described with reference to the hysteresis characteristic diagram of the ferroelectric capacitor of the main body memory cell of FIG. P3801-P38
04 is a period, and in a period P3801, the cell plate signal CP is the logical voltage "L" after the address signal A0 is the logical voltage "L", the data of the bit line BL is "L" and the word line WL0 becomes the logical voltage "L". L ". At this time, the state of the main body memory cell in which the data is rewritten is point D in FIG.
It is 4. In the period P3802, after the address signal A0 is the logical voltage “L”, the data of the bit line BL is the “H”, and the cell plate signal CP becomes the logical voltage “L”, the word line WL0 becomes the logical voltage “L”. At this time, the state of the main body memory cell in which the data has been rewritten is point A4 in FIG. In the period P3803, the address signal A0 is the logical voltage “H”, and the data of the bit line / BL is “H” (the bit line B
After the data of L is "L") and the cell plate signal CP becomes the logical voltage "L", the word line WL1 becomes the logical voltage "L". At this time, the state of the main body memory cell in which the data has been rewritten is point A4 in FIG. P3804
Address signal A0 is logical voltage "H" and bit line / BL
Is "L" (the data on the bit line BL is "H") and the word line WL1 is at the logical voltage "L", and then the cell plate signal CP is at the logical voltage "L". At this time, the state of the main body memory cell in which the data is rewritten is shown in FIG.
Is point D4.

As described above, in the fourteenth embodiment, the charge amount for rewriting is increased depending on the operation timing of the word line and the cell plate electrode, and the read charge amount can be read at the time of reading, and stable operation or low voltage operation is possible. .

(Fifteenth Embodiment) A fifteenth embodiment is a dummy cell when the dummy memory cell capacitor selected at the time of data rewriting of the dummy memory cell is the logical voltage "L" of the bit line electrically connected. By setting the plate electrode to the non-selected state of the logic voltage "L" and setting the dummy word line to the logic voltage "L", the state of the dummy memory cell is initialized. FIG. 40 is an overall circuit configuration diagram, in which the dummy memory cell of FIG. 1 of the first embodiment does not have an initialization circuit. FIG. 41 shows the dummy word line drive signal DWL and the dummy cell plate electrode signal D.
42 is a control circuit for generating CP and FIG. 42 is a control circuit for generating signals from the dummy word line drive signal DWL and the address signal A0 to the dummy word lines DWL0 and DWL1. FIG. 43 is an operation timing chart of these circuits. FIG. 44 is a hysteresis characteristic diagram of the ferroelectric capacitor of the dummy memory cell. Since the overall circuit configuration diagram of FIG. 40 is almost the same as that of FIG. 1 of the first embodiment, its explanation is omitted.

The control circuit shown in FIGS. 41 and 42 will be described. The circuit diagram of FIG. 41 is similar to the circuit diagram of FIG.
The circuit diagram of is similar to the circuit diagram of FIG. DWLDCP
Is a control signal, DWL is a drive signal for the dummy word line, DC
P is a dummy cell plate electrode and its signal, DWL0,
DWL1 is a word line, A0 is an address signal, BL is a bit line and its signal, INV4101 to INV4203 are NOT circuits, NAND4101 to NAND4202 are NAND circuits, NOR4101 to NOR4102 are NOR circuits, and EXNOR4101 is exclusive logic. Negation circuits for sums, N4101 to N4203, are node names. The circuit configuration is an exclusive OR negation circuit EXNOR4101.
Receives the bit line signal BL and the address signal A0 as an input and outputs the node N4101, the negation circuit INV4106 receives N4101 as an input and the node N4102 as an output, and the control signal DWLDCP as an input and the negation circuit INV4101.
~ The output of the 5 stage NOT circuit of INV4105 is set to the node N4.
103, and the NAND circuit NAND4101 receives the nodes N4102 and N4103 as inputs and
4104 as an output and a NAND circuit NAND410 of the logical product
The node 2 inputs the nodes N4101 and N4103, outputs the node N4105, and outputs a NOR circuit NOR of the logical sums.
Reference numeral 4101 inputs the control signal DWLDCP and the node N4104 and outputs the node N4106. The logical sum negation circuit NOR4102 controls the control signal DWLDCP and the node N4102.
4105 as an input, the node N4107 as an output, the NOT circuit INV4107 as an input of N4106, the drive signal DWL of the dummy word line as an output, and the NOT circuit INV
4108 has N4107 as an input and a dummy cell plate electrode signal DCP as an output. Also, the negation circuit IN
V4201 receives the address signal A0 as an input, and receives the node N42.
01 is an output, and the NAND circuit NAND4201 inputs the drive signal DWL of the dummy word line and the node N4201 and outputs the node N4202. The NAND circuit NAND4202 outputs the drive signal DW of the dummy word line.
L and address signal A0 are input, node N4203 is output, NOT circuit INV4202 receives N4202 as input, dummy word line DWL0 is output, and NOT circuit I
The NV4203 inputs N4203 and outputs the dummy word line DWL1. This circuit uses address signal A
When 0 is the logical voltage "L", the dummy word line DWL0 is selected, and when the address signal A0 is the logical voltage "H", the dummy word line DWL1 is selected. When the dummy memory cell capacitor selected at the time of data rewriting is the logic voltage “H” of the bit line electrically connected, the dummy word line is set to the non-selection state of the logic voltage “L”. The dummy cell plate electrode is set to the logic voltage "L". FIG. 43 is an operation timing chart, and FIG.
The operation will be briefly described with reference to the hysteresis characteristic diagram of the ferroelectric capacitor of the main body memory cell. P
4301 to P4304 are periods, and in the period P4301, the dummy word line DWL0 is set after the address signal A0 is the logical voltage “L”, the data of the bit line BL is “L”, and the dummy cell plate signal DCP is the logical voltage “L”. The logic voltage becomes “L”. In the period P4302, the dummy cell plate signal DCP becomes the logical voltage "L" after the address signal A0 is the logical voltage "L" and the data of the bit line BL is "H" and the dummy word line DWL0 becomes the logical voltage "L". . In the period P4303, the address signal A0 is the logical voltage “H”, and the data on the bit line / BL is “H” (bit line B
Since the data of L is "L") and the dummy word line DWL1 becomes the logic voltage "L", the dummy cell plate signal D
CP becomes the logic voltage "L". P4304 is a dummy after the address signal A0 is the logical voltage "H", the data of the bit line / BL is "L" (the data of the bit line BL is "H"), and the dummy cell plate signal DCP becomes the logical voltage "L". The word line DWL1 becomes the logical voltage "L". In any of the periods P4301 to P4304, the state of the dummy memory cell is point O in FIG.

As described above, in the fifteenth embodiment, the dummy memory cells can be set to the initialized state depending on the operation timings of the dummy word lines and the dummy cell plate electrodes, and the circuit structure is simplified.

(Embodiment 16) The sixteenth embodiment is similar to the fourteenth and fifteenth embodiments in that the read charge amount is increased when data is read from the memory cell. In the sixteenth embodiment, a 1-bit memory cell is composed of two ferroelectric capacitors and two transistors, and complementary data is stored in each ferroelectric capacitor. Among the bit lines electrically connected to the two memory cell capacitors selected at the time of rewriting the data of the memory cell, the bit line having the logical voltage “L” is defined as the word line being in the non-selected state of the logical voltage “L”. After that, the cell plate electrode is set to the logic voltage "L" to increase the charge amount for rewriting the data "L", and the bit of the logic voltage "H" electrically connected to the other memory cell capacitor. For the line, the cell plate electrode is set to the logic voltage "L" and then the word line is set to the non-selection state of the logic voltage "L" to increase the charge amount for rewriting the data "H". A large amount of the read charge is read out. First, FIG. 45 is an overall circuit configuration diagram. FIG. 46 is an operation timing chart. A curve 47 in FIG. 47 is the hysteresis characteristic of data read / write of the memory cell of this embodiment. This circuit configuration is different from the eighth embodiment shown in FIG. 22 in that the cell plate electrodes of the two ferroelectric capacitors storing complementary data are independently present.

WL0 to WL255 are word lines, BL, /
BL is a bit line, CP0A to CP255A, CP0B to
CP255B is a cell plate electrode, BP is a bit line precharge control signal, SAE is a sense amplifier control signal, V
SS is a ground voltage, SA is a sense amplifier, C0 to C25
5, C0B to C255B are memory cell capacitors, Qn
0-Qn255, Qn0B-Qn255B, QnBP0
~ QnBP2 is an N channel type MOS transistor, QL
Reference numeral 47 is the "L" data read charge amount of this embodiment, QH4
Reference numeral 7 is the amount of "H" data read charge in this embodiment, QS47
Is a charge amount difference between the “L” data read charge amount QL47 and the “H” data read charge amount QH47 in the present embodiment. Here, QL47 is almost 0, and QH47 is point A.
It is the charge amount from 47 to point D47. Therefore, Q
S47 has a charge amount substantially equal to QH47.

First, the circuit configuration diagram of FIG. 45 will be described. Bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA is a sense amplifier control signal S
It is controlled by AE. The first electrode of the memory cell capacitor C0 is connected to the bit line BL via the memory cell transistor Qn0 whose gate electrode is connected to the word line WL0, and the second electrode is connected to the cell plate electrode CP0A. The first electrode of the memory cell capacitor C0B paired with the memory cell capacitor C0 is connected to the bit line / BL via the memory cell transistor Qn0B whose gate electrode is connected to the word line WL0, and the second electrode is It is connected to another cell plate electrode CP0B.
Other memory cell capacitors C1 to C255 and C1B to
C255B is connected to memory cell capacitors C0 and C
Same as 0B. The bit lines BL and / BL are connected by an N-channel MOS transistor QnBP2, and the bit line BL and the ground voltage VSS and the bit line / BL and the ground voltage VSS are N-channel MOS transistor Q, respectively.
n-channel MOS connected by nBP0 and QnBP1
The gate electrodes of the transistors QnBP0 to QnBP2 are connected to the bit line precharge control signal BP.

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing chart of FIG. 46 and the hysteresis characteristic chart of the ferroelectric capacitor of the memory cell of FIG. In the hysteresis characteristic diagram of the ferroelectric capacitor of FIG. 47, the horizontal axis represents the electric field applied to the memory cell capacitor, and the vertical axis represents the electric charge at that time. In FIG. 47, a curve 47 is the hysteresis characteristic of the ferroelectric capacitor of the memory cell, and in the ferroelectric capacitor, remanent polarization remains at points B47 and E47 even when the electric field is zero. Further, here, the memory cell is composed of two ferroelectric capacitors that store complementary data in a state where an electric field is applied to the ferroelectric capacitor at the time of rewriting data, and the state is at point A47 and point D47. .

First, in order to read the data of the memory cell, the bit line precharge control signal BP is set to the logical voltage "H", and the bit lines BL and / BL are set to the logical voltage "L". Also, word lines WL0 to WL25
5. The cell plate electrodes CP0A and CP0B are set to the ground voltage VSS which is the logic voltage "L". Next, the bit line precharge control signal BP is set to the logical voltage "L" to bring the bit lines BL and / BL into a floating state. Next, the word line WL0 and the cell plate electrode CP0
A and CP0B are set to the logic voltage "H", and the data of the memory cell capacitors C0 and C0B are read to the bit line BL and the bit line / BL. Memory cell capacitors C0 and C
Regarding the state of 0B, regarding the memory cell capacitor C0, when the data is “H”, the charge QH47 transitions from the point A47 of FIG. 47 to the point D47, and when the data is “L”, the charge QH47 of FIG. Charge QL47 (= 0) at point D47
Is read to the bit line BL. As for the memory cell capacitor C0B, the memory cell capacitor C0 operates in the opposite data state. Next, the sense amplifier control signal SAE is set to the logic voltage "H", and the sense amplifier S
Operate A. As a result, when the data is "H", the state of the memory cell capacitor C0 is point D4 in FIG.
7 to the point E47, the memory cell capacitor C0B
47 holds the state of point D47 in FIG. 47, then sequentially sets the cell plate electrode CP0A to the logical voltage “L”, the word line WL0 to the logical voltage “L”, and the cell plate electrode C
The data of the memory cell capacitors C0 and C0B is rewritten by setting P0B to the logical voltage “L”.
Accordingly, when the data is "H", the state of the memory cell capacitor C0 transits from the point E47 of FIG. 47 to the point A47, and the state of the memory cell capacitor C0B is the state of the point D47 of FIG. After that, the sense amplifier control signal SAE is set to the logic voltage "L" to stop the operation of the sense amplifier SA. Next, the bit line precharge control signal B
By setting P to the logical voltage "H", the bit line B
L and / BL are set to a logic voltage "L" to be in an initial state. When the data is opposite to this, the data is read at the same timing, but when the data is rewritten, the cell plate electrode CP0B is sequentially set to the logical voltage "L" and the word line WL0 is set to the logical voltage "L". Then, the cell plate electrode CP0A is set to the logic voltage "L".

In the sixteenth embodiment, after the cell plate electrode of the memory cell capacitor whose data is "H" is set to the logical voltage "L", the word line is set to the logical voltage "L",
After that, by setting the cell plate electrode of the memory cell capacitor whose data is “L” to the logical voltage “L”, a voltage is applied between both electrodes of the memory cell capacitor in the data rewriting state, and the read operation is performed. The feature is that the difference in the amount of read charge at the time is increased to enable stable operation or low voltage operation.

(Embodiment 17) The seventeenth embodiment is similar to the sixteenth embodiment in that the read charge amount is increased when data is read from the memory cell. 1 in the seventeenth embodiment
A bit memory cell is composed of two ferroelectric capacitors and two transistors, and complementary data is stored in each ferroelectric capacitor. Of the bit lines electrically connected to the two memory cell capacitors selected at the time of rewriting the data in the memory cell, the bit line having the logical voltage "L" causes the word line to have the logical voltage "L".
The cell plate electrode is set to the logic voltage "L" after the non-selection state of "1" to increase the charge amount for rewriting the data "L", and the logic voltage electrically connected to the other memory cell capacitor. For the “H” bit line, the cell plate electrode is set to the logical voltage “L” and then the word line is set to the non-selected state of the logical voltage “L” to increase the charge amount for rewriting the data “H”. Therefore, a large amount of read charge can be read at the time of reading. First, FIG. 48 is an overall circuit configuration diagram. FIG.
9 is an operation timing chart. This circuit configuration is different from the eighth embodiment of FIG. 22 in that word lines which are gate electrodes of select transistors (memory cell transistors) of two ferroelectric capacitors storing complementary data are independently present. Is.

WL0A to WL255A, WL0B to WL
255B is a word line, BL, / BL is a bit line, CP0
~ CP255 is a cell plate electrode, BP is a bit line precharge control signal, SAE is a sense amplifier control signal, V
SS is a ground voltage, SA is a sense amplifier, C0 to C25
5, C0B to C255B are memory cell capacitors, Qn
0-Qn255, Qn0B-Qn255B, QnBP0
-QnBP2 are N-channel type MOS transistors.

First, the circuit configuration diagram of FIG. 48 will be described. Bit lines BL and / BL are connected to the sense amplifier SA. The sense amplifier SA is a sense amplifier control signal S
It is controlled by AE. The first electrode of the memory cell capacitor C0 is connected to the bit line BL via the memory cell transistor Qn0 whose gate electrode is connected to the word line WL0A, and the second electrode is connected to the cell plate electrode CP0. The first electrode of the memory cell capacitor C0B paired with the memory cell capacitor C0 is connected to the bit line / BL via the memory cell transistor Qn0B whose gate electrode is connected to another word line WL0B, and is connected to the second electrode. The electrode is connected to the cell plate electrode CP0.
Other memory cell capacitors C1 to C255 and C1B to
C255B is connected to memory cell capacitors C0 and C
Same as 0B. The bit lines BL and / BL are connected by an N-channel MOS transistor QnBP2, and the bit line BL and the ground voltage VSS and the bit line / BL and the ground voltage VSS are N-channel MOS transistor Q, respectively.
n-channel MOS connected by nBP0 and QnBP1
The gate electrodes of the transistors QnBP0 to QnBP2 are connected to the bit line precharge control signal BP.

The operation of the circuit of this ferroelectric memory device will be described with reference to the operation timing chart of FIG. Here, as in the sixteenth embodiment, an electric field is applied to the two ferroelectric capacitors storing complementary data when rewriting data. Further, in order to make the electric field applied to the ferroelectric capacitors at the time of rewriting data, in the seventeenth embodiment, the word lines which are the gate electrodes of the two ferroelectric capacitors storing complementary data are made independent, The cell plate electrode is shared and controlled.

First, in order to read the data of the memory cell, the bit line precharge control signal BP is set to the logical voltage "H", and the bit lines BL and / BL are set to the logical voltage "L". In addition, word lines WL0A to WL2
55A, WL0B to WL255B, cell plate electrode C
Let P0 be the ground voltage VSS which is the logical voltage "L". Next, the bit line precharge control signal BP is set to the logical voltage "L" to bring the bit lines BL and / BL into a floating state. Next, word lines WL0A, W
The logical voltage "H" is applied to L0B and the cell plate electrode CP0, and the data in the memory cell capacitors C0 and C0B are read out to the bit line BL and the bit line / BL. Next, the sense amplifier control signal SAE is set to the logic voltage "H" to operate the sense amplifier SA. Then, sequentially word line WL0B
Is set to the logic voltage "L", the cell plate electrode CP0 is set to the logic voltage "L", and the word line WL0A is set to the logic voltage "L", thereby setting the memory cell capacitors C0 and C0B.
Rewrite the data of. After that, the sense amplifier control signal SAE is set to the logic voltage "L" to stop the operation of the sense amplifier SA. Next, the bit line precharge control signal BP is set to the logic voltage "H" to set the bit lines BL and / BL to the logic voltage "L" to be in the initial state. If the data is the opposite of this, the data is read at the same timing, but when the data is rewritten,
Sequentially, the word line WL0A is set to the logic voltage "L", the cell plate electrode CP0 is set to the logic voltage "L", and the word line WL0 is set.
B is a logical voltage "L".

In the seventeenth embodiment, the word line which is the gate electrode of the select transistor of the memory cell capacitor having the data "L" is set to the logic voltage "L", and the cell plate electrode is set to the logic voltage "L". After that, by setting the word line, which is the gate electrode of the selection transistor of the memory cell capacitor in which the data is “H”, to the logical voltage “L”, both electrodes of the memory cell capacitor in the data rewriting state are connected. A characteristic is that a voltage is applied and the difference in the amount of read charges at the time of reading is increased to enable stable operation or low voltage operation.

[0102]

As described above, according to the present invention, it is possible to increase the operation margin of the ferroelectric memory device, prevent malfunction, and achieve stable operation and low voltage operation. .

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a ferroelectric memory device according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the ferroelectric memory device according to the first embodiment of the present invention.

FIG. 3 is a hysteresis characteristic diagram of a main body memory cell capacitor and a dummy memory cell capacitor of the ferroelectric memory device according to the first embodiment of the present invention.

FIG. 4 is a hysteresis characteristic diagram of a main body memory cell capacitor for explaining a method of determining both hysteresis characteristics in FIG.

FIG. 5 is a hysteresis characteristic diagram of a main body memory cell capacitor and a dummy memory cell capacitor of a ferroelectric memory device of a comparative example with respect to the first embodiment of the present invention.

FIG. 6 is a hysteresis characteristic diagram of a main body memory cell capacitor and a dummy memory cell capacitor of a ferroelectric memory device according to a second embodiment of the present invention.

7 is a hysteresis characteristic diagram for explaining a method of determining the hysteresis characteristic of the dummy memory cell capacitor in FIG.

FIG. 8 is a circuit configuration diagram of a ferroelectric memory device according to a third embodiment of the present invention.

FIG. 9 is an operation timing chart of the ferroelectric memory device according to the third embodiment of the present invention.

FIG. 10 is a circuit configuration diagram of a ferroelectric memory device according to a fourth embodiment of the present invention.

FIG. 11 is an operation timing chart of the ferroelectric memory device according to the fourth embodiment of the present invention.

FIG. 12 is a hysteresis characteristic diagram of a main body memory cell capacitor and a dummy memory cell capacitor of a ferroelectric memory device according to a fourth embodiment of the present invention.

13A and 13B are configuration diagrams of a control circuit for generating a signal of a cell plate electrode and a signal of a dummy cell plate electrode of a ferroelectric memory device according to a fourth embodiment of the present invention. .

FIG. 14 is a circuit configuration diagram of a ferroelectric memory device according to a fifth embodiment of the present invention.

FIG. 15 is an operation timing chart of the ferroelectric memory device according to the fifth embodiment of the present invention.

FIG. 16 is a hysteresis characteristic diagram of a main body memory cell capacitor and a dummy memory cell capacitor of a ferroelectric memory device according to a fifth embodiment of the present invention.

FIG. 17 is a configuration diagram of a control circuit for generating a signal of a dummy cell plate electrode of a ferroelectric memory device according to a sixth embodiment of the present invention.

FIG. 18 is an operation timing chart of the ferroelectric memory device according to the sixth embodiment of the present invention.

FIG. 19 is a hysteresis characteristic diagram of a main body memory cell capacitor and a dummy memory cell capacitor of a ferroelectric memory device according to a sixth embodiment of the present invention.

FIG. 20 is an operation timing chart of the ferroelectric memory device according to the seventh embodiment of the present invention.

FIG. 21 is a hysteresis characteristic diagram of a main body memory cell capacitor of the seventh embodiment of the present invention.

FIG. 22 is a circuit configuration diagram of a ferroelectric memory device according to an eighth embodiment of the present invention.

FIG. 23 is an operation timing chart of the ferroelectric memory device according to the eighth embodiment of the present invention.

FIG. 24 is a hysteresis characteristic diagram of the complementary memory cell capacitor of the ferroelectric memory device according to the eighth embodiment of the present invention.

FIG. 25 is a configuration diagram of a sense amplifier and its drive circuit in a ferroelectric memory device according to a ninth embodiment of the present invention.

FIG. 26 is an operation timing chart of the ferroelectric memory device according to the ninth embodiment of the present invention.

FIG. 27 is a hysteresis characteristic diagram of a main body memory cell capacitor of the ferroelectric memory device according to the ninth embodiment of the present invention.

FIG. 28 is a circuit configuration diagram of a ferroelectric memory device according to a tenth embodiment of the present invention.

FIG. 29 is an operation timing chart of the ferroelectric memory device according to the tenth embodiment of the present invention.

FIG. 30 is an operation timing chart of the ferroelectric memory device according to the eleventh embodiment of the present invention.

FIG. 31 is a hysteresis characteristic diagram of a main body memory cell capacitor of a ferroelectric memory device according to an eleventh embodiment of the present invention.

FIG. 32 is a configuration diagram of a word line drive circuit of a ferroelectric memory device according to a twelfth embodiment of the present invention.

FIG. 33 is an operation timing chart of the ferroelectric memory device according to the twelfth embodiment of the present invention.

FIG. 34 is a configuration diagram of a word line drive circuit of a ferroelectric memory device according to a thirteenth embodiment of the present invention.

FIG. 35 is an operation timing chart of the ferroelectric memory device according to the thirteenth embodiment of the present invention.

FIG. 36 is a configuration diagram of a control circuit for generating a word line drive signal and a cell plate electrode signal of a ferroelectric memory device according to a fourteenth embodiment of the present invention.

FIG. 37 is a configuration diagram of a word line drive circuit of a ferroelectric memory device according to a fourteenth embodiment of the present invention.

FIG. 38 is an operation timing chart of the ferroelectric memory device according to the fourteenth embodiment of the present invention.

FIG. 39 is a hysteresis characteristic diagram of a main body memory cell capacitor of a ferroelectric memory device according to the fourteenth embodiment of the present invention.

FIG. 40 is a circuit configuration diagram of a ferroelectric memory device according to a fifteenth embodiment of the present invention.

FIG. 41 is a configuration diagram of a control circuit for generating a dummy word line drive signal and a dummy cell plate electrode signal of a ferroelectric memory device according to a fifteenth embodiment of the present invention.

FIG. 42 is a configuration diagram of a dummy word line drive circuit of the ferroelectric memory device of the fifteenth embodiment of the present invention.

FIG. 43 is an operation timing chart of the ferroelectric memory device according to the fifteenth embodiment of the present invention.

FIG. 44 is a hysteresis characteristic diagram of the dummy memory cell capacitor of the ferroelectric memory device according to the fifteenth embodiment of the present invention.

FIG. 45 is a circuit configuration diagram of a ferroelectric memory device according to a sixteenth embodiment of the present invention.

FIG. 46 is an operation timing chart of the ferroelectric memory device according to the sixteenth embodiment of the present invention.

FIG. 47 is a hysteresis characteristic diagram of the complementary memory cell capacitor of the ferroelectric memory device according to the sixteenth embodiment of the present invention.

FIG. 48 is a circuit configuration diagram of a ferroelectric memory device according to a seventeenth embodiment of the present invention.

FIG. 49 is an operation timing chart of the ferroelectric memory device according to the seventeenth embodiment of the present invention.

[Explanation of symbols]

WL0-WL255, WL0A-WL255A, WL0
B to WL255B Word line DWL0, DWL1 Dummy word line BL, / BL Bit line and its signal CP, CP0 to CP255, CP0A to CP255A,
CP0B to CP255B Cell plate electrode and its signal DCP Dummy cell plate electrode and its signal BP Bit line precharge control signal DCRST Dummy memory cell data initialization control signal SAE Sense amplifier control signal S1, WLG1 to WLG3, WLS, WLCP, DWL
DCP control signal VSS ground voltage VCC power supply voltage VPP voltage source SA sense amplifier C0 to C255, C0B to C255B main body memory cell capacitor DC0, DC1 dummy memory cell capacitor C1701 to C3401 capacitor Qn0 to Qn3404, Qn0B to Qn255B, Qn
D0, QnD1, QnR0 to QnR3, QnBP0 to Q
nBP2 N-channel MOS transistor Qp, QpR0 to QpR1, Qp1701 to Qp251
3 P-channel type MOS transistor VLS Voltage level shifter 28 Bit line boosting circuit BBS Bit line boosting control signal CB0 to CB1 Bit line boosting capacitor WL Word line drive signal DWL Dummy word line drive signal A0 Address signal INV3601 to INV4203 Negative circuit NAND3601 -NAND4202 NAND gate NOR3601 to NOR4102 NOR gate EXNOR4101 Exclusive OR gate circuit SAP, SAN, N1701 to N4203 Node name QL, QL21 to QL47 Main memory cell "L" data read charge amount QH, QH21 To QH47 main memory cell “H” data read charge amount QD dummy memory cell data read charge amount RSTDT dummy memory cell capacitor reset voltage C PC cell plate electrode control signal DCPC dummy cell plate electrode control signal QS, QS21 to QS47 Difference between “L” data read charge amount and “H” data read charge amount of main body memory cell P3801 to P4304 period

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area H01L 27/108 21/8242

Claims (23)

[Claims] 1. A pair of bit lines, a first ferroelectric capacitor connected to one bit line of the pair of bit lines so as to form a body memory cell, and a dummy memory cell. A second ferroelectric capacitor connected to the other bit line of the pair of bit lines so as to constitute the second ferroelectric capacitor, wherein the second ferroelectric capacitor is the first ferroelectric capacitor. A ferroelectric memory device, wherein a predetermined capacitance value is set in accordance with a capacitance characteristic when repeatedly operated. 2. The ferroelectric memory device according to claim 1, wherein the voltage applied to the second ferroelectric capacitor is positive or negative in only one direction. Memory device. 3. The ferroelectric memory device according to claim 1, wherein the voltage applied to the second ferroelectric capacitor is in both positive and negative directions. 4. A pair of bit lines, a first ferroelectric capacitor connected to one of the pair of bit lines so as to form a body memory cell, and a dummy memory cell. A second ferroelectric capacitor connected to the other bit line of the pair of bit lines, the voltage applied to the first ferroelectric capacitor and the second ferroelectric substance. A ferroelectric memory device characterized in that a voltage applied to a capacitor is different. 5. The ferroelectric memory device according to claim 4, wherein the voltage applied to the second ferroelectric capacitor is more than the voltage applied to the first ferroelectric capacitor when reading data. A ferroelectric memory device characterized by being set low. 6. The ferroelectric memory device according to claim 4, wherein the voltage applied to the second ferroelectric capacitor is a voltage applied to the first ferroelectric capacitor when data is rewritten. A ferroelectric memory device characterized by being set lower than the above. 7. The ferroelectric memory device according to claim 4, wherein the voltage applied to the second ferroelectric capacitor is greater than the voltage applied to the first ferroelectric capacitor when reading data. A ferroelectric memory device characterized by being set high. 8. A ferroelectric capacitor connected to a bit line so as to form a memory cell, wherein the voltage applied to the ferroelectric capacitor when reading data and the ferroelectric capacitor when rewriting data. A ferroelectric memory device characterized by being different from a voltage applied to the ferroelectric memory device. 9. The ferroelectric memory device according to claim 8, wherein a voltage applied to the ferroelectric capacitor when reading data is higher than a voltage applied to the ferroelectric capacitor when rewriting data. A ferroelectric memory device characterized by being set. 10. The ferroelectric memory device according to claim 8, wherein a voltage applied to the ferroelectric capacitor when rewriting data is higher than a voltage applied to the ferroelectric capacitor when reading data. A ferroelectric memory device characterized by being set. 11. The ferroelectric memory device according to claim 10, wherein the voltage applied to the amplifier connected to the bit line and the ferroelectric capacitor when rewriting data is the ferroelectric memory when reading data. A ferroelectric memory device, further comprising: means for boosting a power supply voltage of the amplifier so as to be higher than a voltage applied to the body capacitor. 12. The ferroelectric memory device according to claim 10, wherein a voltage applied to the ferroelectric capacitor when rewriting data is higher than a voltage applied to the ferroelectric capacitor when reading data. A ferroelectric memory device further comprising means for boosting the potential of the bit line. 13. A ferroelectric capacitor connected to a bit line so as to form a memory cell, the voltage applied to the ferroelectric capacitor when reading data, and the ferroelectric capacitor when rewriting data. A ferroelectric memory device characterized in that the voltage applied to each of them is set higher than the power supply voltage. 14. A transistor having a gate electrode connected to one word line, first and second plate electrodes, and the first plate electrode so as to form a memory cell together with the transistor. Is a ferroelectric capacitor connected to a bit line through the transistor and the second plate electrode is connected to a cell plate line; and the word line is selected with a logic voltage "H" or "L". A ferroelectric memory device comprising: a means for bringing a word line into a floating state. 15. The ferroelectric memory device according to claim 14, further comprising means for applying a voltage between the cell plate line and the bit line after setting the word line in a floating state. Ferroelectric memory device characterized by. 16. A pair of bit lines, a first transistor having a gate electrode connected to a word line, first and second plate electrodes, and a main body memory cell together with the first transistor. As configured, the first plate electrode is connected to one bit line of the pair of bit lines via the first transistor and the second plate electrode is connected to a cell plate line. A first ferroelectric capacitor, a second transistor having a gate electrode connected to the dummy word line, first and second plate electrodes, and a dummy memory cell with the second transistor. Thus, the first plate electrode is connected to the other bit line of the pair of bit lines through the second transistor and the second plate electrode is connected to the other bit line of the pair of bit lines. The electrode is a second ferroelectric capacitor connected to a dummy cell plate line, and the data is rewritten to the main body memory cell when a voltage is applied between the cell plate line and the one bit line. A ferroelectric memory device comprising means for deselecting a word line. 17. The ferroelectric memory device according to claim 16, wherein at the time of rewriting the data of the main body memory cell, the timing of deselecting the word line and the timing of transitioning the logic voltage of the cell plate line. 2. A ferroelectric memory device further comprising means for changing the order of the above according to the logic voltage of the data read onto the one bit line. 18. A pair of bit lines, a first transistor having a gate electrode connected to a word line, first and second plate electrodes, and a main body memory cell together with the first transistor. As configured, the first plate electrode is connected to one bit line of the pair of bit lines via the first transistor and the second plate electrode is connected to a cell plate line. A first ferroelectric capacitor, a second transistor having a gate electrode connected to the dummy word line, first and second plate electrodes, and a dummy memory cell with the second transistor. Thus, the first plate electrode is connected to the other bit line of the pair of bit lines through the second transistor and the second plate electrode is connected to the other bit line of the pair of bit lines. The electrode is a second ferroelectric capacitor connected to the dummy cell plate line, and the data is written in the dummy memory cell again, and a voltage is not applied between the dummy cell plate line and the other bit line. And a means for making a dummy word line non-selected, a ferroelectric memory device. 19. The ferroelectric memory device according to claim 18, wherein at the time of rewriting the data of the dummy memory cell, the timing of deselecting the dummy word line and the logic voltage of the dummy cell plate line are changed. A ferroelectric memory device further comprising means for changing the order of timing according to the logic voltage of the data read onto the other bit line. 20. A pair of bit lines, a first transistor having a gate electrode connected to a word line, first and second plate electrodes, and a complementary memory cell together with the first transistor. The first plate electrode is connected to one bit line of the pair of bit lines through the first transistor and the second plate electrode so as to form one of the memory cells. Has a first ferroelectric capacitor connected to a first cell plate line, a second transistor having a gate electrode connected to the word line, and first and second plate electrodes, The first plate electrode is connected to the pair of bits via the second transistor so as to form another memory cell of the complementary memory cells together with a second transistor. Other of which is connected to the bit line and the second plate electrode ferroelectric memory device characterized by comprising a second ferroelectric capacitor connected to the second cell plate line of the. 21. The ferroelectric memory device according to claim 20, wherein a voltage is applied between the first cell plate line and the one bit line when rewriting data of the complementary memory cell. And deselecting the word line, and further comprising means for deselecting the word line in a state where a voltage is applied between the second cell plate line and the other bit line. A characteristic ferroelectric memory device. 22. A pair of bit lines, a first transistor having a gate electrode connected to the first word line, first and second plate electrodes, and complementary with the first transistor. The first plate electrode is connected to one bit line of the pair of bit lines via the first transistor and is configured to form one of the memory cells. Has a first ferroelectric capacitor connected to the cell plate line, a second transistor having a gate electrode connected to the second word line, and first and second plate electrodes. , The first plate electrode via the second transistor so as to form the other memory cell of the complementary memory cells together with the second transistor. The other is connected to the bit line and the second plate electrode is a ferroelectric memory device characterized by comprising a second ferroelectric capacitor connected to the cell plate line of the line. 23. The ferroelectric memory device according to claim 22, wherein a voltage is applied between the cell plate line and the one bit line when rewriting data of the complementary memory cell. Means for deselecting one word line and deselecting the second word line with a voltage applied between the cell plate line and the other bit line; A characteristic ferroelectric memory device.