JPH04367120A - Programmable logic device using ferrodielectric memory - Google Patents

Abstract

PURPOSE:To obtain the programmable logic device capable of writing in configuration with normal operating voltage. CONSTITUTION:Both ends of a SRAM 10 are connected to a line PL through a ferrodielectric condenser 16. The ends of the SRAM 10 are connected by a switch 18. After the SRAM is set to the prescribed state, data is written in the ferrodielectric condenser 16 by turning on a switch 14. At the time of rising, the switch 18 is turned on while turning off the switch 14 so as to make the ends of the SRAM 10 the same electric potential. The switch 14 is turned on in this state, and the difference of the electric potential based on the ferrodielectric polarization in the ferrodielectric condenser 16 is exerted on the ends of the SRAM 10, and the SRAM 10 is set according to the data written in the ferrodielectric condenser 16. Thus, no high voltage is required for a nonvolatile memory.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device (hereinafter referred to as PLD) that uses a ferroelectric memory as a configuration memory.

0002

2. Description of the Related Art Conventionally, programmable logic devices in which operations such as the contents of logical operations can be set have been widely used. In this programmable logic device, it is necessary to write data for operation settings after manufacturing the device, and it is also necessary to rewrite the stored contents for testing the operation contents. For this reason, as a configuration memory for setting operation contents, EPROM (erasable ROM) whose stored data can be erased by irradiation with ultraviolet rays and EEPROM (electrically erasable ROM) whose stored data can be electrically erased are used.
M) etc. are used, and this makes it possible to rewrite in nonvolatile memory.

0003

The EPROM stores data by passing a large current as a write current between the drain and source, accumulating charges in the floating gate. Therefore, when writing data, at a high voltage corresponding to the write current to the EPROM, for example, a 5V system, at the time of writing, 12 to 1
Approximately 5V is applied. Therefore, it is necessary to increase the withstand voltage of each memory cell of the EPROM, resulting in the problem that the memory cell becomes larger and the degree of integration cannot be increased. Further, in EEPROM, the write voltage is higher than that in EPROM. For this reason, it is difficult to ensure a withstand voltage including the peripheral circuits that electrically connect to the memory, making it impossible to achieve high integration of the circuits, resulting in the problem that the program logic device becomes larger. Furthermore, since the writing speed of conventional EPROMs is very slow, there is a problem in that the test time becomes long when data is rewritten many times during testing.

An object of the present invention is to provide a programmable logic device that can store and rewrite data in a configuration memory at normal operating voltages.

[0005]

[Means for Solving the Problems] A programmable logic device according to the present invention is a programmable logic device that operates according to the storage state of a configuration memory, the configuration memory comprising:
A volatile memory circuit that stabilizes by outputting opposite polarity to both ends according to an input signal, and a volatile memory circuit that is connected to this volatile memory circuit and generated due to dielectric polarization of a ferroelectric material at both ends of the volatile memory circuit. A ferroelectric capacitor whose dielectric layer is made of a ferroelectric material and supplies a potential difference between the two.

[0006]

[Operation] In a ferroelectric memory, dielectric polarization is generated in the ferroelectric by applying a voltage. Therefore, when the power is turned on, the polarity of the volatile memory is set according to the state of dielectric polarization of the two ferroelectric memories, thereby operating as a nonvolatile memory. In addition, because large voltages are not required to generate dielectric polarization in ferroelectric memory, the withstand voltage of the entire memory cell can be set low, which eases the manufacturing conditions of programmable logic devices and increases the degree of integration. can do.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a PLD, which includes a wiring block 1 and a plurality of unit cells 2. As shown in FIG.

The wiring block 1 has a crossbar switch corresponding to each unit cell 2 in order to achieve a desired connection between the input/output terminals provided on the integrated circuit and each unit cell 2. The on/off status of this switch is set using non-volatile configuration memory. That is, as shown in FIG. 2, a pass transistor Tr for turning on and off signal transmission is provided as a crossbar switch, and the on/off state of this pass transistor Tr is set by the configuration memory NVM. Therefore, the on/off state of the pass transistor Tr is set according to the data in the configuration memory NVM, and a desired signal is transmitted. Also, unit cell 2
Each has a logic circuit, and this logic is set by the configuration memory NVM. For example, as shown in FIG. 3, the input signal of the logic gate NAND is determined by the configuration memory NVM, and the logic operation is set to a desired one.

The configuration memory NVM in this embodiment preferably has a configuration as shown in FIG. That is, two inverters 10a
, 10b, data input/output switches 12a and 12b which connect both ends of this SRAM 10 to a bit line and an inverted bit line and are turned on and off by the word line, read/write switches 14a and 14b connected to both ends of the SRAM 10, and these leads. It consists of ferroelectric capacitors 16a, 16b connecting the light switches 14a, 14b and the control line PL, and a switch 18 connected to both ends of the SRAM 10 and turned on and off by the control line EQ.

The ferroelectric capacitor 16 is a capacitor in which a ferroelectric material is used as a dielectric layer, and PZT (lead zirconate titanate) or the like is used as the ferroelectric material. Ferroelectric materials exhibit dielectric polarization even when no electric field is applied. For this reason,
When a voltage is applied to the ferroelectric capacitor 16 to cause dielectric polarization, the polarization continues even after the voltage application is stopped. Therefore, data can be stored using this ferroelectric capacitor 16.

The data storage mechanism will be explained based on FIG. 5. When a voltage of -VDD to +VDD is applied to the capacitor 16 by a variable power supply as shown in FIG. 5(A), the charge due to polarization in the capacitor 16 has hysteresis as shown in FIG. 5(B). , when looking only at one side, when VDD is applied, the polarization of charge δq remains, and when -VDD is applied, the polarization of charge -δq remains. Therefore, data can be stored using this polarized state. Next, a data set based on the charge δq caused by this dielectric polarization will be explained based on FIGS. 6 and 7. Here, FIG. 3 shows the case where data "1" is written, and FIG. 4 shows the case where data "0" is written. If the capacitance in the ferroelectric capacitor 16 is Cs, then this Cs
is considered to consist of an amount C that changes depending on the applied voltage, and an amount δC that corresponds to the polarization that remains even after the applied voltage is removed. It consists of a charge q accumulated in response to application and a charge δq corresponding to the above-mentioned polarization. Therefore, when the applied voltage is V, q+δq=(C+δC)V (where, Cs=C+δ
Let it be C. ).

Therefore, as shown in FIG. 6A, when voltage V is applied to the capacitor 16, charges q+δq are accumulated on the positive electrode side, and charges -q−δq are accumulated on the negative electrode side. . Furthermore, as shown in FIG. 6(B), when the power is turned off and the application of voltage V is removed, the capacitor 16
Although the above-mentioned charges are accumulated and the potential difference is V, polarization of ±δq remains in the ferroelectric layer 116. Therefore, the dielectric polarization of this ferroelectric material is used to store data. That is, as shown in FIG. 6(C), capacitor 1
6, the polarization in the ferroelectric layer 116 will remain, and the ferroelectric layer 1 of the capacitor 16 will remain polarized.
16, a state has been written in which the upper side in the figure is -δq and the lower side is δq.

When connected to the bit line bit as shown in FIG. 6(D), this bit line bit becomes
It is expressed as a capacitor consisting of a capacitance of Cbit. Therefore, when the lower electrode of the capacitor 16 in the diagram is raised by the voltage V, charges corresponding to the capacitances of the two capacitors are accumulated, and the potential of the bit line BIT becomes a value corresponding to the charge qb+ accumulated here.

On the other hand, when the direction of voltage application to the capacitor 16 is reversed, charge accumulation and polarization similar to those described above occur as shown in FIGS. is the opposite. Therefore, as shown in FIG. 7(D), when the voltage V is raised, a charge corresponding to the charge qb- is taken out to the bit line BIT. Here, the voltage difference between the bit line bits in the case of FIG. 6(D) and FIG. 7(D) is the difference when the charge δq due to dielectric separation of the ferroelectric material is increased and decreased. , ΔV
= (qb+ -qb-)/Cbit =2δq/(C
s + Cbit).

[0015] Therefore, this potential difference ΔV is set to "0", "1"
”, the written data can be read out.

Here, the above-mentioned potential difference ΔV is calculated as follows.

First, since charge is conserved, qb-
qs=±δq... (1) Also, the voltage drop across the two capacitors is qb/Cbit + qs
/Cs=V (2).

Therefore, from equations (1) and (2), qb=C
bit (CsV±δq)/(Cs+Cbit). Since +δq corresponds to the case in FIG. 6 and -δq corresponds to the case in FIG. 7, ΔV can be expressed as described above.

Therefore, if this ΔV is used to determine the state of the SRAM 10 at startup, data can be stored using the dielectric polarization of the ferroelectric capacitor 16. Therefore, in normal times, by reading the contents of the SRAM 10, it is possible to write or read data "0" or "1" on the bit line.

Next, the initial operation of the nonvolatile memory shown in FIG. 1 when the power is turned on will be explained based on FIGS. 8 and 9. First, as described above, predetermined data is written in each capacitor 16 (the ferroelectric material is polarized). Then, when the power is turned on, SRAM1
0 is SRAM1 depending on the state (undefined) conditions at that time.
Both ends of 0 are stable at either 0.5V or 5.0V (A). Next, turn on the switch 18 and
Make the potentials at both ends of AM10 the same (B). At this time, S
If the characteristics of the inverters 10a and 10b constituting the RAM 10 are the same, both ends of the SRAM 10 should be stable at 2.5V, and the SRAM 10 is configured in this way.

In this state, the plate voltage is set to 2.5
At the same time, the read/write line RW is set to H, and the switch 14 is turned on to connect both ends of the SRAM 10 and the capacitor 14, respectively. Therefore, capacitor 1
Both ends of 6 are 2.5V. Therefore, capacitor 1
The polarization state of the ferroelectric material in 6 is not destroyed (C). Then, the switch 18 is turned off and the plate voltage is changed to -2.5V (D). As a result, a difference in the voltages written in the capacitor 16 appears at the upper electrode of the capacitor 16. That is, with respect to -2.5V, a voltage Δv corresponding to 2δq is applied as a potential difference between both ends of the SRAM 10. Therefore, the SRAM 10 operates according to the difference in Δv between both ends, and the left side with the high voltage is 5
V, the right side stabilizes at 0V (E). In this way, S
In the RAM 10, a state can be set according to the state of the capacitor 16, so it functions as a nonvolatile memory.

However, in (E) above, voltages of 7.5V and 2.5V are applied across the capacitor 16. For this reason, the polarization state of the capacitor 16, especially the capacitor 16 whose upper side was negatively polarized,
The memory contents of b are destroyed. Therefore, it is necessary to restore the contents stored in the capacitor 16. Therefore, the plate voltage is set to 5V (F). This allows capacitor 16
b is restored to a state where the upper side is -. When the restoration of the storage state is completed in this way, the read/write signal is set to L to disconnect the capacitor 16 that operates as a nonvolatile memory (G). This causes the SRA to enter a predetermined storage state.
M10 can be set. Therefore, it functions as a nonvolatile memory.

As described above, in the memory of this embodiment, a voltage of -2.5V to 5V is applied to the capacitor 16, but only 0 to 5V is used for the SRAM 10 and other circuits. Therefore, write at the normal operating potential (5V system). It can be rewritten, and there is no need to consider special breakdown voltages for the memory and its peripheral circuits. Therefore, the transistors constituting the circuit can be of the same type as those of normal logic, and the overall area can be reduced and the degree of integration can be increased.

Next, FIG. 10A shows the configuration of a system using this configuration memory. This example has four (2×2) nonvolatile memories NVM, each of which is connected to a decoder 20 and a read/write unit 22. That is, the decoder 20 has an address bus and a control line connected to its input side, and a word line, EQ line, RW line, and plate line PL to its output side. Further, the read/write section 22 has a data bus connected to its input side, and a bit line b and an inverted bit line rb connected to its output side. In addition, Figure 10
(B) shows a symbol of the nonvolatile memory NVM of this embodiment, and each nonvolatile memory NVM in FIG. 9 has the configuration shown in FIG. 4.

When writing data to this nonvolatile memory NVM, as shown in FIG.
With RW set to H and plate PL set to L, the address to be written is placed on the address bus. by this,
The corresponding word line W becomes H, and the bit line b and the inverted bit line rb are connected to both ends of the corresponding SRAM 10. Therefore, bit line data is set in the SRAM. At this time, since RW is H, the ferroelectric capacitor 16 is also connected to the SRAM.
Dielectric polarization occurs depending on the 10 states. Here, since the potential on both sides of the ferroelectric capacitor 16 on the data 0 side is the same, no dielectric polarization occurs here. Therefore, with RW set to H, the plate is set to H (5V), and dielectric separation opposite to that in the above case is created. In this way, data can be written to the ferroelectric capacitor 16. Note that in this example, there are 2
Since there are two nonvolatile memories NVM, data on the corresponding bit lines is written to the two NVMs.

Furthermore, at power-on, the state of the SRAM 10 is set depending on the state of dielectric isolation of the ferroelectric capacitor 16. Therefore, as shown in FIG. 12, both the word line and bit line are in the L state, and each control line is operated to perform initialization as shown in FIGS. 9 and 10 described above.

[0027] After performing such initialization, R
Since W is kept at L, the corresponding word line becomes H according to the address specification, and this data is outputted to the data bus via the data supply section.

Furthermore, the nonvolatile configuration memory can also have a configuration as shown in FIG. In the figure, a switch 30 and a ferroelectric capacitor 32 are arranged between the bit line b and the plate line P, and an output Q is output from the connection thereof via an inverter 34. A word line w is connected to the gate of the switch 30, and the on/off state of the switch 30 can be controlled by the word line.

In such a circuit, the word line,
If the bit line and plate line are controlled in the same manner as in the case of FIG. 8, dielectric polarization similar to that in the above case can be generated in the ferroelectric capacitor 16. and,
During normal operation, the plate voltage is set to a predetermined value, and set to a potential at which the output from the inverter 34 is inverted by the above-mentioned ΔV. Therefore, an output corresponding to the state of dielectric polarization in the ferroelectric capacitor 16 can be obtained as the output of the inverter 34.

FIG. 11 is a block diagram showing a PLD configuration memory data set system using the configuration memory shown in FIG. This refresh control unit 34 sets the state of each configuration memory. This set is similar to the case of FIG. 10 described above.

[0031]

[Effects of the Invention] As explained above, the PL according to the present invention
According to D, since the dielectric polarization in a ferroelectric capacitor can be used for nonvolatile data storage, high voltage is not required for writing, etc., and the withstand voltage of the memory can be reduced.
The memory can be made smaller and the degree of integration can be increased.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a PLD.

FIG. 2 is a configuration diagram of a configuration memory that controls pass transistors.

FIG. 3 is a configuration diagram of a configuration memory that controls a logic circuit.

FIG. 4 is a circuit diagram showing the configuration of an embodiment of a nonvolatile memory according to the present invention.

FIG. 5 is an explanatory diagram showing dielectric polarization of the ferroelectric capacitor of the example.

FIG. 6 is an explanatory diagram showing the operation of the ferroelectric capacitor of the example.

FIG. 7 is an explanatory diagram showing the operation of the ferroelectric capacitor of the example.

FIG. 8 is an explanatory diagram showing the operation of the embodiment.

FIG. 9 is an explanatory diagram showing the operation of the embodiment.

FIG. 10 is a configuration diagram of a memory cell using the nonvolatile memory of the example.

FIG. 11 is a chart showing a write operation of the same memory cell.

FIG. 12 is a chart showing the initialization operation of the memory cell.

FIG. 13 is another configuration diagram of a nonvolatile memory.

FIG. 14 is a configuration diagram of a system using the memory of FIG. 13.

[Explanation of symbols]

10 SRAM 12, 14, 18 switch 16 Ferroelectric capacitor

Claims (1)

[Claims] 1. A programmable logic device that operates according to the storage state of a configuration memory, wherein the configuration memory is a volatile memory circuit that stabilizes by outputting opposite polarities to both ends thereof according to an input signal. , a ferroelectric capacitor connected to the volatile memory circuit and having a dielectric layer made of a ferroelectric material and supplying a potential difference generated due to dielectric polarization of the ferroelectric material to both ends of the volatile memory circuit; A programmable logic device using ferroelectric memory, characterized in that: