JP3102161B2 - Data signal demultiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal demultiplexing apparatus, and more particularly to a data signal demultiplexing apparatus for demultiplexing a large capacity network signal and a plurality of small capacity terminal signals.

[0002]

2. Description of the Related Art Conventionally, a data signal demultiplexing apparatus of this kind has the structure shown in FIG. FIG. 3 is a block diagram of a conventional example. The downstream data signal d, frame signal e, and clock signal f created by the master-side device 21
Via the slave side device 22 through the downlink data signal d
-1, slave side frame signal e-1, clock signal f
-1 and the uplink data signal c-1 is generated by the terminal interfaces 4-1-1 to 4-n in the slave device 22, and the uplink data signal c-1 is transmitted via the bus 28 to the master device 21. Is connected to the master-side expansion device 29-1. Since the master-side expansion devices 29 are connected one-to-one to the slave-side devices 22, there are as many as the slave-side devices 22. The figure shows a case in which there are two slave devices 22, and the description will be made mainly on behalf of the slave device 22-1.

The remote control device 7 remotely controls the master control device 5 and each slave control device 6 by a remote control signal c. The master-side control device 5 and each slave-side control device 6 transmit / receive each terminal-side control signal g corresponding to the remote control to / from each terminal-side interface 4. Each terminal-side interface 4 receives the terminal-side control signal g
The connection of the corresponding terminal device and the setting of the channel are performed, and the terminal data signal b including the uplink data signal c and the downlink data signal d is transmitted and received.

FIG. 4 is a time chart of data signals between the master device 21 and the slave device 22. The time chart shows that the frame signal e and the clock signal f output from the network interface 3 are transmitted via the bus 28 and the frame signal e-1 generated by the slave extension device 30 of the slave device 22. Due to the timing of the clock signal f-1, the upstream data signal c-1 output from the terminal side interface 4 becomes the upstream data signal c-3 output from the FIFO 31-1 at the same timing as the upstream data signal c in the master side device 21. , Are multiplexed as the uplink data signal c. The FIFO buffer 31 writes the slave-side upstream data signal c at the timing of the slave-side frame signal e and the slave-side clock signal f generated by each slave-side device 29, and writes the frame signal e and the clock signal f of the master-side device 21. At this timing, the upstream data signal c of the bus signal is output to adjust the timing. In the terminal-side interfaces 4-1 and 4-2, the slave-side uplink data signals c-1 and c-2 are arranged and output at the positions of channel 1 and channel 2, respectively.

The three-state 32 serves to multiplex connect the upstream data signal c output from the FIFO 31 to the data signal c. In this three-state 32, when the upstream data signal c output from the FIFO 31 is at the logical value "L" state, the upstream data signal c is also set to the "L" state. In this state, wired multiplex connection is performed on the data signal c side.

[0006]

As described above, the conventional data signal demultiplexing apparatus requires the master side expansion apparatus 9 in the master side apparatus 1 by the number of slave side apparatuses 2 as described above.
When many slave devices 2 are required, there is a problem that the master expansion device 9 increases and the master device 1 becomes large. Further, there is a problem that wiring to the master-side expansion device 9 is concentrated on the master-side device 1.

[0007]

A data signal demultiplexing apparatus according to the present invention extracts a clock signal, a frame signal, and a downstream data signal from a downstream data signal on the network side and outputs the same, and simultaneously outputs the input upstream data signal on the network side. A corresponding master provided externally with a downlink data signal of a corresponding channel from among the downlink data signals according to the network side interface for transmitting as an uplink data signal and the master side control signal corresponding to the clock signal and the frame signal. A plurality of master-side terminal interfaces for simultaneously transmitting an uplink data signal from the master-side terminal device to the network-side interface at a timing of a corresponding channel; Master control unit that inputs and outputs external control signals and external control signals A buffer amplifier that sends the clock signal, the frame signal, and the downlink data signal to a signal transmission bus provided externally, and an extension unit bus that extends the clock signal, the frame signal, and the bus. A master-side FIFO buffer for multiplexing an upstream data signal obtained from the extension unit bus with the obtained clock signal and the frame signal into an upstream data signal output from the master-side terminal interface and transmitting the multiplexed upstream data signal to the network-side interface; A master-side device including a master-side three-state buffer, and a corresponding one of the downlink data signals obtained from the bus by the slave-side control signal corresponding to the clock signal and the frame signal obtained through the bus. The downlink data signal of the corresponding channel is A plurality of slave-side terminal interfaces that output an uplink data signal from the slave-side terminal device at the timing of the corresponding channel simultaneously with transmission to the slave-side terminal device, and control of the external control signal output by the master-side control device. A slave-side control device for inputting and outputting each of the slave-side control signals; and the slave signal based on the clock signal and the frame signal obtained from the bus, and the clock signal and the frame signal obtained from the extension unit bus. Slave FIF for adjusting the timing of the upstream data signal output from the side terminal interface and outputting the same to the extension section bus
It comprises a plurality of slave devices including an O buffer and a slave three-state buffer.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of this embodiment. FIG.
The major difference from the conventional data signal multiplexing / demultiplexing apparatus shown in FIG. 1 is that the master-side expansion apparatus 9 is shared and one is used, and a FIFO buffer 11 and a three-state 12 are added to the slave-side expansion apparatus 10. This figure shows a case where two slave devices are provided. The operation of the present embodiment will be described below. FIG. 2 shows a time chart of a data signal between the master device 1 and the slave device 2 in FIG. This time chart shows that the frame signal e and the clock signal f output from the network side interface 3 are transmitted via the bus 8 and the slave side expansion device 10 of each of the slave side devices 2-1 and 2-2.
-1, 10-2, the frame signals e-1, e
The slave-side uplink data signals c-1 and c-2 output from the terminal-side interface 4 are generated based on the timing of the clock signals f-1 and f-2. The uplink data signals c-1-1 and c-2-1 are synchronized with the timings of the frame signals e-1-1 and e-2-1 and the clock signals f-1-1 and f-2-1 of the extension bus 12. Is output to the extension bus 12. This slave-side uplink data signal c-1-1,
From c-2-1 to the upstream data signal c-1-1 of the bus signal,
The timing for c-2-1 is adjusted by the FIFO buffers 11-1 and 11-2 and the three-state buffer 12- in the slave side expansion devices 10-1 and 10-2.
1, 12-2. The data signal transmitted between the bus 8 and the extension bus 12 is delayed. For example, the frame signal c is delayed by the bus 8 and the slave side frame signal c
-1 and the frame signals e-1-1 and e-3 extracted from the extension bus 12 are further delayed.
There is also a delay difference between the slave side frame signals c-1 and c-2. The upstream data signals c-1-1 and c-2-1 output to the extension unit bus 12 are input to the FIFO buffer 11 of the master device 1 as one multiplexed upstream data signal c-3. The upstream data signal c-3 is the
The role of multiplexing the O buffer 11 and the upstream data signal c of the bus signal is adjusted by the slave side expansion device three-state buffer 12, multiplexed with the upstream data signal c on the master side, and input to the network side interface 3. And sent to the network side.

[0010]

As described above, according to the present invention, by providing a FIFO buffer and a three-state in a slave device, the number of master expansion devices in the slave device can be reduced to one regardless of the number of slave devices. And the bus wiring does not concentrate on the master device.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a time chart of a data signal in FIG. 1;

FIG. 3 is a block diagram of a conventional data signal demultiplexing apparatus.

FIG. 4 is a time chart of a data signal in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Master side device 2 Slave side device 3 Network side interface 4 Terminal side interface 5 Master side control device 6 Slave side control device 7 Remote control device 8 Termination device 9 Master side expansion device 10 Slave side expansion device 11 FIFO buffer 12 Three state a network Data signal b Terminal data signal c Up data signal d Down data signal e Frame signal f Clock signal g Terminal control signal h Master-slave control signal i Remote control signal

Claims (1)

(57) [Claims] A network interface for extracting and outputting a clock signal, a frame signal, and a downlink data signal from a network-side downlink data signal, and simultaneously transmitting an input uplink data signal as a network-side uplink data signal; And transmitting the downlink data signal of the corresponding channel from the downlink data signal to the corresponding master side terminal device provided externally by the master side control signal corresponding to the frame signal, and simultaneously transmitting the downlink data signal from the master side terminal device. A plurality of master-side terminal interfaces for transmitting an uplink data signal to the network-side interface at a timing of a corresponding channel; and a master side for inputting / outputting each of the master-side control signals and the external control signal under the control of an external remote controller. A control device, the clock signal, the frame signal, and the downlink data A buffer amplifier for sending a signal to a bus for signal transmission provided externally, and the clock signal and the frame signal, and the clock signal and the frame signal obtained from the extension bus extending the bus. A master side including a master side FIFO buffer and a master side three-state buffer for multiplexing a bus side upstream data signal obtained from the extension section bus into an upstream data signal output from the master side terminal interface and transmitting the same to the network side interface A device, and a downlink data signal of a corresponding channel out of the downlink data signals obtained from the bus is provided externally by the clock signal obtained through the bus, the frame signal, and a slave control signal corresponding to the frame signal. At the same time as sending to the corresponding slave side terminal device A plurality of slave-side terminal interfaces that output uplink data signals from the side-side terminal device at the timing of the corresponding channel; and input / output each slave-side control signal under the control of the external control signal that is output from the master-side control device. An uplink data signal output from the slave-side terminal interface according to the slave-side control device, the clock signal and the frame signal obtained from the bus, and the clock signal and the frame signal obtained from the extension bus. A data signal demultiplexing apparatus comprising: a plurality of slave devices including a slave FIFO buffer and a slave three-state buffer that output the data to the extension unit bus at a predetermined timing.