JPH03296340A - Interface circuit - Google Patents

Abstract

PURPOSE:To correctly receive a data without being affected by data transfer delay between equipments by grasping a delay time between equipments and adjusting a read timing by the delay time with respect to a synchronization clock. CONSTITUTION:A clock generating circuit 6 is started as a synchronizing signal before transfer of a data and transfers the synchronization clock to a 2nd equipment 2. Then a signal processing section 4a transfers a prescribed data to a serial parallel conversion circuit 5a, from which the data is transferred to the 2nd equipment 2. The transmission delay time of a data between the 1st equipment 1 and the 2nd equipment 2 is set before the reception of the data, a prescribed data is sent, a transfer timing of the data is adjusted by a transmission delay time so that the data is correctly received, a signal processing section 4b uses an advance transmission timing circuit 10 so as to adjust a transmission delay time to to obtain an optimum data transfer timing thereby adjusting the data transmission timing to be led by the time to from the timing of the synchronization clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an interface circuit for synchronous serial data communication, and in particular to an interface circuit for serial data provided in an interface between aircraft-mounted AVIEX.

[Prior Art] FIG. 5 shows the configuration of a conventional interface circuit.

In the figure, (1) is a first device t that can decide whether to send or receive data, and (2) is a first device M that receives data transmitted from (1) and responds with data based on the request. a second device having the capability (3a) to (3b);
) are cables including a grounding wire and a signal wire connecting the first device (1) and the second device (2), (4a) (4b
) is a signal processing section of a synchronous interface circuit that determines data transmission/reception in the first device (1) and the second device; a serial/parallel conversion circuit (6) that converts the data requested by each of the signal processing units (4a) and (4b) of the device (2) from parallel data to serial data, or from external serial data to parallel data; (7) is a synchronization circuit that generates read timing based on the synchronization signal; (8a) to (8d) are the first device (1) and the second device ( This is an isolation transformer for insulating 2) from ground.

Next, the operation will be explained using the timing chart of FIG. 6 showing the data transmission/reception processing operation.
) starts the clock generation circuit (6) as a synchronization signal before transferring data, and sends the synchronization clock (a) shown in FIG. 4 to the second device through the isolation transformer (8b). Transferred to (2). Next, the signal processing section (4
The predetermined data (a) shown in FIG. 4 in a) is transferred to the serial/parallel converter circuit (5a) and transferred as serial data to the second device (2) through the isolation transformer (8a). The transferred data (a) is received by the serial/parallel converter circuit (5c) through the isolation transformer (8c), converted into parallel data, and processed by the signal processor (4b).

Next, if the processed data is a data request required by the first device R (1), the second signal processing unit (4b) transfers the requested data to the serial/parallel conversion circuit (5d). The transferred data is converted into serial data (x) shown in FIG. 4 by the serial/parallel conversion circuit (5d) and sent to the first device (1) through the isolation transformer (8c). First device (1)
The serial data (1) transferred to the isolating transformer (8a
), the waveform (1) delayed by t due to the transmission delay between the first device (1) and the second device (2) as shown in
) is read and converted into parallel data by the serial/parallel converter circuit (5b) according to the timing (o), and the signal processing unit (4a)
is loaded into.

[Problem to be Solved by the Invention] Since the conventional synchronous interface circuit is configured as one or more, if the transmission delay t between the first device and the second device is delayed beyond the reading timing. , there were issues such as the inability to read the data.

This invention is intended to solve the above-mentioned problem. When the transmission time between devices is delayed by more than a predetermined reading timing, the device detects the delay time and delays the reading timing by the delay time. The present invention provides an interface circuit for synchronous serial data transfer that can transfer data synchronously without being affected by transmission time delays between the two.

Another invention of the present invention is to solve the above-mentioned problem, and when the transmission time between devices is delayed by more than a predetermined reading timing, the delay time is set and the data transmission timing is changed to the delay time. The present invention provides an interface circuit in synchronous serial data transfer that can transfer data synchronously without being affected by delays in transmission time between devices by advancing the data by a minute.

[Means for Solving the Problems] The interface circuit according to the present invention includes a timing delay circuit that can grasp the transmission delay time between devices before receiving predetermined data and adjust the reading timing using that value. It is equipped with

An interface circuit according to another invention of this invention is
This device is equipped with a forward timing circuit that can set the transmission delay time between devices before receiving predetermined data, and adjust the data transmission timing using that value.

[Operation J] In order to receive predetermined data correctly, the interface circuit of the present invention requests the predetermined data by the signal processing unit, and when the received data cannot be received correctly, measures the delay time with respect to the synchronization clock, and By understanding the transmission delay time between the devices, the reading timing is delayed by that delay time and the data is received correctly.

The interface circuit in another invention of this invention is
In order to receive the specified data correctly, the signal processing unit requests the specified data, and if the received data cannot be received correctly, the delay time with the synchronization clock is measured and the transmission delay time between each device is set. Depending on the situation, the data transmission timing is advanced by the delay time and the data is received correctly.

[Example code] An embodiment of the present invention will be described below.

In FIG. 1, (1) to (8) are the same as the above-mentioned conventional technology, and (9) is a read timing that measures the transmission delay time between devices and is delayed from the synchronous clock by that value. It is a timing delay circuit that creates

Next, a description will be given with reference to FIG. 2, which shows processing timing waveforms of the synchronous interface circuit according to the present invention.

In such a configuration, when transmitting and receiving predetermined data, the signal processing unit (4a) of the first device (1) activates the clock generation circuit (6) as a synchronization signal before transferring the data, and The synchronous clock (A) shown in the figure is transferred to the second device (2) through the isolation transformer (8b). Next, from the signal processing unit (4a), the predetermined data (a) shown in FIG.
) will be forwarded to. The transferred data (a) is received by the serial/parallel converter circuit (5c) through the isolation transformer (8c), converted into parallel data, and processed by the signal processor (4b).

However, before receiving the data of the first device
) and the second device (2), send and receive predetermined data, adjust the read timing and transmission delay time so that the data is received correctly, and set the optimal adjusted transmission delay time. decide. Determined transmission delay time t. The signal processing unit (4a) adjusts the signal using the timing delay circuit (9), and the reading timing is adjusted in advance to be read 10 minutes later than the synchronization clock as shown in the waveform (force) in FIG.

Next, the serial data (1) transferred to the first device (1)
is t due to the transmission delay between the first device (1) and the second device (2) through the isolation transformer (8a) as shown in FIG. The resulting waveform (1) is read and converted into parallel data by a serial/parallel conversion circuit (5b) depending on timing (force), and read into a signal processing section (4a).

Next, other embodiments of the invention will be described.

In Fig. 3, (1) to (8) are the same as the conventional one, and (10) sets the transmission delay time between devices and advances the data timing by the delay time from the synchronization clock by that value. This is a postponed timing circuit.

The operation will be described with reference to FIG. 4, which shows processing timing waveforms of the synchronous interface circuit in this invention.

In such a configuration, when transmitting/receiving predetermined data, the signal processing ffl<(4a) of the first device (1) generates a clock generation circuit (6) as a synchronization signal before transferring the data.
), and the synchronous clock (a) shown in FIG. 4 is transferred to the second device (2) through the isolation transformer (8b). Next, from the signal processing unit (4a), the predetermined data (a) shown in FIG. will be forwarded to. The transferred data (a) is received by the serial/parallel converter circuit (5c) through the isolation transformer (8c), converted into parallel data, and processed by the signal processor (4b).

However, before receiving the data of the first device
) and the second device (2), transmit the predetermined data, adjust the data transfer timing by the transmission delay time so that the data is received correctly,
Transmission delay time t to achieve optimal data transfer timing
0, the signal processing unit (4b) postpones the timing circuit (10
) to adjust the data transmission timing to (1) in Figure 4.
As shown in the waveform below, it is adjusted in advance to transmit data 16 minutes ahead of the synchronized clock.

Next, the serial data (1) transferred to the first device 1f (1) is transferred to the first device 1f (1) through an isolation transformer (8a) as shown in FIG. The waveform (1), which is delayed by 10 minutes due to the transmission delay between (1) and the second device (2), is read and converted into parallel data by the serial/parallel conversion circuit (5b) according to the timing (o), and the signal processing unit ( 4a).

Although a synchronous interface circuit has been described in the above embodiment, the same effects as in the above embodiment can be obtained even in an asynchronous interface circuit.

[Effects of the Invention] As described above, the interface circuit according to the present invention grasps the delay time between devices and adjusts the read timing by the delay time with respect to the synchronization clock, thereby transmitting data between the devices. This has the effect of allowing data to be received correctly without being affected by transfer delays.

Further, in the interface circuit according to another aspect of the present invention, a delay time between devices is set, and the data transfer timing is adjusted by the delay time with respect to the synchronization clock, thereby reducing the data transfer delay between the devices. This has the effect of allowing data to be received correctly without being affected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an interface circuit according to an embodiment of the present invention, FIG. 2 is a data reading timing chart in the interface circuit of the invention, and FIG. 3 is a diagram showing another embodiment of the invention. 4 is a timing chart for reading data in the interface circuit of FIG. 3, FIG. 5 is a block diagram of a conventional interface circuit, and FIG. 6 is a timing chart for reading data in the conventional interface circuit. In the figure, (1) is the first device! , (2) is the second device (3a)-(3b) is the cable, (4a)-(4
(b) is a signal processing unit (5a) to (5d) is a serial/parallel conversion circuit, (6) is a clock generation circuit, (a) is a synchronization circuit, (
8a) to (8d), the isolation transformer (9) is a timing delay circuit, and (10) is a forward timing circuit. Note that the same reference numerals in the two figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) An interface circuit for synchronous serial data communication between first and second devices connected to each other by a cable including a grounding wire and a signal line, which is provided in the first device and connected to the second device. a serial-to-parallel conversion circuit that transmits and receives serial data to and from the device; and a serial-to-parallel conversion circuit that is provided in the second device and that transmits and receives the serial data from the first device via the signal line in synchronization with the synchronization clock. a parallel conversion circuit; a clock generation circuit provided in the first device and generating a synchronous clock so as to transmit and receive data synchronously with the second device; The device is characterized in that it is equipped with a synchronization circuit that generates read timing from a synchronization clock, and a timing delay circuit that measures data transmission delay time in the first device and delays the read timing by the delay time. interface circuit. (2) An interface circuit for synchronous serial data communication between first and second devices connected to each other by a cable including a grounding wire and a signal line, which is provided in the first device and connected to the second device. a serial-to-parallel conversion circuit that transmits and receives serial data to and from the device; and a serial-to-parallel conversion circuit that is provided in the second device and that transmits and receives the serial data from the first device via the signal line in synchronization with the synchronization clock. a parallel conversion circuit; a clock generation circuit provided in the first device and generating a synchronous clock so as to transmit and receive data synchronously with the second device; It is characterized by comprising a synchronization circuit that generates read timing from a synchronization clock, and a postponement timing circuit that sets a data transmission delay time in the second device and postpones the data transmission timing by the delay time. interface circuit.