JP3102113B2 - Electronic camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic camera, and more particularly, to an electronic camera for improving image quality at the time of encoding / decoding.

[0002]

2. Description of the Related Art In recent years, electronic still cameras for recording photographed images on floppy disks have been put to practical use. Digital electronic still cameras that record images on a memory card or the like using a semiconductor memory have also been developed. However, at present, about 50 images can be recorded on one floppy disk, and only about 10 to 20 images can be recorded with a memory card of 1 megabyte. Moreover, memory cards are extremely expensive. Therefore, improvement in image compression technology is essential for electronic still cameras, and DCT (Discrete Cos
ine Transform: discrete cosine transform).

[0003]

However, in such a conventional electronic camera, image compression is performed by using a DCT device in the image compression / decompression unit. And square block-like noise (block distortion) in low density areas such as background
And the image quality is degraded. As shown in FIG. 49 in which the noise portion of FIG. 48 is enlarged,
This noise occurs at the boundary of 8 × 8 pixels, which is the processing unit of the DCT device, and this block distortion is generated by DCT at the time of companding.
This is because a calculation error generated in the T / inverse DCT calculation causes discontinuity at a block boundary. Therefore, the present invention
It is an object of the present invention to provide an electronic camera capable of greatly improving image quality with a simple circuit configuration.

[0004]

In order to achieve the above object, according to the first aspect of the present invention, a basic function is directly converted from captured image data.
Encoding processing in block units by orthogonal transformation as an intersection function
In an electronic camera that performs
During the encoding process, blocks adjacent in the horizontal direction
First computing means for performing a compensation operation for a fundamental function,
Perform base function compensation on blocks adjacent to
A second calculating means. The first calculating means and the
The two calculation means may be, for example, an image
A base function that superimposes data between adjacent blocks of image data
The image data is superimposed orthogonally using a number (LOT) and
Perform inverse polymerization orthogonal transformation (ILOT).

[0005]

According to the first and second aspects of the present invention, at the time of encoding processing,
In addition, the first arithmetic means converts the blocks adjacent in the horizontal direction to
A compensation operation of the fundamental function is performed on the
Primitive compensation for vertically adjacent blocks
An operation is performed. Therefore, for adjacent blocks
The distortion is properly removed.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 19 show an embodiment of an electronic camera according to the present invention, which is an example applied to a digital still camera.

First, the configuration will be described. FIG. 1 is a block diagram showing an electronic camera. In FIG. 1, reference numeral 511 denotes an electronic camera, and 521 denotes a lens system.
Is movable along its optical axis by a focus motor 522. The CCD 523 is arranged on the optical axis of the lens system 521, and a photographed image of a subject is formed on the imaging surface of the CCD 523 via the lens system 521. Here, the CCD 523 is connected to the timing generator 6.
CCD driver 6 whose operation timing is measured by 31
32 controls the imaging operation.

An image signal picked up by the CCD 523 is output to a process circuit 524. Process circuit 5
In 24, the input image signal is separated and extracted into a luminance signal YH and a chrominance signal C.

[0009] The luminance signal YH and the chrominance signal C from the process circuit 524 are output to an A / D converter 525, where they are digitized. Then, the digitized luminance signal Y
H is applied to one input terminal of adders 526 and 527, respectively. Adder 526 outputs the added output to field memory 529 via switch 528, and the output of field memory 529 is provided to the other input terminal of adder 526. The adder 527 outputs the added output to the field memory 5 via the switch 530.
31 and the output of the field memory 531 is provided to the other input terminal of the adder 527. in this case,
As data of the luminance signal YH for each line, A, B,
Given field data C, D, E, F,..., Field memory 529 stores field data of A + B, C + D, E + F,..., And field memory 531 stores field data B + C, D + E, + F + G,. Is stored.

Here, in the case of video through (when an image from a CCD is viewed with a view finder), the output of the field memory 531 is taken out via a switch 523 and after being gamma-corrected by a gamma correction unit 533, The outline is emphasized by the enhancer 534 and output through the switch 535. On the other hand, at the same time, the A / D converter 52
The chrominance signal C digitized in 5 is supplied to a switch 536 and a synchronizing unit 5 for adjusting the timing with the luminance signal YH.
37 to the color difference generation unit 538,
-Y color difference signal, and switches 539 and 54
0 are stored in the field memories 541 and 542, respectively. These field memories 541,
The RY and BY color difference signals extracted from the 542 are supplied to the color view finder ROM table 543 together with the luminance signal YH output through the switch 535. Thereby, the ROM is controlled by the driver 544.
The corresponding display data is output from the table 543 and displayed on the color view finder 545 as a video through image. This ROM table 543 is for generating RGB signals from the luminance signal YH and the color difference signals RY and BY.

In the case of still image pickup, the output of the field memory 529 is supplied to a 1H memory 546, and the output of the 1H memory 546 is supplied to one input terminal of an adder 547. The adder 547 receives the output from the field memory 529 at the other input terminal, and outputs the addition result. Then, the output of the adder 547 is taken out via the switch 532, and is output to the gamma correction unit 533.
, And the outline is enhanced by the enhancer section 534, and is returned to the field memory 529 again. Also,
At the same time, the color signal C digitized by the A / D converter 525 is supplied to the field memory 548 and to one input terminal of the adder 549. The adder 549 has the other input terminal connected to the field memory 54.
8 and outputs the result of addition. The output of the adder 549 is the switch 536,
It is provided to the color difference generation unit 538 via the synchronization unit 537,
Are generated as RY and BY color difference signals,
Field memories 541 and 542 through 39 and 540
Respectively. Then, the luminance signal YH of the field memory 529 and the field memory 541,
The color difference signals RY and BY 542 are input to the image compression / expansion circuit 600 as a frame still image, and the image data is compressed by the image compression / expansion circuit 600 so that the external memory 55
0 is stored.

The image compression / expansion circuit 600 is a circuit including a DCT device and a LOT operation device for executing a LOT (Lapped Orthogonal Transform) operation for reducing block distortion when image data is compressed, The use of the image compression / expansion circuit 600 makes it possible to compress / expand image data with high efficiency while reducing block distortion. The details of the image compression / expansion circuit 600 will be described later.

In the case of image reproduction, the external memory 55
0, the luminance signal YH is read out, and the image compression / decompression circuit 6
After the image data is decompressed at 00, the data is written to the field memory 531 via the switch 530, and the color difference signal R-
Similarly, Y and BY are decompressed by the image compression / decompression circuit 600 and then written into the field memories 541 and 542 via the switches 539 and 540. The output of the field memory 531 is supplied to switches 532 and 535.
And supplied to the ROM table 551 together with the outputs from the field memories 541 and 542.
Accordingly, the corresponding display data is output from the ROM table 551 under the control of the encoder / timing generator 552, converted into an analog signal by the D / A converter 553, and output as a video reproduction signal via the amplifier / buffer 554. Become like

On the other hand, a contrast detection unit 555 is connected to the process circuit 524 described above. The contrast detection unit 555 is provided with a luminance signal YH output from the process circuit 524, and detects an imaging contrast from the luminance signal YH. Then, such a contrast signal of the contrast detection unit 555 is
It is provided to the main controller 556.

The main controller 556 controls the focus drive circuit 557 according to the output from the contrast detector 555.

A focus drive circuit 557 is provided with a focus motor 522 under the control of the main controller 556.
And the lens system 521 is moved from the ∞ end to the closest end to adjust the focus position with respect to the CCD 523.

FIG. 2 is a diagram showing a screen configuration of the electronic camera. In FIG. 2, the luminance signal YH is 768 dots wide and 4 dots long.
80 lines, and each of the color difference signals RY and BY
It has 92 dots and 240 vertical lines. If one pixel is compressed to 1.5 bits, 24 images can be recorded on a 2 MB memory card as the external memory 550.

By the way, as described above, not only the DCT apparatus but also high-efficiency coding to reduce the average number of bits per pixel lowers the image quality, and raises the compression ratio to deteriorate the image quality. Problems that occur when the current standard television signal is compressed to 1.5 Mbit / s are deterioration of the contour part and block units (for example, 8 ×) which are processed by the DCT device.
(8 pixels). When a pixel is reproduced by performing an inverse transformation, all the DCT outputs in the block are linearly summed. However, if any one of 64 DCT outputs of a block including 8 × 8 pixels has information loss, Degradation occurs in the reproduced pixels in the entire block.

Therefore, in this embodiment, in order to reduce such block distortion, an image compression / decompression circuit 600 using a LOT operation together with a DCT device is provided as described in detail below. The image compression / decompression device 600 includes a DCT unit,
It comprises a LOT section and a working memory. Hereinafter, FIGS.
9, the LOT calculation processing will be described. FIG.
In the image compression / expansion circuit 600, a LOT operation device 100 that performs LOT operation processing is shown.
FIG. 3 shows a block diagram of the OT. In FIG. 3, 100
Denotes a LOT operation device, 101 and 102 denote DCT devices, and various operation units shown in FIGS. 4 to 7 are connected to the DCT devices 101 and 102. Here, FIG.
5 shows an operation indicating addition c = a + b, FIG. 6 shows an operation for adjusting a predetermined gain (for example, 1/2), and FIG. 7 shows an operation for performing vector rotation. Each is shown. The outputs of the DCT devices 101 and 102 are separately added and subtracted into even outputs 0, 2, 4, and 6 and odd outputs 1, 3, 5, and 7, and finally only odd components are output. Vector rotation is performed by the butterfly operation unit shown in FIG. 7 to become LOT data. In the one-dimensional LOT configuration shown in FIG. 3, if 16 pixels (X _{0 to} X ₇ , X ₀ ′ to X ₇ ′) are input to the DCT devices 101 and 102 which constitute the image compression / decompression circuit 600 together with the LOT operation device, the LO becomes low.
The output of the 8 data by T operation (Y ₀ ~Y ₇₎ is obtained. That is, at the input first stage, one-dimensional DCT operation is performed to obtain 16 data, and after performing various operations on the 16 data, vector rotation is performed to finally obtain 8 data. Since this LOT operation is one-dimensional, the output is 8 × 16 for a 16 × 16 input pixel, and the same LOT operation is performed again by exchanging the length and width to obtain 8 × 8 data.

Although two DCT devices are shown in FIG. 3, there is only one DCT device in hardware.
The data X,
X ′ (X _{0 to} X ₇ , X ₀ ′ to X ₇ ′) are supplied.

FIG. 8 is a diagram showing input / output pixels of the LOT arithmetic unit 100. The LOT operation device is an extension of the conventional DCT device, and performs two-dimensional block processing similarly to the DCT device. In the DCT device, if the input is 8 × 8 pixels, 8 × 8 data is obtained. On the other hand, in the LOT operation device, in order to obtain the 8 × 8 output, as shown by the broken line in FIG. 16 × 16 pixels including 8 × 8 are required. The broken line in FIG. 8 is the LOT input pixel, and the solid line is the output data.

Hereinafter, the LOT operation device of the image compression / decompression circuit 600 will be described in detail. FIG. 9 is a block diagram illustrating a calculation unit of the LOT calculation device. In FIG.
The T operation device 21 is capable of performing (closed) operation (Hadamard transform) using only data of one certain block Y ₁
A stage 22 and a Y ₂ stage 23 that can perform an operation (Hadamard transform) only when the data of the two blocks are complete
When, the Y ₁ is inserted between odd stage 22 and Y ₂ stage 23, data (reverse L of odd components from temporarily Y ₁ stage until the operation of the next block line is completed
OT at the time of one block line memory 24 for storing data) in the odd component from Y ₂ stage, a Z stage 25 for performing the vector rotation, a switch 26-33 for switching the flow of data by a switch switching circuit 40 It is configured.

The switch switching circuit 40 includes a switch 2
6 to 33 are switched to switch the data flow between LOT and ILOT. The switches 26 to 33 are for switching the data flow by, for example, switching the bus, and the configuration is not particularly limited as long as the connection relation of the bus can be switched physically or electrically. For example, a transistor switch or the like can be used.

[0024] In the following, Y ₁ stage 22, Y ₂ stage 23
The Z stage 25 will be specifically described with reference to FIGS. The Z stage 25 is used to rotate the odd component of the input data as shown in FIG. 10 for the operation at the time of LOT and as shown in FIG. 11 for the operation at the time of reverse LOT.
The butterfly operation is shown in FIG. K in FIG.
Is a coefficient for giving a vector rotation, for example, 0.13
It is set to 0.16. The Z stage 25 is the same as the conventional Z stage, but the number is only one. Further, the Y ₁ stage 22 and Y ₂ stage 23
Is obtained by dividing the Y stage shown in FIG. 10 into two stages as shown in FIG. 16 and FIG. 17, and closes in one block during LOT (using only data of one block). (Hadamard transform) can be calculated unit Y ₁ stage 22 (first processing unit), LOT
Sometimes Y ₁ stage 2 for different blocks of data
2 by the operation result is aligned is the first operation (Hadamard transform) can be calculated units Y ₂ stage 23 (second processing unit). The Y ₁ stage operation results in one block line in the memory 24 is block is a memory for temporarily storing until calculation of Y ₁ stage in the next block ends. 12 to 15.
Shows various butterfly operations in each stage, and shows the same operation contents as the butterfly operations in FIGS. 4 to 7.

Next, the operation of this embodiment will be described. Operation of Digital Still Camera 511 First, when a still image is captured, the output of the field memory 529 is output to the 1H memory 546.
The output of 46 is output to one input terminal of the adder 547. The adder 547 adds the output of the field memory 529 to the input output of the 1H memory 546 and outputs the result of the addition. Then, the output of the adder 547 is taken out via the switch 532, and
The gamma correction is performed in 33, the outline is enhanced in the enhancer 534, and the image is returned to the field memory 529 again. At the same time, the color signal C digitized by the A / D converter 525 is supplied to the field memory 548 and to one input terminal of the adder 549.
The adder 549 receives the output from the field memory 548 at the other input terminal, and outputs the result of addition. The output of the adder 549 is
6. The data is supplied to the color difference generation unit 538 via the synchronization unit 537, is generated as RY, BY color difference signals, and is supplied to the field memories 541, 5 via the switches 539, 540.
42 respectively. The luminance signal YH of the field memory 529 and the field memory 54
The 1,542 color difference signals RY and BY are input to the image compression / expansion circuit 600 as frame still images. The image data (the luminance signal YH and the color difference signals RY and BY) input to the image compression / expansion circuit 600 is transmitted to the DCT device 1.
001, 1002 and the LOT operation device 1000 are subjected to overlapping orthogonal transformation by the image compression / decompression circuit 600 to reduce block distortion, and are compressed and stored in the external memory 550.

On the other hand, when reproducing images, the external memory 550
The luminance signal YH of the image data stored in the image data is expanded by the image
After the block distortion is reduced by the inverse superposition orthogonal transform by the T arithmetic unit, the data is written to the field memory 531 via the switch 530. Similarly, the color difference signals RY and BY stored in the external memory 550 are also subjected to image data expansion by the image compression / expansion circuit 600 and are subjected to inverse polymerization orthogonal transformation by the LOT arithmetic unit to reduce block distortion. , Are written into the field memories 541 and 542 via the switches 539 and 540. Then, the output of the field memory 531 is taken out via the switches 532 and 535, and supplied to the ROM table 551 together with the outputs from the field memories 541 and 542. Accordingly, the corresponding display data is output from the ROM table 551 under the control of the encoder / timing generator 552, converted into an analog signal by the D / A converter 553, and output as a video reproduction signal via the amplifier / buffer 554. Become like

The operation of the LOT arithmetic unit is as follows. Operation at LOT Calculation (See FIG . 18) FIG. 18 is a diagram showing the flow of data at the time of LOT. First, F ₀ to F ₇ of the DCT operation output as shown in FIG. 10,
Is Hadamard converted by Y ₁ stage 22, G ₀ ~G
It becomes ₇ . Among them, the even sides G ₀ , G ₂ , G ₄ , G ₆ (hereinafter, referred to as Ge) are directly input to the Y ₂ stage 23. Also, the odd sides G ₁ , G ₃ , G ₅ , and G ₇ (hereinafter, referred to as Go) must add and subtract with the even when the next block is operated, so that the operation times in the Y ₂ stage 23 are aligned. For this purpose, it is temporarily stored in the one block line memory 24. Subsequently, the block data F ₀ ′ to F ₇ ′ based on the DCT operation output at the next timing
But is Hadamard converted by Y ₁ stage 22,
G ₀ ′ to G ₇ ′. Ge, like the Go Ge 'is input directly to Y _2-stage 23, Go' is stored in 1 block line memory 24. The Ge 'Y ₂ Stage 2
If you enter a 3 Go which was stored in 1 block line memory 24 at the same time inputted to Y ₂ stage 23, Y ₂ stage 23 performs a Hadamard transform on the Go and Ge '.
That is, the operation between data of different blocks is LOT
Sometimes, it performed in Y ₂ stage 23. Then, the outputs H _{0 to} H ₇ of the Y ₂ stage 23 are input to the Z stage 25, and the Z stage 25 obtains Y _{0 to} Y ₇ which are the results of the LOT operation (see FIG. 10). Meanwhile, Y ₂ on the stage 23 by the amount of memory access is applied when Y ₁ stage 22 output is input is considered as the execution time becomes slow,
Actually, since the LOT operation is a repetition of the above operation, the total time hardly changes from the conventional one.

Operation during reverse LOT operation (see FIG . 19) FIG. 19 is a diagram showing the flow of data during reverse LOT. Input data Y ₀ '~Y _7' is converted to J ₀ '~J _7' by Z stage 25, Y ₂ stage 23 further
Convert J ₀ ′ to J ₇ ′ to K ₀ ′ to K ₇ ′. Z stage 2
Only the odd side data is rotated at 5 and the even side data is output as it is. In the Z stage 25 at the time of ILOT, the odd-numbered data input and output are changed from 1 → 7,3
If the twist is performed in the order of → 5, 5 → 3, 7 → 1, the data at the time of ILOT can be processed by the same hardware as the hardware at the time of LOT. Then, perform the odd side of the data rotated by the Z stage 25, computation by Y _2-stage 23 with respect to the even side of the data supplied as the (Hadamard transform). Here, no operation is performed on the data on the even side in the Z stage, but the data on the even side is also input to the Z stage 25 in FIG. 19 for convenience. Then, the as same as the output of the Y ₁ stage 22 at the time of LOT, Ke 'is directly input to the Y ₁ stage 22, Ko' is 1 block line memory 24
Store in. Similarly, the subsequent input data is transferred to Z stage 2
5. Converted to K _{0 to} K ₇ by the Y ₂ stage 23 and Ke
Inputs directly Y ₁ stage 22, Ko gonna stored in 1 block line memory 24. Memory 24 with Ke
Inputting the Ko 'data that has been stored in the Y ₁ stage 22. And by executing the calculation of Y ₁ stage 22 to obtain the ILOT output F ₀ to F _7. That is, I
LOT Sometimes, operations between different blocks so that the charge of the Y ₁ stage 22.

As described above, in the present embodiment, image data compression and the like are executed using the image compression / decompression circuit 600 including the LOT arithmetic unit, so that data between adjacent blocks is, for example, 16 × 6. As a result, 8 × 8 data is obtained from the pixels and the images are appropriately superimposed, so that a high-quality electronic camera 511 with less block distortion can be constructed. Further, LOT calculation device of this embodiment, the Y stage of the LOT calculation Y ₁ stage 22 and Y ₂
With divided into the stage 23, 1 block line memory 24 for storing data until the operation of the next block line between Y ₁ stage 22 and Y ₂ stage 23 is completed
Because be provided with a processing in the Y ₁ stage 22, Y ₂ stage 23 is completed at 8 input units. In addition, since operations between blocks are performed by different stages at the time of LOT and at the time of ILOT, the number of Z stages 25 can be reduced to one. Therefore, the circuit size of the Z stage can be reduced by half compared to the related art. Further, since the one block line memory 24 also needs to store only the data on the even side, the memory capacity can be reduced.

In this embodiment, an example in which the present invention is applied to an electronic camera has been described. However, the present invention can be applied to a video camera and the like.

Further, in this embodiment, the image signal converted into the electric signal is separated into the luminance symbol Y, the color difference symbols RY and BY and stored in the frame memory. Any method may be used as long as the image signal is stored in a predetermined form. For example, the image signal may be stored in the form of an RGB signal, or the image signal converted into an electric signal may be stored as it is.

(Second Embodiment) The image data processing apparatus shown in FIGS. 9 to 19 performs one-dimensional (horizontal)
After performing a LOT operation (LOT is basically one-dimensional), one-dimensional (vertical) LOT operation is performed again on the obtained data to obtain two-dimensional image data. Therefore, before the data output from the two-dimensional DCT operation unit is quantized by the quantization operation unit, the one-dimensional processing must be repeated twice by the LOT operation unit. Therefore, the operation of the two-dimensional DCT operation unit must be rested until the one-dimensional LOT operation completes the processing of the second dimension, so that not only the operation time cannot be reduced but also the timing is difficult. . Therefore, the second embodiment provides an image compression / decompression circuit that can significantly reduce the image processing time.

This embodiment will be described below with reference to the drawings. Rationale First, the basic concept of the present embodiment. In the present embodiment, a first operation processing unit X capable of performing an operation (Hadamard transform) by closing (using data of one block) a LOT operation device of an image compression / expansion circuit, and a plurality of blocks A second operation processing unit Y that performs an operation using the data of FIG.
It is intended to realize high-speed data processing by dividing the data into two-dimensional calculations in the respective processing units. Therefore, as shown in FIG.
The operation unit, the Y operation unit, and the Z operation unit are divided into three parts, and two-dimensional operation is performed in each part. FIG. 21 is a diagram showing the operation contents (for one dimension) of the rotation processing in the Z operation unit, and FIGS. 22 and 23 show the details (for one dimension) of the X operation unit and the Y operation unit in FIG. It is a block diagram.

Next, a specific configuration and operation of the image compression / decompression circuit according to the present embodiment will be described with reference to FIGS. FIG. 24 is a block diagram showing the LOT operation device of the image data processing device. In FIG. 24, LOT operation device 121 includes two-dimensional X operation unit 122 that performs two-dimensional Hadamard transform, two-dimensional Y operation unit 123 that performs two-dimensional Hadamard transform, and two-dimensional X operation unit 122 Inserted between the Y operation unit 123 and the two-dimensional X operation unit 12
One-block line memories A124, B125, and C1 for controlling data exchange between the two-dimensional and two-dimensional Y operation units 123 and delaying data by one block line.
26 and a two-dimensional Z operation unit 1 for performing vector rotation
27. The two-dimensional X operation unit 12
2 performs addition and subtraction on the data of one image block at the time of LOT, so that the output of the DCT can be directly processed. Also, in the reverse direction, to perform an operation on the data of the two block lines, the data of the block line memory is read and the data operation is performed.
The two-dimensional Y operation unit 123 performs an operation on data of two block lines in the forward direction and outputs data to the two-dimensional Z operation unit 127, and outputs the data from the two-dimensional Z operation unit 127 in the reverse direction. Is directly processed to write data into the block line memories A124, B125, and C126.
The two-dimensional Z operation unit 127 processes the data from the two-dimensional Y operation unit 123 in the forward direction, and processes the quantized data from the quantization device in the backward direction.

FIG. 22 is a block diagram of the two-dimensional X operation unit 122. The two-dimensional Y operation unit 123 has the same circuit configuration. In FIG. 22, two-dimensional X operation unit 122 includes data latches A131 and B13 for temporarily holding data.
2, C133, D134 and data latches A131, B
132, C133, and D134, adders / subtractors 135 and 136 for adding / subtracting the data latched by D134;
An adder 137 for adding the output of the adder 136;
Subtractor 138 for subtracting the output of 5,136, and adder 1
37, and a data selector 139 for selecting and outputting data from the subtractor 138. The data selector 139 has a function of selecting and outputting input data, and further reduces input data by １ ／.
It has a multiplying operation function.

There are 64 DCT outputs for an 8 × 8 pixel block. Therefore, in the X operation unit 122, 16 sets of the configuration of FIG.
The corresponding four of the outputs of the CT are input. Similarly,
Also in Y operation section 123, 16 sets of the configuration in FIG. 22 are arranged. In the X and Y calculation units 122 and 123, a predetermined number of circuits shown in FIG. 22 may be arranged and input data may be subjected to time division processing.

FIG. 27 is a configuration diagram of the two-dimensional Z calculation section 127. The two-dimensional Z operation unit 127 is for rotating the odd component of the input data, and the butterfly operation is shown in FIG. Θ in FIG. 21 is a coefficient for giving a vector rotation, and is set to, for example, 0.13, 0.16. The two-dimensional Z operation unit 127 is, specifically,
As shown in FIG. 24, two one-dimensional Z operation units 141 and 14
2 and two block line memories A143 and B144
And each of the Z operation units 141 and 14
2 is responsible for vertical and horizontal Z operations. The two block line memories A143 and B144 are provided to hold data necessary for performing a second-dimensional operation. The block line memory A 143 and the block line memory B 144 switch and store the output of the Z operation unit 141 for each block. Z is assigned to the block line memory A 143 or the block line memory B 144.
While storing the output data of the operation unit 141, the Z operation unit 142 performs the second-dimensional Z operation on the data stored in the buffer 144B or 143A. Here, in the Z operation, the odd component 1,
3, 5, 7 are switched to 1⇔7, 3⇔5.

Next, the operation of this embodiment will be described. Operations of the forward and reverse of each block of the entire LOT computing device is shown in FIGS. 28 and 29. For example, in the case of the forward direction, as shown in FIG. 28, the two-dimensional X operation unit 122 outputs the input from the DCT device to the block line memories A124, B125, and C12.
Write to 6 in order. The two-dimensional Y operation unit 123 reads data from the two block line memories, performs two-dimensional processing, and outputs the result to the two-dimensional Z operation unit 127. When a memory that can be read and written at once is used, the above operation is not necessarily required.

Operation of two-dimensional X operation part and two-dimensional Y operation part
(See FIG. 25) First, the forward direction will be described. Data latch A131 has a
(I, j) data is latched, and data latch B1
32, a (i, j + 1), and the data latch C133 have a
(I + 1, j), and a (i + 1, j) is stored in the data latch D134.
j + 1) are latched, and the adder / subtractor 135, 1
36 operate as adders, a (i, j) + a (i, j +
1), + a (i + 1, j) + a (i + 1, j + 1) are output from the adder 137 and the subtractor 138, respectively.
(I, j) + a (i, j + 1) + a (i + 1, j) + a
(I + 1, j + 1) and a (i, j) + a (i, j + 1)
-A (i + 1, j) -a (i + 1, j + 1) is output. The output of the adder 137 is the converted b (i, j) component, and the data of the subtractor 138 is the b (i + 1, j) component. Next, when the adders / subtractors 135 and 136 are operated as subtractors, the outputs from the adder 137 and the subtractor 138 are b (i +, j + 1) and b (i + 1, j + 1). Note that i and j are even numbers.

More specifically, for example, the data a00, a01, a10, and a11 (i = 0, j = 0) of a certain block are stored in the X operation unit 1
The data is converted into a00 ', a01', a10 ', and a11' according to the following equation. a00 '= (a00 + a01 + a10 + a11) / 2 a01' = (a00 + a01-a10-a11) / 2 a10 '= (a00-a01 + a10-a11) / 2 a11' = (a00-a01-a10 + a11) / 2 All i and j in one block
By performing the processing for (both even numbers), for example, the four blocks A to D shown in FIG.
Converted to D '.

As shown in FIG. 28, X operation unit 122
Are stored in block line memories 124 to 126 in block line units. Then, when the X operation unit 122 is operating for the next block line, Y
The operation unit 123 reads a block H 'obtained from the four blocks A' to D 'from the block line memories 124 to 126. Block H 'can be expressed as follows. a11 ', a13', a15 ', a17', b10 ', b12', b14 ', b16' a31 ', a33', a35 ', a37', b30 ', b32', b34 ', b36' a51 ', a55 ', A55', a57 ', b50', b52 ', b54', b56 'a71', a77 ', a75', a77 ', b70', b72 ', b74', b76 'H' = c11 ', c13' , c15 ', c17', d10 ', d12', d14 ', d16' c31 ', c33', c35 ', c37', d30 ', d32', d34 ', d36' c51 ', c53', c55 ', c57 ', d50', d52 ', d54', d56 'c71', c73 ', c75', c77 ', d70', d72 ', d74', d76 '

The Y operation unit 123 reads the read block H '.
, A two-dimensional Hadamard transform is performed. The specific conversion operation is the same as the operation of the X operation unit 122 described above. The output of the Y stage is supplied to the Z operation unit 127.
In this way, for four adjacent blocks, X
The processing by the arithmetic unit 122, the Y arithmetic unit 123, and the Z arithmetic unit 127 is sequentially executed.

On the other hand, in the reverse direction, the above a (i, j) is changed to (i
−1, j + 1), the above a (i, j + 1) is replaced by a (i−
1, (j + 8) is replaced with the above a (i + 1, j) by a (i, j +
1), the above a (i + 1, j + 1) is converted into a (i, j + 8)
Change to each. Here, the adder 137 and the subtractor 13
8 has a range twice as large as the inputs of the data latches A131 to D134.
In 39, it is necessary to perform a half-adjustment calculation by multiplying by 1/2. That is, the two-dimensional X operation unit 22 and the two-dimensional X
Since the two-dimensional operation is performed in each operation unit of the operation unit 123, the operation result is output from each operation unit in the form of an integer. Further, the two-dimensional X operation unit 122 and the two-dimensional Y operation unit 123 can be configured by the same circuit. Therefore, it is sufficient to debug only one of the operation units, and the debugging can be performed very efficiently.

As described above, in the second embodiment, DC
The two-dimensional X that can be operated by closing the LOT operation device that constitutes the image compression / decompression circuit together with the T device in one block
The arithmetic unit 122 and two units that can be operated by a plurality of blocks
Dimension Y operation unit 123 and two-dimensional Z that performs vector rotation
It is divided into three by the operation unit 127, and each of the operation processing units
Since the two-dimensional operation is performed, the data output from the two-dimensional DCT device can be directly subjected to the two-dimensional LOT operation and output to the quantization device. It is possible to prevent data stagnation such as having to rest until the eye processing is completed, thereby significantly improving arithmetic processing. Also, D
Since the CT device, the LOT operation device, and the quantization device can be operated at the same time, timing adjustment is very easy, and a high-speed image compression device can be realized. It goes without saying that the above-mentioned effect is also generated in the reverse direction, that is, in data expansion, and when applied to an image data processing apparatus for compressing / expanding image data, the image processing time can be greatly reduced.

(Third Embodiment) In the above-described LOT arithmetic unit, encoded data can be processed at a high speed with a relatively small circuit as described above.
Since the configuration is such that the T operation is performed, the number of accesses to the memory increases, and the control of the address and the bus becomes complicated, resulting in a problem that the circuit scale is still large. Therefore, the electronic camera according to the third embodiment provides an image compression / decompression circuit that performs LOT processing and LOT processing with a smaller circuit scale by executing a LOT operation and an inverse LOT operation by a serial operation for sequentially moving data at a predetermined clock. .

Hereinafter, this embodiment will be described with reference to the drawings. FIGS. 30 to 47 are diagrams showing the specific configuration and operation of the image compression / decompression circuit according to this embodiment. First, the configuration will be described. FIG. 30 is a configuration diagram showing a data operation unit of the LOT operation device of the image compression / decompression circuit. In FIG. 30, 2
Reference numeral 31 denotes a Y stage for performing a predetermined addition / subtraction process, and 232 denotes a Z stage for performing vector rotation. The Z stage 232 performs the LOT operation in FIG.
The operation at the time of (LOT) is for rotating the odd component of the input data as shown in FIG. 31, and the butterfly operation is shown in FIG. 15 described above. K in FIG. 15 is a coefficient for giving a vector rotation, for example, 0.13, 0.1
6 is set.

FIGS. 32 to 44 are block diagrams showing the data conversion unit and the quantization unit of the image compression / decompression circuit according to the present embodiment. In FIG. 32, 241 is a LOT operation device 240
And 242 are data quantization units, and are quantization units thereof, and are cos0.13π and sin0.13π, cos0.16π and sin which are operation coefficients (numerical values circled in the figure) of the data conversion unit 241.
The ratio of 0.16π is approximated by an integer ratio as shown in Equation 1.

(Equation 1)

It should be noted that the ratio of the integers does not necessarily need to be such a ratio, and a ratio having a larger number of digits may be used and replaced with a more accurate ratio. In addition, in the calculation based on the integer ratio, the gain differs from the calculation that should be performed, so that the difference in the gain is absorbed by the quantization calculation. For example, the value z formed by x ₁ and x ₂ is 7 ² +3 ² = 58, so actually sin, co
The value shown in Expression 2 is obtained by multiplying (58) ^1/2 times as compared with the calculation using s.

(Equation 2) Note that the correction value is created by approximation as shown in Expression 2, and does not necessarily need to be this value.

In the case of the present embodiment, since the output of such an operation is an input of the operation of the next stage, the operation for adjusting the gain is performed once at z ₁ , z ₂ and z ₃ in FIG. . Note that in this case, the gain adjustment means that the gains of the input data are the same, and does not mean that the gains of the output data are the same. The gain ratio between the inputs is given by Equations 3 and 4.

(Equation 3)

(Equation 4)

In FIG. 32, z ₁ : z ₂ : z ₃ = 5: 38: 392 is set as an example satisfying the above equations ₃ and 4.
Note that this is only an example, and does not necessarily need to be set to such a numerical value.

The change in each output gain caused by expressing the gain as an integer ratio is calculated by the quantization unit 242.
Absorb in That is, the operation coefficient of the data conversion unit 241 is replaced by an integer ratio, and the gain changed by this is corrected by the quantization unit 242.

FIG. 33 is a diagram showing an inverse data transformation unit and a quantization unit in the inverse transformation of the data compression apparatus, and shows an example in which the inverse transformation of FIG. 32 is performed. In FIG. 33, 25
1 is an inverse quantization unit of the LOT arithmetic unit 240, and 252 is an inverse data conversion unit. In the case of the inverse transform as well, as in the case of FIG. 32, the operation coefficient of the inverse data transform unit 252 is replaced with an integer ratio as indicated by a numerical value circled in FIG. 25, and the resulting change in gain is inversely quantized. Adjustment is made so that the part 251 absorbs (compensates).

In this embodiment, the LOT and inverse LOT operations are performed by serial operations described below. First, as a basic idea, a value represented by a ratio of integers as shown in Expression 1 is converted to a power of two as shown in Expression 5 (that is, n of 2).
To the sum or difference of the powers).

(Equation 5) The reason why the numerical value is expressed by a power of 2 as shown in Expression 5 is to realize an operation by a serial circuit. That is, in FIG. 34, reference numeral 271 denotes an FF that responds to a clock input signal and outputs the input signal delayed by one clock.
(Flip-flop), one time delay unit 27
Output coming out through 1 and 1 time delay unit 2
Compared with the output directly coming out without passing through 71, the former is one clock later than the latter. Here, the one time delay unit 271 has a structure in which shift registers are arranged. For example, if data is sequentially input from the LSB side, it means that one data delay comes out one clock later.
Means doubled. Similarly, the 8-fold in 2 ³ If to delay three side by side three clocks, as shown in FIG. 35 the one time delay unit 271 when to be eight times. In this embodiment, a serial operation circuit is realized by performing addition and subtraction by combining the above units.

FIG. 36 shows a serial operation configuration of the multiplication unit. FIG. 36 shows an example in which input data is multiplied by 38. First, 38 is decomposed into the form of Equation 6.

(Equation 6) In Equation 6, multiplying a certain numerical value x by 32 means that
This means that x is shifted to the left (in the MBS direction) five times. In FIG. 36, this is realized by passing through one time delay unit 271 of five stages. In addition, since 2 × (2 + 1) shown in Expression 6 is actually 6, 4 + 2
May be expressed as However, the full adder 272 in FIG. 36 has one time delay unit, and employs the expression form 2 × (2 + 1) to double the input data. FIG. 37 shows the circuit configuration as described above applied to the entire Z stage, and is a circuit configuration diagram for performing serial operation on the data conversion unit 241 in FIG. Also,
38 to 40 are diagrams showing each unit in FIG. 37. FIG. 38 is a diagram showing one time delay unit 2 composed of FF.
FIG. 39 shows a one time delay unit full adder (internal carry type) 272 for performing addition (a + b),
FIG. 40 shows one time delay unit full subtractor (internal Borrow type) 273 for performing subtraction (ab). In FIG. 37, a one-time delay unit not related to the calculation is added for the purpose of positioning the decimal point. For example, the integer value 7 in x ₁ data conversion unit 241 of FIG. 32 (4 + 2 + 1)
In FIG. 37, one time delay unit 271 and two full adders 272 are combined. Similarly, all the numerical values shown in FIG. 32 can be realized by a serial circuit as shown in FIG.
T can be realized by a serial operation. In this case, since each of the units 271, 272, and 273 can be realized by an extremely small circuit having about one FF, the circuit scale of the entire LOT arithmetic device can be reduced.

Also, the same serial operation can be performed at the time of reverse LOT as at the time of LOT. FIG. 41 is a circuit configuration diagram in which the inverse data conversion unit 252 of FIG. 33 is performed by a serial operation, and the same serial operation as in FIG. 37 is executed.

FIG. 42 is a circuit diagram of the serial operation circuit of FIG.
7 is a timing chart when 9-bit (sign + Data8) data shown in FIG. 3 is input. As shown in FIG.
At the time of inputting bit data, the next 9-bit data can be input after 24 (9 + 15) time units have elapsed. Therefore, one cycle of data input is 24 time units. In general, data can be input at an n + 15 time unit cycle for an n-bit input.

The reverse LOT will be described.
It can be considered that the data itself flows from right to left in the LOT flow graph of FIG. 30 (see FIG. 29). Considering the Z stage 232 and the Y stage 231, the Z stage 232 and the Y stage 231 are symmetric except for the gain of the Z stage 232. If the gain of the Z stage 232 is previously absorbed at the time of inverse quantization as in the case of LOT, the Z stage 232 and Y
The stages 231 may be combined as shown in FIG. However, y input was x ₁ in FIG. 37
_7, a y ₅ in x _3, the y ₃ in x _5, the y ₁ is input to the x _7, so that'll twisted equally to the output. Also,
FIGS. 45 and 46 show the overall configuration considering the reverse LOT. FIG. 45 shows the data flow at the time of LOT, and FIG. 46 shows the data flow at the time of reverse LOT.

As described above, in this embodiment, the inverse L
In consideration of the time of OT, two Z stages are provided, but as shown in FIG.
If a memory is provided in that portion, the circuit scale can be reduced. In this case, an operation of temporarily storing data in the memory is added, so that high-speed operation may be lost. However, when the LOT operation is continuously performed, the data always passes through the previous Z stage. Since the data is held, the execution time itself hardly changes.

In this embodiment, the coefficient is, for example, 7: 3
Although an example in which the ratio is an integer of is shown, the present invention is not limited to this.
Any integer ratio may be used as long as it is represented by an integer ratio.

The operation coefficient is expressed by a sum (difference) of a power of 2 (2 to the n-th power), and the operation is performed by a serial circuit as shown in FIG. 37. Of course, any combination of units may be used.

As described above, in the third embodiment, the LOT operation and the inverse LOT operation in the image compression / decompression circuit are performed by serial operation.
When the LOT operation is performed by using a circuit, the circuit scale is very large and the execution time is long. However, the circuit scale is significantly reduced because a serial circuit including a combination of extremely small FFs or the like is realized. Can be
In addition, processing can be performed at high speed. It is suitable to apply such a high-speed LOT calculation process with a small circuit scale to an encoded data processing device that performs image compression and audio compression.

In this embodiment, the data converter 214,
The operation coefficient of the inverse data conversion unit 252 is replaced with an integer ratio, and the change in the gain is absorbed by the quantization unit and the inverse quantization unit. The other operations are performed only once, and the other operations can be performed by an integer ratio that does not include a rounding error. This has an effect that high operation accuracy can be obtained with a small bus width.

In each of the above embodiments, the DCT and the Hadamard transform are applied to the image compression / decompression circuit. However, the present invention is not limited to these encoding methods, and any apparatus that performs the LOT operation can be used. Needless to say, this can also be applied. For example, the present invention can be applied to an encoded data processing device using a Harr transform, a gradient transform (slant transform), a symmetric sine transform, or the like.

[0064]

According to the first aspect of the present invention, the encoding process
At the time of processing, the first computing means
To perform the basic function compensation operation on the
Primitive compensation for more vertically adjacent blocks
The operation is performed, so the adjacent block
Distortion can be appropriately removed.

[0065]

[0066]

[Brief description of the drawings]

FIG. 1 is a block diagram of an electronic camera according to the present invention.

FIG. 2 is a screen configuration diagram of the electronic camera according to the present invention.

FIG. 3 is a configuration diagram of a LOT calculation device of the electronic camera according to the present invention.

FIG. 4 is a diagram showing a computing unit for butterfly computation of the LOT computing device of the electronic camera according to the present invention.

FIG. 5 is a diagram illustrating a computing unit for butterfly computation of the LOT computing device of the electronic camera according to the present invention.

FIG. 6 is a diagram showing a computing unit for butterfly computation of the LOT computing device of the electronic camera according to the present invention.

FIG. 7 is a diagram showing a computing unit for butterfly computation of the LOT computing device of the electronic camera according to the present invention.

FIG. 8 is a diagram showing input / output pixels of the LOT calculation device of the electronic camera according to the present invention.

FIG. 9 is a block diagram of the LOT operation device according to the first embodiment.

FIG. 10 is a diagram for explaining LOT calculation of the LOT calculation device according to the first embodiment.

FIG. 11 is a diagram showing an ILOT of the LOT operation device according to the first embodiment;
It is a figure for explaining operation at the time.

FIG. 12 is a diagram illustrating an arithmetic element of the LOT arithmetic device according to the first embodiment.

FIG. 13 is a diagram illustrating an arithmetic element of the LOT arithmetic device according to the first embodiment.

FIG. 14 is a diagram illustrating an arithmetic element of the LOT arithmetic device according to the first embodiment.

FIG. 15 is a diagram illustrating an arithmetic element of the LOT arithmetic device according to the first embodiment.

16 is a block diagram of a Y ₁ stage LOT computation device according to the first embodiment.

17 is a block diagram of a Y ₂ stage LOT computation device according to the first embodiment.

FIG. 18 is a block diagram for explaining a data flow at the time of LOT of the LOT operation device according to the first embodiment.

FIG. 19 is a diagram showing ILOT of the LOT calculation device according to the first embodiment;
FIG. 3 is a block diagram for explaining a data flow at the time.

FIG. 20 is a block diagram of a LOT operation device according to a second embodiment.

FIG. 21 is a diagram illustrating a computing unit for butterfly computation of a LOT computing device according to a second embodiment.

FIG. 22 is a configuration diagram of an X operation unit of the LOT operation device according to the second embodiment.

FIG. 23 is a configuration diagram of a Y operation unit of the LOT operation device according to the second embodiment.

FIG. 24 is a block diagram of a LOT operation device according to a second embodiment.

FIG. 25 shows a two-dimensional X of the LOT calculation device according to the second embodiment.
FIG. 3 is a circuit configuration diagram of a calculation unit.

FIG. 26 shows a two-dimensional X of the LOT calculation device according to the second embodiment.
FIG. 4 is a diagram illustrating a conversion operation by a calculation unit.

FIG. 27 shows a two-dimensional Z of the LOT calculation device according to the second embodiment.
FIG. 3 is a configuration diagram of a calculation unit.

FIG. 28 is a diagram for explaining the operation of each block in the forward direction of the LOT operation device according to the second embodiment.

FIG. 29 is a diagram for explaining the operation of each block in the reverse direction of the LOT operation device according to the second embodiment.

FIG. 30 is a configuration diagram for explaining a calculation at the time of LOT of the LOT calculation device according to the third embodiment.

FIG. 31 is a diagram showing ILOT of the LOT calculation device according to the third embodiment;
FIG. 3 is a configuration diagram for explaining a calculation at the time.

FIG. 32 is a configuration diagram illustrating a data conversion and quantization unit of the LOT operation device according to the third embodiment.

FIG. 33 is a configuration diagram illustrating an inverse data conversion and inverse quantization unit of the inverse LOT operation device according to the third embodiment.

FIG. 34 is a diagram for explaining a serial operation in the LOT operation device according to the third embodiment.

FIG. 35 is a diagram for explaining a serial operation in the LOT operation device according to the third embodiment.

FIG. 36 is a diagram for explaining a serial operation in the LOT operation device according to the third embodiment.

FIG. 37 is a circuit configuration diagram when the data conversion unit of the LOT operation device according to the third embodiment is configured by a serial operation circuit.

FIG. 38 is a diagram illustrating a serial operation element according to a third embodiment.

FIG. 39 is a diagram illustrating a serial operation element according to a third embodiment.

FIG. 40 is a diagram illustrating a serial operation element according to a third embodiment.

FIG. 41 is a block diagram showing a circuit configuration for performing a serial operation of the LOT operation device according to the third embodiment of the present invention.

FIG. 42 is a timing chart of a serial operation of the LOT operation device according to the third embodiment.

FIG. 43 is a diagram illustrating a format of input data to a serial operation element of the LOT operation device according to the third embodiment.

FIG. 44 is an inverse LOT of the LOT calculation device according to the third embodiment;
FIG. 9 is a diagram showing a combination of a Y stage and a Z stage at the time.

FIG. 45 is a block diagram showing a flow of data in a Y stage and a Z stage at the time of LOT of the LOT operation device according to the third embodiment.

FIG. 46 shows a Y stage at the time of reverse LOT of the LOT calculation device.
FIG. 3 is a block diagram illustrating a flow of data in a Z stage.

FIG. 47 is a block diagram showing a data flow at the time of reverse LOT when the number of Z stages of the LOT operation device is one;

FIG. 48 is a diagram for explaining block distortion on a playback screen of a conventional electronic camera.

FIG. 49 is an enlarged view of a noise portion for explaining block distortion of a conventional electronic camera.

[Explanation of symbols]

21, ₁₀₀ LOT arithmetic unit 22 Y ₁ stage (first arithmetic processing unit) 23 Y ₂ stage (second arithmetic processing unit) 24 1 block line memory 25 Z stage 26-33 switch 40 switch switching circuit 101, 102 DCT device 121 LOT operation device 122 Two-dimensional X operation unit (first operation processing unit) 123 Two-dimensional Y operation unit (second operation processing unit) 124 to 126 1 block line memory 127 Two-dimensional Z operation unit 131 to 134 Data latch 135, 136 Adder / subtracter 137 Adder 138 Subtractor 139 Data selector 141, 142 One-dimensional Z operation unit 143, 144 Block buffer 231 Y stage 232 Z stage 240 LOT operation device 241 Data conversion unit 242 Quantization unit 251 Inverse quantization unit 252 Inverse data Conversion unit 271 1 tie Unit delay 272 1 time unit delay full adder 273 1 time unit delay full subtractor 511 Electronic camera 521 Lens system 523 CCD 631 Timing generator 632 CCD driver 524 Process circuit 525 A / D converter 526, 527, 547, 549 Adder 529, 531, 541, 542, 548 Field memory 533 Gamma correction unit 533 534 Enhancer unit 537 Synchronization unit 538 Color difference generation unit 543 Color view finder ROM table 544 Driver 545 Color view finder 546 1H memory 550 External memory 551 ROM table 552 Encoder / Timing generator 553 D / A converter 554 amplifier / buffer 555 contrast detector 600 image Contraction and expansion circuit

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. 2-413515 (32) Priority date December 21, 1990 (December 21, 1990) (33) Priority claim country Japan (JP) (72) Inventor Toru Watanabe 3-2-1, Sakaemachi, Hamura-shi, Tokyo Casio Computer Co., Ltd. Hamura Technical Center (72) Inventor Shigeaki Tomita 3-2-1, Sakaemachi, Hamura-shi, Tokyo Casio Computer Stock (56) References JP-A-4-145727 (JP, A) JP-A-3-295379 (JP, A) JP-A-2-226984 (JP, A) JP-A-1-225293 ( JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/76-5/956 H03M 7/30 H04N 5/232 H04N ^7/ 24-7/68

Claims (2)

(57) [Claims] 1. An electronic camera which performs an encoding process on an image memory by performing block-based encoding processing on captured image data by using an orthogonal transformation with a base function as an orthogonal function, and stores the image data in a block adjacent to a horizontal direction during the encoding process. An electronic camera, comprising: first operation means for performing a basic function compensation operation on the basis of the first operation means; and second operation means for performing a basic function compensation operation on vertically adjacent blocks. 2. The first operation means and the second operation means,
2. The electronic camera according to claim 1 , wherein the electronic camera is means for performing a superposition orthogonal transform (LOT) and an inverse superposition orthogonal transform (ILOT) on the image data using a primitive function for superimposing data between adjacent blocks of the image data. .