JP3096371B2 - Information processing apparatus control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling an information processing apparatus having a read-only memory such as a programmable read-only memory which needs to perform a write operation based on a relatively high-precision clock pulse.

[0002]

2. Description of the Related Art In this specification, the term "power-on" means power supply, and should be interpreted as a concept including a power failure recovery such as a momentary power failure.

Overseas, there is a system for reporting the total sales of stores and the like. According to this notification method, sales data and the like are written in a sealed P-ROM in an electronic cash register with a built-in programmable read only memory (hereinafter abbreviated as P-ROM). The P-ROM in which the sales data and the like are written in this manner is removed with the seal removed in the presence of a government official, and thus the total sales of each store is reported.

[0004] Like the above-mentioned electronic cash register, P-RO
In a device using M as a data memory, PR
Writing / reading of OM data is usually performed by a dedicated control circuit. The data written in such a P-ROM is held without requiring backup of the battery.

A P-R constructed based on silicon
In the OM, in a write operation, the control circuit supplies an address signal and a data signal to be stored to the P-ROM in parallel bits. In this state, the control circuit is, for example, 1
The write operation is performed by giving a write command signal that lasts for a predetermined time of ± 5% to the P-ROM.

If the duration of the write command signal is shorter than the predetermined time, the amount of charge required for writing in the P-ROM is insufficient, and the writing of logic "1" and logic "0" is ensured. Can not be done.

When the duration of the write command signal is longer than the predetermined time, P-
The charge generated during writing to the ROM is lost, and writing cannot be performed.

If the duration of the write command signal slightly deviates from the predetermined time, once written data cannot be held for, for example, 10 years or more.

As described above, it is necessary to output a write command signal of an accurate holding time to the P-ROM. At the traffic light,
A write operation is performed on the P-ROM.

FIG. 4 is a block diagram showing the structure of an electronic cash register 41 according to one embodiment of the prior art. The electronic cash register 41 is installed in a store such as a supermarket and stores sales data, a P-ROM 46, a clock pulse generating circuit 47, a P-ROM control circuit (hereinafter simply referred to as a level discriminating means and a writing means). And a processing circuit 43.

The P-ROM 46 is constructed based on silicon or the like, and in a write operation, a data signal to be stored and an address signal are given in parallel bits. In this state, for example, a write command signal that lasts for a predetermined time of 1 millisecond ± 5% is applied, and data is written.

The P-ROM 46 does not require a backup power source such as a battery, and can hold written data. However, the duration of the write command signal needs to be adjusted to the duration specified in the P-ROM 46 with high accuracy in order to reliably write data and not to deteriorate the data holding ability of the P-ROM 46. .

When such a high-precision write command signal is
Based on a clock pulse generating circuit 47 for generating a high-precision clock pulse,
High-precision write command signal from control circuit 45 is P-RO
Output to M46.

In the electronic cash register 41, the processing circuit 43, the input / output control circuit 48, the control circuit 45, etc.
Power is supplied by the power supply circuit 42. In a normal cash register, the cash registration data input from the key input unit 49 is given to the processing circuit 43 via the input / output control circuit 48, and various processes are performed and stored in the random access memory 52. . Such money registration data and processing results are provided from the processing circuit 43 to the display unit 50 via the input / output control circuit 48, and displayed to the operator and the audience. The processing operation in the processing circuit 43 is executed according to a program stored in the read-only memory 53. Further, the processing circuit 43 controls operations such as opening and closing of the money box 54 and printing of money registration data in the printer 55.

The sales data processed by the processing circuit 43 and stored in, for example, the random access memory 52 is written to the P-ROM 46 as described later. From the processing circuit 43, an address signal and a data signal are led to a control circuit 45 via an interface 44. The control circuit 45 includes a clock pulse generation circuit 47
Interface 4 in synchronization with the clock pulse from
FIG. 5 shows an address signal from the processing circuit 43 via
As shown in FIG. 5A, the data signal to be stored is held as shown in FIG.
Give to 6.

During the time period W1 in which the address signal and the data signal are applied and held, the control circuit 45 operates as shown in FIG.
The write command signal shown by (3) is continuously generated for a period W3 corresponding to the cycle of the clock pulse from the clock pulse generation circuit 47, and is given to the P-ROM 46. The period W3 is, for example, 1 millisecond ± 5%. The duration W1 of the address signal and the data signal output from the control circuit 45 is longer than the period W3, and is derived from the control circuit 45 in 8-bit parallel, for example, and supplied to the P-ROM 46.

The control circuit 45 cannot count clock pulses immediately after power-on because the level of the clock pulse from the clock pulse generation circuit 47 is low. In such a case, the control circuit 45 does not derive the write command signal by the operation described later.

FIG. 6 is a flowchart for explaining the operation of the processing circuit 43. If the power is turned on or the power failure is recovered in step n1, the process proceeds to step n2.

In step n1, for example, if the processing to be executed next to the processing circuit 43 is to write data to the P-ROM 46, the processing circuit 43 outputs signals such as an address signal and a data signal. . If the data has not been written to the P-ROM 46 in step n3, the processing circuit 43 continuously outputs the address signal and the data signal. Step n
In step 3, when the data writing is completed, the flow advances to step n4 to execute the next process.

FIG. 7 is a flowchart for explaining the operation of the control circuit 45. In step m1, when the power is turned on or the power failure is recovered, the flow proceeds to step m2.

In step m2, an address signal, a data signal, a data signal, and the like are output from the control circuit 43, and if writing should be performed, the process proceeds to step m3.

If it is determined in step m2 that writing should not be performed, the flow advances to step m5 to execute other processing. At step m3, it is determined whether the clock pulses output from the clock pulse generation circuit 47 can be counted. That is, when the clock pulse is higher than a predetermined discrimination level, that is, a so-called threshold level, the control circuit 45 can count the clock pulse. If the clock pulse cannot be counted, step m3 is repeated. When the clock pulse can be counted, the process proceeds to step m4. At step m4, the control circuit 45 writes data to the P-ROM 46. When step m4 is completed, the aforementioned step m
2, the same operation is repeated.

[0023]

In the conventional method as described above, the clock pulses are counted, and if the counting can be performed, the oscillation is considered to be stable. However, when the oscillation waveform becomes close to the threshold levels of the high side and the low side of the LSI, the counting is also performed. In order to proceed to the next routine, the clock pulse is immediately used in the next routine, and if the time is monitored, the error may be reduced. There was a possibility. It is an object to improve the timer accuracy as described above, to surely confirm that the clock pulse is stabilized, and to proceed to the next routine.

[0024]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a read-only memory in which data is written by a write command signal, a clock pulse generating circuit for generating a clock pulse, and a clock pulse generating circuit.
Finger to write to read-only memory
Writing means capable of deriving a command signal
In the method for controlling an information processing device, a clock pulse from the clock pulse generation circuit is counted and counted to a specified number.
A first determining step of determining whether or not the
Count ram steps and judge whether it is within specified value
A second determining step, wherein the first determining step
If in response to the output of the second determination step, only when the normal transmission of the clock pulses is confirmed, the write
The means derives a write command signal to the read-only memory based on the clock pulse, and executes a write process.
And a control method of the information processing apparatus.

[0025]

With the above arrangement, the information processing apparatus according to the present invention is provided.
According to the control method , after turning on the power, while keeping the delay to a minimum, immediately after the accuracy of the timer count is determined,
The system can be operated and the accuracy of the timer count is improved, so that the data is written correctly,
In addition, regular storage retention period data can be retained.

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention; The present invention is, of course, not limited to these embodiments. FIG. 1 is a configuration diagram of the device of the present invention. FIG. 2 is a flowchart showing the operation of the present invention, and FIG. 3 clarifies the relationship between a clock pulse and an LSI input necessary for explaining the embodiment of the present invention by clearly indicating a threshold level. The electronic cash register 1 is installed in a store such as a supermarket,
P that stores sales data? And ROM6 a clock pulse generating circuit 7, P-ROM control circuit at a level discriminator hand Dandea Ri writing means (hereinafter, simply referred to as control circuit) 5
And a processing circuit 3. The processing circuit 3
It also has a function of controlling the program step counter 3a that counts program steps. Based on a clock pulse generation circuit 7 for generating a high-precision clock pulse, a high-precision write command signal
Output to OM6.

In the electronic cash register 1, the processing circuit 3, the input / output control circuit 8, the control circuit 5, and the like are energized by the power supply circuit 2. In a normal money registration operation, money registration data input from the key input unit 9 is given to the processing circuit 3 via the input / output control circuit 8,
Various processes are performed and stored in the random access memory 12. Further, such money registration data and processing results are sent from the processing circuit 3 to the display unit 1 via the input / output control circuit 8.
0 and displayed to the operator and the audience. The processing operation in the processing circuit 3 is executed according to a program stored in the read-only memory 13. Processing circuit 3
Controls operations such as opening and closing of the money box 14 and printing of money registration data in the printer 15.

The sales data processed by the processing circuit 3 and stored in, for example, the random access memory 12 is written to the P-ROM 6 as described later.

From the processing circuit 3, an address signal and a data signal are led out to the control circuit 5 via the interface 4. The control circuit 5 holds the address signal from the processing circuit 3 via the interface 4 in synchronism with the clock pulse from the clock pulse generation circuit 7 and
OM6.

As shown in FIG. 2, after the power failure reset routine (after power-on), it is determined whether or not it is a timing to write data to the P-ROM 21. If it is a read timing, the process proceeds to a read routine (if not a write timing) to write. If it is the timing, the program counter is reset 22, and the count-up is executed 23. At the time of counting up, for example, counting is performed until 1 msec elapses, or the like is determined in advance. Judge whether the clock pulse count has reached the specified number count 24; if not, continue counting up; if so, judge whether the program counter is within the specified value 25, reset the program counter if not. Do 22. If it is within the specified value, the timer determines that oscillation has started normally, and proceeds to the next routine.

As described above, for example, when the threshold levels are as shown in FIG. 3, the threshold levels High, L
The recognition of High or Low is undefined inside ow. Since the time in the undefined area is undefined, if the timer count is performed in the undefined area, the accuracy decreases. Therefore, the method of the present invention in which the timer count is not performed until the indeterminate region has passed is more effective.

In this embodiment, the P-ROM 6 is used as the read-only memory.
(Electrically Erasable Pr
programmable-read only memory
y) and other read only memories.

In addition, the present invention is not limited to the embodiment described above and shown in the drawings, and it is needless to say that the present invention can be carried out by appropriately modifying it without departing from the scope of the invention.

[0034]

According to the control method of the information processing apparatus of the present invention, a normal timer pulse can be generated in the shortest time after the power is turned on. It is possible to hold the written and regular storage holding period data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of the device of the present invention.

FIG. 2 is a flowchart showing the operation of the present invention.

FIG. 3 is an explanatory diagram of an embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional device.

FIG. 5 is an explanatory diagram of an embodiment of a conventional device.

FIG. 6 is a flowchart showing the operation of the conventional device.

FIG. 7 is a flowchart showing the operation of the conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electronic cash register 2 Power supply circuit 3 Processing circuit (CPU) 3a Program step counter 4 Interface 5 P-ROM control circuit 6 P-ROM 7 Clock pulse generation circuit 8 Input / output control circuit 9 Key input unit 10 Display unit 12 Random Access memory (RAM) 13 Read only memory (ROM) 14 Money box 15 Printer 43 Processing circuit (CPU) 52 Random access memory (RAM) 53 Read only memory (ROM)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-165509 (JP, A) JP-A-1-173495 (JP, A) JP-A-3-95606 (JP, A) JP-A-63- 67822 (JP, A) JP-A-2-101514 (JP, A) JP-A-61-67151 (JP, A) JP-A-4-147350 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) G11C 16/32 G06F 1/04

Claims (1)

(57) [Claims] 1. A and read-only memory in which data is written by the write command signal, a clock pulse generating circuit for generating a clock pulse, based on said clock pulse
The write command signal to read-only memory
Information processing apparatus provided with writing means capable of performing
The control method of mosquito clock pulses from the clock pulse generating circuit
First judgment to judge whether or not the count has been reached
Steps and program steps are counted and
And a second determination step of determining whether internal or not, in response to an output at said first determination step and the second determination step, only when the normal transmission of the clock pulses is confirmed, the writing means derives a write command signal to the read only memory based on said clock pulse, write
Control of an information processing apparatus characterized in that the processing is performed
How .