JP3091771B2 - Semiconductor device having emitter short-circuit structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar three-terminal semiconductor device having an emitter short-circuit structure in which a buffer layer is interposed between an anode emitter and a base.

[0002]

2. Description of the Related Art Bipolar three-terminal semiconductor devices, such as an electrostatic induction thyristor (SITh), a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT), and a MOS control thyristor (MCT), generate a current when turned off. There is a tailing phenomenon seen in the waveform, that is, a so-called tail current, which is a non-negligible loss source and a factor that increases the turn-off time.

The loss caused by the tail current and the increase in the turn-off time are factors that limit the amount of power that can be handled, the operating frequency, and the like in the application of a bipolar three-terminal semiconductor element to a high-frequency inverter or the like. I have.

One of the methods for reducing the tail current is to short-circuit the emitter and the buffer. This method is called an anode-emitter short-circuit structure in the case of SITh or GTO of a p-type gate, and has a short-circuit effect of suppressing the injection amount of excess carriers and increasing the speed of injection (drawing) in principle. It is a feature.

In the application to devices, when the short-circuit effect is strengthened, the turn-off characteristic is improved, but on the other hand, since there is a trade-off in that the turn-on characteristic is reduced, it is actually important to optimize the short-circuit structure. The present invention relates to the improvement of the short circuit structure.

In the short-circuit structure of a semiconductor device with a buffer, the impurity density of the short-circuit region is equal to or higher than that of the buffer, and the arrangement is made in a unit section (for example, 3 mm in length and width in width) of the device.
(Having a size of 0.5 mm) within a few places, and the interval between short-circuit areas is large.

FIG. 11 is a sectional view of one section of a conventional example of an electrostatic induction (SI) thyristor having an anode-emitter short circuit structure, and FIGS. 12 and 13 are each a sectional view of FIG.
FIG. 3 is a partial sectional view taken along lines II-II ′ and III-III ′. 2 is an n-type high resistance region, 3 is a p-type low resistance region, 4 is p-type
5 is an n-type region, 6 is an n-type low-resistance region, 7 is a short-circuit region made of n-type low resistance, 8 is an n-type medium resistance region (buffer layer), and 2 to 8 are all silicon semiconductor regions. It is.

At the boundary between the layer of the n-type high resistance region 2 and the layer of the n-type region 5, a lattice-like p-type region 4 as shown in FIG. The portion of the n-type high resistance region 2 surrounded by the p-type region 4 is called a channel, and the load current mainly flows through this channel portion.
A layer of the n-type low-resistance region 6 is overlaid on the layer of the n-type region 5, and a cathode electrode 10 is provided on the upper surface thereof.

A layer of an n-type medium resistance region 8 is provided below the layer of the n-type high resistance region 2, and a layer of a p-type low resistance region 3 is overlapped at the lower central portion thereof so as to form a pn junction. As shown in FIG. 3, an n-type low-resistance region is provided in the peripheral portion to form a short-circuit region 7. An anode electrode is formed on the lower surface of the layer composed of the p-type low-resistance region 3 and the short-circuit region 7. 9 is provided so that the short-circuit region 7 is an n-type medium-resistance region 8.
And the anode electrode 9 are short-circuited. The impurity density of short-circuit region 7 is equal to or higher than the impurity density of n-type medium resistance region 8 of the buffer.

Further, the peripheral portions of both the n-type region 5 and the n-type low-resistance region 6 are removed, and the peripheral portion of the lattice-shaped p-type region 4 is exposed.
Is provided. A large number of sections configured in this way are arranged in a single semiconductor substrate to form an SI thyristor. Each such section is, for example, about 0.5 mm wide,
It is very small, about 3 mm in length, and this section is arranged neatly on the semiconductor substrate.

The SI thyristor having the anode short circuit structure has n
The turn-on, turn-off, and turn-on characteristics are changed to the extent that excessive conduction electrons in the high-resistance region 2 and the medium-resistance region 8 flow to the anode electrode 9 via the short-circuit region 7, that is, the short-circuit resistance. In order to make the in-plane distribution of the short-circuit resistance uniform, a method of further reducing the interval between the short-circuit regions is conceivable. However, it is difficult to implement the method because the impurity density of the short-circuit region is high.

At the time of turn-on and in the on-state, the conduction electrons accumulated in the n-type medium resistance region 8 and the n-type high resistance region 2 decrease as the short-circuit resistance decreases. The number of holes injected into the medium resistance region 8 and the n-type high resistance region 2 decreases, and in terms of characteristics, the turn-on time becomes longer and the on-voltage becomes higher. Therefore, the ON characteristics are improved by increasing the short-circuit resistance.

In the turn-off process, the conduction electron injection from the n-type low resistance region 6 stops, and after the depletion layer is formed starting from the junction of the p-type region 4 and the n-type high resistance region 2, the n-type high resistance region is formed. Carriers are accumulated in the non-depleted portions of the resistance region 2 and the n-type medium resistance region 8, and this serves as a tail current source. The smaller the short-circuit resistance, the smaller the accumulated carriers at the beginning of the tail period, and therefore the smaller the peak tail current.

The accumulated conduction electrons flow out to the anode electrode 9 as the short-circuit resistance becomes smaller during the tail period, and the accumulated holes have a component flowing out to the p-type low-resistance region 3. Decay is faster.
That is, in order to shorten the turn-on time and lower the on-voltage, and to reduce the tail current and accelerate the attenuation of the tail current, it is important to optimize the short-circuit structure and thus the short-circuit resistance. Had the following disadvantages:

(1) When an element is manufactured using an n-type high-resistance semiconductor substrate (corresponding to the n-type high-resistance region 2), the lattice-like and short-circuit regions of the p-type region 4 are formed in a photolithographic process. It is necessary to match the pattern between the front surface and the back surface in order to maintain the uniform relationship between them. However, it is difficult to match the patterns accurately, and the plane distance from the above-described channel to the short-circuit region 7 becomes inaccurate. Since the short-circuit region may overlap with the short-circuit region, it is difficult to accurately control the short-circuit resistance.

(2) The short-circuit resistance per unit area between the layer of the n-type medium resistance region 8 and the anode electrode 9 is made uniform regardless of the arrangement of a large number of sections constituting the SI thyristor. It is desirable to keep. As a method for this, it is conceivable to disperse the short-circuit regions so as to reduce the intervals. However, it is difficult to obtain a short-circuit resistance that does not impair the ON characteristics because the impurity density in the short-circuit region is high.

[0017]

Accordingly, an object of the present invention is to provide a static induction thyristor (SITh), a gate turn-off thyristor (GTO), an insulated gate bipolar transistor (IGBT) and a MOS controlled thyristor (MCT).
In a bipolar type three-terminal semiconductor device such as that described above, the trade-off relationship between turn-on characteristics and turn-off characteristics has been improved by optimizing the emitter short-circuit structure in which a buffer layer is interposed between an anode emitter and a base. Another object of the present invention is to provide a semiconductor device having an anode-emitter short circuit structure.

[0018]

Accordingly, the structure of the present invention is as follows. That is, the present invention provides a three-terminal semiconductor having a medium resistance region of a first conductivity type forming a buffer between a high resistance region of a first conductivity type and a low resistance region of a second conductivity type forming an emitter. In the device, the impurity density is lower than the buffer in parallel with the emitter,
A first conductivity type short-circuit region having an impurity density range of 10 ¹¹ to 10 ¹⁵ cm ^-3 is provided, the interval between the short-circuit regions is set to 500 μm or less, and a first short-circuit region is provided between the emitter and the short-circuit region. A semiconductor element having an emitter short-circuit structure, wherein the electrodes are connected, or the short-circuit resistance from the first electrode to the buffer is 0.5 Ω per element unit area. · A semiconductor device having an emitter short-circuit structure characterized by being made to be ² cm ² or more, or wherein the three-terminal semiconductor device is an electrostatic induction thyristor, a gate turn-off thyristor, an insulated gate bipolar transistor. As a semiconductor element having an emitter short-circuit structure, comprising a semiconductor element of any one of a transistor and a MOS control thyristor. Are those having the structure, or alternatively, at least the emitter short-circuit regions of the three-terminal semiconductor element is a carrier lifetime control, and,
It has a structure as a semiconductor element having an emitter short-circuit structure characterized by high resistance.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of the present invention will be described below using numerical values based on specific experimental results.

The short-circuit region has an impurity density of 10 ¹¹ to 10 ¹⁵ cm ⁻³ lower than that of the buffer, thereby increasing the short-circuit resistance of one short-circuit region as compared with the conventional case. Then, the intervals between the short-circuit regions are reduced by distributing the short-circuit regions so that the number of short-circuit regions is larger than in the related art.

The following experiment 1 was conducted to examine the effects of the impurity density and spacing of the short-circuit region on the device characteristics. As a result, the relationship shown in FIG. 5 was obtained for the short-circuit resistance per unit area of the device and switching loss. From this, it can be seen that as the short-circuit resistance decreases, the turn-off loss decreases almost proportionally, and the turn-on loss increases inversely. The short circuit resistance since the increase in turn-on loss is significant at 0.5 Ω · cm ² or less suitable is 0.5 Ω · cm ² or more.

Further, in Experiment 2 below, lifetime control was performed on the same device as in Experiment 1, and the relationship between the turn-on loss and the turn-off loss was examined. The result shown in FIG. 10 was obtained. This shows that the trade-off between the turn-on loss and the turn-off loss is further improved by performing the lifetime control by gold diffusion.

[0023]

[Experiment 1] The basic structure of one section of the SI thyristor used in the experiment on which the present invention was based is shown in FIG. 1 and II in FIG.
FIGS. 2 and 3 are partial cross-sectional views along the line I-III '. 1 to 3 are the same as those shown in FIG. FIG. 4 shows the impurity density distribution of the buffer and the short-circuit region, and reference numerals A, B, and C correspond to those in FIG.

The main structure of the experimental device is as follows.

The chip size is 7 mm × 7 mm,

The size of one section is 0.3 mm × 3 mm,

The longitudinal direction of the channel is parallel to the short side of one section.

The interval between short-circuit areas is w + W = 20-500 μm,

The width of the short-circuit area is about 10 μm,

The thickness of the buffer is about 20 μm,

The thickness of the short-circuit area is about 10 μm,

The short-circuit resistance is obtained by calculating the resistance r _C of the buffer layer and the resistance r _{A of the} short-circuit area in FIG.
Further, the resistance R _S when the number of short circuits per unit area of the element is connected in parallel is determined. Under the experimental conditions, r _A is greater than r _C. Since such a resistance can be easily calculated, it is practical for studying the relationship between the design of the short-circuit structure and the element characteristics. Here, the resistance R _S is obtained. The area of one short-circuit region is defined as S (cm ² ) from FIG. The number n of short circuits in the element area is n = 1 / S (1 / cm ² ). Accordingly, the short-circuit resistance R _S per element unit area can be expressed by the following equation. That is, R _S
= (R _C + r _A ) / n = (r _C + r _A ) S (Ω · cm ² )
Becomes

With the above-described method, a prototype was made in a direction in which the interval between the short-circuit regions was made smaller than before, and the relationship between the short-circuit resistance and the on-voltage and switching characteristics of the element was examined.

FIGS. 6 to 8 show examples of switching waveforms of prototype elements having different short-circuit resistances. FIG. 5 shows the relationship between the turn-on loss and the turn-off loss obtained from such a switching waveform and the short-circuit resistance. This indicates that the turn-off loss is directly proportional to the short-circuit resistance, and the turn-on loss is inversely proportional to the short-circuit resistance.

Based on the results of trial production of an SI thyristor having a short-circuit structure in which the impurity density in the short-circuit region is reduced and the interval between the short-circuit regions is reduced, it is possible to adjust the ratio of the turn-on and turn-off losses using the short-circuit resistance as an index. Good.

If the short-circuit resistance is too small, the turn-on time becomes longer and the loss increases, so that a short-circuit resistance of 0.5 Ω · cm ² or more is suitable for practical use.

[Experiment 2]

Lifetime control is performed on the SI thyristor used in Experiment 1.

The SI thyristors III to II shown in FIG.
Gold diffusion is performed from the I 'side. The diffusion temperature was at most 850 ° C.

FIG. 9 shows an example of a switching waveform in a case where gold diffusion is further performed on a device having a short-circuit resistance of 2.3 Ω · cm ² under predetermined conditions. FIG. 10 illustrates a trade-off relationship between these losses using the turn-on loss and the turn-off loss obtained from such a switching waveform. The parameter is the gold diffusion temperature.

It is effective to improve the trade-off between the turn-on characteristic and the turn-off characteristic by further controlling the lifetime by gold diffusion for an element in which the impurity density in the short-circuit region is reduced and the interval between the short-circuit regions is reduced. It is.

It can be seen from the result of the spreading resistance measurement that the resistivity of the short-circuit region after gold diffusion increases compared to that before gold diffusion. The fact that the element is easily turned on by the increase in the short-circuit resistance is apparent from the relationship between FIG. 5 and the fact that the injection of holes by the voltage generated at the short-circuit resistance is promoted. On the other hand, it is well known that when the lifetime of a carrier is reduced, the turn-off characteristic is improved. The combination of the above two effects improves the trade-off relationship between turn-on and turn-off.

The above manufacturing conditions can be selected from those shown in Experiments 1 and 2 according to the target characteristics of the device. Furthermore, radiation such as proton irradiation can be used as a lifetime control method.

[0043]

According to the present invention, the in-plane characteristic distribution of a large-area semiconductor element in which a number of fine unit elements are integrated in parallel can be made uniform, thereby providing an effective method for improving the characteristics of the entire element. In designing a short-circuit structure, a method of adjusting the balance between the ON and OFF characteristics of the element can be provided by using the short-circuit resistance, which can be easily calculated, as an index. Further, by implementing the lifetime control, it is possible to provide an effective method for improving the trade-off between the turn-on characteristic and the turn-off characteristic.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of one section of an electrostatic induction thyristor, and is an explanatory view of a short-circuit structure of the present invention.

FIG. 2 is a plan layout view of a short-circuit region of FIG. 1;

FIG. 3 is a plan layout view of a short-circuit area of FIG. 1;

FIG. 4 is an impurity density distribution diagram of the short-circuit structure of the present invention;
The horizontal axis corresponds to the sectional structural view of FIG.

FIG. 5 is an experimental result showing a relationship between resistance in a short-circuit region of the short-circuit structure of the present invention and switching loss of an element.

FIG. 6 is a switching waveform diagram of a representative element in the experiment of FIG.

FIG. 7 is a switching waveform diagram of a representative element of the experiment of FIG.

8 is a switching waveform diagram of a representative element of the experiment of FIG.

FIG. 9 is a switching waveform of an example in which gold (Au) diffusion is performed for carrier lifetime control in the short-circuit structure element of the present invention.

FIG. 10 is a diagram showing a trade-off relationship between a turn-on loss and a turn-off loss, using lifetime control as a parameter.

FIG. 11 is a cross-sectional structure diagram illustrating a conventional short-circuit structure.

FIG. 12 is a plan layout view of a p-type region in FIG. 11;

FIG. 13 is a plan layout view of a short-circuit area in FIG. 11;

[Explanation of symbols]

 2 n-type high resistance region 3 p-type low resistance region 4 p-type region 5 n-type region 6 n-type low resistance region 7 short circuit region 8 n-type medium resistance region 9 anode electrode 10 cathode electrode 11 gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/74 H01L 29/744 H01L 29/78 H01L 29/80

Claims (4)

(57) [Claims] 1. A three-terminal semiconductor having a medium resistance region of a first conductivity type forming a buffer between a high resistance region of a first conductivity type and a low resistance region of a second conductivity type forming an emitter. In the device, the impurity density is lower than that of the buffer, and the impurity density range is 10 ^{11 in} parallel with the emitter.
A short-circuit region of a first conductivity type of about 10 ¹⁵ cm ^-3 , a distance between the short-circuit regions is set to 500 μm or less, and a first electrode is connected to the emitter and the short-circuit region. A semiconductor device having an emitter short-circuit structure. 2. A semiconductor having an emitter short-circuit structure according to claim 1, wherein a short-circuit resistance from said first electrode to said buffer is set to 0.5 Ω · cm ² or more per unit area of the device. element. 3. The semiconductor device according to claim 1, wherein the three-terminal semiconductor device is a semiconductor device selected from the group consisting of an electrostatic induction thyristor, a gate turn-off thyristor, an insulated gate bipolar transistor, and a MOS control thyristor. 3. A semiconductor device having an emitter short-circuit structure according to claim 2. 4. The device according to claim 1, wherein at least the emitter short-circuit region of the three-terminal semiconductor element has a controlled carrier lifetime and a high resistance. A semiconductor device having an emitter short-circuit structure.