JP3083768B2 - Super lattice semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a superlattice semiconductor device having a diode type semiconductor element having a superlattice layer and performing an oscillating operation.

[0002]

2. Description of the Related Art A conventional superlattice semiconductor device having a diode-type semiconductor element using a superlattice structure and performing an oscillation operation includes a superlattice doped with impurities and a superlattice not doped with impurities. is there. In the former case, continuous oscillation occurs by carrier excitation by laser light or by applying a certain voltage to two electrodes sandwiching the semiconductor layer. In the latter, continuous oscillation is generated by carrier excitation by laser light.

[0003]

In a conventional semiconductor oscillating device having a superlattice structure, two types of materials having the same lattice constant, mainly GaAs, are used as the superlattice material.
And AlAs is used for the barrier layer. In this system, the possible range of the X level is A, which is the material of the barrier layer.
1As, the carrier moves from the キ ャ リ ア level to X
The voltage at which the Γ-X mixing voltage that can flow into the level, that is, the voltage required for oscillation is determined by the intrinsic value of the material used, and the element design is greatly restricted. Further, in the case of optical excitation, there is a problem that the wavelength of a laser beam that can be used is limited by the absorption edge of GaAs.

An object of the present invention is to provide a superlattice semiconductor device which solves the above-mentioned problems and which can set an applied voltage required for oscillation relatively freely and has a small limitation on the wavelength of incident light upon photoexcitation and which performs an oscillation operation. To provide.

[0005]

According to a first aspect of the present invention, there is provided a superlattice semiconductor device having a superlattice structure in which barrier layers and quantum well layers are alternately stacked between two electrodes. A superlattice semiconductor device comprising a superlattice semiconductor element in which a second semiconductor layer, which is a semiconductor i-layer, is interposed between first and third semiconductor layers, respectively, constituting the superlattice structure. At least one pair of the barrier layer and the quantum well layer are made of materials having different lattice constants from each other, and one of the electrodes has an opening for injecting excitation light for exciting the superlattice semiconductor element. It is characterized by.

The superlattice semiconductor device according to claim 2 is the superlattice semiconductor device according to claim 1, wherein the superlattice semiconductor element is a pin type or a pin type. It is characterized by.

Further, the superlattice semiconductor device according to claim 3 of the present invention has a second semiconductor layer having a superlattice structure in which barrier layers and quantum well layers are alternately stacked between two electrodes. A superlattice semiconductor device provided with an n ⁺ -n ^-- n ⁺ type superlattice semiconductor element in which the superlattice structure is sandwiched between first and third semiconductor layers, respectively. The pair of barrier layers and the quantum well layers are made of materials having different lattice constants from each other, and an opening is formed in one of the electrodes to allow excitation light for exciting the superlattice semiconductor element to enter. Features.

The superlattice semiconductor device according to claim 4 is the superlattice semiconductor device according to claim 1, 2 or 3, wherein the quantum well layer is made of InGaAs or GaAs, and the barrier layer is made of InAlAs. It is characterized by becoming.

Further, in a superlattice semiconductor device according to a fifth aspect, a plurality of superlattice semiconductor elements according to the first, second, third or fourth aspect are formed in an array on a substrate, and One electrode of each of the lattice semiconductor elements is connected to each other, and the other electrodes of the plurality of super lattice semiconductor elements are connected to each other.

According to a sixth aspect of the present invention, there is provided a superlattice semiconductor device, wherein a plurality of superlattice semiconductor elements according to the first, second, third or fourth aspect are formed in a matrix of rows and columns on a substrate.
One electrode of each of the plurality of superlattice semiconductor elements is connected to each other for each row, and the other electrode of each of the plurality of superlattice semiconductor elements is connected to each other for each column.

The superlattice semiconductor device according to claim 7 is the superlattice semiconductor device according to claim 1, 2, 3 or 4, wherein the superlattice semiconductor element and the superlattice semiconductor element are formed on a substrate. An amplifier for amplifying and outputting an output oscillation signal is formed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a superlattice semiconductor device having a superlattice semiconductor element 10 according to an embodiment of the present invention. In the superlattice semiconductor device of this embodiment, the barrier layers 21-0 to 21-N (hereinafter, generically referred to as 21) and the quantum well layer 22 are provided between the two electrodes 11 and 12.
-1 to 22-N (hereinafter, generically referred to as 22) are alternately stacked on the intrinsic semiconductor i layer 15 having a superlattice structure, and the p-type cap layer 13 and the n-type buffer layer 17 are respectively formed. Heterojunction pi sandwiched between
A superlattice semiconductor device including the superlattice semiconductor element 10 which is an n-type diode element, wherein at least one pair of the barrier layer 21 and the quantum well layer 22 constituting the superlattice structure are:
It is characterized by being made of materials having mutually different lattice constants.

In the prior art superlattice semiconductor device, it was necessary to apply a reverse bias voltage of 1 V or more in order to obtain oscillation, but in the present embodiment, it is realized with a bias voltage near 0 V. As shown in FIG. 1, the superlattice semiconductor element 10 of the present embodiment has a flat plate-shaped electrode 12 made of Au on the back surface and n-type impurity ions made of Si, for example, at an implantation amount of 10 ¹⁸ / cm ^3. N-G injected
On an n-type semiconductor substrate 20 made of aAs and having a thickness of 300 μm, the following layers are sequentially laminated from the side close to the n-type semiconductor substrate 20. (A) An n-type impurity ion made of Si
A 50 nm thick n-type buffer layer 17 made of n-GaAs implanted by × 10 ¹⁸ / cm ³ ; (b) a 5 nm thick i made of i-In _0.2 Al _0.8 As
(C) Intrinsic semiconductor i-layer (i-SL) 15 having a superlattice structure and having a thickness of about 300 nm; (d) i having a thickness of 5 nm and made of i-In _0.2 Al _0.8 As
Mold cladding layer 14; (e) p-type impurity ions of Be
A 110 nm-thick p-type cap layer 13 of p-GaAs implanted by × 10 ¹⁸ / cm ³ ; and (f) a ring-shaped Au having an opening 11h penetrating in the thickness direction formed in the center. An electrode 11 consisting of Here, the i-type cladding layer 14 and the p-type cap layer 13 are formed to be thin as described above, and transmit light input from the p-type cap layer 13 side.

The reason why the electrode 11 is formed into a ring shape is as follows.
After the above-mentioned lamination is performed, it is performed by a predetermined etching method. Further, the intrinsic semiconductor i layer 15, for example, as a quantum well layer 22-N is adjacent to the i-type cladding layer 16, a quantum well layer 22 of thickness 5nm of 18 atomic layers becomes at GaAs, an In _0.2 It is formed by alternately stacking 18 atomic layers of 5 nm thick barrier layers 21 of Al _0.8 As, for example, at N = 30 periods (ie, 30 pairs). The electrode 11 is connected to a variable DC power supply 30 having a reverse bias voltage Vb.
Are connected to the electrode 12 via a negative electrode and a positive electrode, a load resistor 32 serving as a load circuit, and a current amplifier 31 that current-amplifies an oscillation signal output from the superlattice semiconductor element 10 and outputs the amplified signal to the load resistor 32. . As a result, a predetermined electric field is applied between the electrodes 11 and 12 of the superlattice semiconductor element 10.

FIG. 2 is an energy band diagram showing the level energy with respect to the position in the thickness direction of the intrinsic semiconductor i-layer 15 of the superlattice semiconductor device 10 of FIG. 1, and FIG. FIG. 10 is an energy band diagram showing level energies at respective points of the intrinsic semiconductor i-layer 15 when a reverse bias voltage Vb is applied to FIG.

In FIGS. 2 and 3, Γ denotes a point at the lower end of the conduction band in the wave vector k space when the wave vector k = 0 or (000) in the quantum well layer 22, and X denotes a barrier layer. At 21, the wavenumber vector k =
This is the point at the bottom of the conduction band in the wave vector k-space when (100) is reached. The X points of the first level, the second level,... When the barrier layer 21 is not a bulk type semiconductor are shown as X1, X2,. 1st level, 2nd level, ...
Points are indicated as # 1 point, # 2 point, ... respectively. Here, the X point is divided into an Xz point in the z-axis direction parallel to the direction connecting the two electrodes 11 and 12 and an Xxy point in the xy plane direction perpendicular to the z-axis direction. Think.
2 and 3, Γ2 (0) indicates Γ2 point in the quantum well layer 22-0, Γ2 (1) indicates Γ2 point in the quantum well layer 22-1, and so on.
Xz1 (+ ／), Xz2 (+ ／), Xxy1
(+1/2) is the Xz in the barrier layer 21-0.
1 point, Xz2 point, Xxy1 point, and Xz1 (-1 /
2), Xz2 (-1/2), and Xxy1 (-1/2) are the Xz1 point, the Xz2 point, and the Xz1 point in the barrier layer 21-1, respectively.
Xxy1 point, and so on.

In the superlattice semiconductor device 10 of this embodiment, the intrinsic semiconductor i-layer 15 which is a superlattice layer is formed by using a combination of materials having different lattice constants.
Utilize the strain in the superlattice. For example, the lattice constant of GaAs is 5.66, while the lattice constant of In _0.2 Al _0.8 As is 5.74. Since the 歪 み -band edge of the quantum well layer 22 and the X-band edge of the barrier layer 21 can be changed by the effect of the distortion, the Γ-X mixing voltage can be set freely, and the degree of freedom of the voltage required for oscillation can be reduced. It can be larger.

In the superlattice semiconductor device configured as described above, the electrodes 11, 1 at both ends of the superlattice semiconductor element 10 are provided.
2 applies an electric field in a direction perpendicular to the superlattice, and the accelerated electrons travel to the adjacent quantum well layer 22 by the tunnel effect. , Some electrons flow into the X level and are trapped there. In the superlattice semiconductor device 10 of the present embodiment, the adjacent Γ1 level in the superlattice and each X level, or each X level, intersect near 0 volt (indicated by P in FIG. 3). An electron trapped at the X level generally has a long relaxation time, and it takes a long time to escape therefrom. Therefore, at a voltage at which the X level resonates with another level, electron conduction is significantly impaired, the electron drift speed drops sharply, and a negative differential drift speed is realized. In a region where the negative differential drift velocity is realized, the distribution of the electric field domain becomes unstable and causes oscillation. Therefore, current oscillation occurs at a frequency synchronized with the vibration. The oscillation signal of the current oscillation is amplified by the current amplifier 31 and output to the load resistor 32 which is a load circuit.

In the present invention, various materials can be used for the intrinsic semiconductor i-layer 15 which is a superlattice layer. In this embodiment, GaAs is used for the quantum well layer 22 and In _x is used for the barrier layer 21. Al _(1-x) As (where 0 <x
Taking the structure using <1) as an example, the barrier layer 21 of I
When the _nx Al _(1-x) As layer is subjected to compressive strain, two types of X band edges (X _z point and X
_(xy point) is split, and the band edge thereof is lower than that of the unstrained superlattice used in the conventional superlattice semiconductor device. The band edge of the point X in the barrier layer 21 is In _x
It can be changed by the In composition ratio x, the quantum well width, and the barrier width in Al _(1-x) As, and the positional relationship between the Γ level and the X level changes accordingly. Can be set freely.

In this embodiment, the quantum well layer 22 made of GaAs is used, but the present invention is not limited to this.
As the material of the quantum well layer 22, instead of GaAs, In _x
Ga _(1-x) As (0 <x <1) may be used. In this case, the bandgap energy can be reduced by increasing the composition ratio x of In, so that the superlattice semiconductor element 10 can be excited with longer wavelength excitation light or laser light.
The carrier inside can be excited and continuous oscillation becomes possible.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present inventor produced the superlattice semiconductor device of the embodiment shown in FIG. First, FIG. 4 shows a current characteristic with respect to a reverse bias voltage Vb applied to the superlattice semiconductor element 10 when optically excited by an argon laser having an intensity of about 5 mW.

As is apparent from FIG. 4, for example, when the reverse bias voltage Vb is -1.5 V to -0.3 V and the electric field is relatively low, electrons are accelerated by the electric field, so that the current increases. doing. However, when the reverse bias voltage Vb becomes -0.3 V or more, the current value sharply decreases. This is because the current value is almost proportional to the drift speed, that is, the superlattice semiconductor device of the present embodiment shows a negative differential drift speed at a reverse bias voltage of −0.3 V or more.

FIG. 5 shows a temporal change of the photocurrent when the reverse bias voltage Vb is changed under the same excitation conditions as in FIG. In FIG. 5, the current offset is changed for each reverse bias voltage Vb. As is clear from FIG. 5, the photocurrent oscillates temporally in the region where the reverse bias voltage Vb is -0.3 to 0.1 V, and the superlattice semiconductor element 10 oscillates.

As described above, according to the present embodiment, the intrinsic semiconductor i-layer having a superlattice structure in which the barrier layers 21 and the quantum well layers 22 are alternately stacked between the two electrodes 11 and 12. 15 each having a p-type cap layer 13 and an n-type buffer layer 17 interposed therebetween.
In a superlattice semiconductor device provided with an n-type superlattice semiconductor element 10, at least a pair of barrier layers 21 and quantum well layers 22 constituting the superlattice structure are made of materials having mutually different lattice constants. With such a configuration, it is possible to provide a superlattice semiconductor device which can relatively freely set an applied voltage required for oscillation and has a small limitation on the wavelength of incident light upon light excitation and performs an oscillation operation. For example, by setting the bias voltage near 0 V, a superlattice semiconductor device with low voltage and low power consumption can be realized. In the present embodiment, it was shown that the oscillation at about 0 volt with extremely low power consumption was obtained by lowering the X band edge due to the effect of the distortion.
By changing the n composition ratio, the width of the quantum well layer 22 and the width of the barrier layer 21, it is possible to realize oscillation at an arbitrary voltage value.

<First Modification> In the above embodiment, the superlattice semiconductor device 10 is a pin type diode device having a superlattice layer made of GaAs / In _x Al _(1-x) As. Although described, the present invention is not limited to this, n-i-n-type superlattice semiconductor element or n ⁺ -n shown in Table 1 and Table 2 - may be ^{-n +} -type superlattice semiconductor element . In Tables 1 and 2, the composition ratio is not limited to this. The composition of the superlattice layer may be the material shown in Table 3. In Table 3, the composition ratio is not limited to this. Also in the above modified example, the same operation and effect as the above embodiment can be obtained.

[0027]

[Table 1] Nin-type superlattice semiconductor device ─────────────────────────────────── layer Or substrate composition thickness impurity doping amount (/ cm ³ ), impurity ──────────────────────────────────キ ャ ッ プ cap layer 13 n-GaAs 110 nm 5 × 10 ¹⁸ , Si cladding layer 14 i-In _0.2 Al _0.8 As 5 nm semiconductor i layer 15 GaAs / 5 nm In _0.2 Al _0.8 As 5 nm period N = 30 cladding layer 16 i-In _0.2 Al _0.8 As 5 nm buffer layer 17 n-GaAs 50 nm 2 × 10 ¹⁸ , Si semiconductor substrate 20 n-GaAs 300 μm 10 ¹⁸ ───────────────────────── ──────────

[0028]

[Table 2] n ⁺ −n ⁻ −n ⁺ type superlattice semiconductor device ─────────────────────────────────層 Layer or substrate composition Thickness Impurity doping amount (/ cm ³ ), impurity ───────────────────────────────キ ャ ッ プ Cap layer 13 n ⁺ -GaAs 110 nm 5 × 10 ¹⁸ , Si clad layer 14 n ⁻ −In _0.2 Al _0.8 As 5 nm 1 × 10 ¹⁷ , Si semiconductor i layer 15 n ⁻ −GaAs / 5 nm 1 × 10 ^{17 _{, Si n - -In 0.2 Al 0.8}} As 5nm 1 × 10 17, Si cycle n = 30 cladding layer _{^{16 n - -In 0.2 Al 0.8 As}} 5nm 1 × 10 17, Si buffer layer 17 n ⁺ -GaAs 50nm 2 × 10 ^18, Si semiconductor substrate ^{20 n + -GaAs 300μm 10 18,} Si ───────── ─────────────────────────

[0029]

[Table 3] Composition of superlattice layer ─────────────────────────────────── Quantum well layer 22 / composition Example of ratio Lattice constant in this example Barrier layer 21 ─────────────────────────────────── GaAs / _{5.66 / Al x Ga (1-} x) As y P (1-y) x = 0.5, y = 0.6 5.58 ──────────────────── _{─────────────── In x Ga (1-x} ) As y P (1-y) / x = 0.8, y = 0.85 5.95 / InP 5.87 ─── _{──────────────────────────────── InAs / 6.06 / In x Ga} (1-x) As y P ( _1-y) x = 0.9, y = 0.8 5.98 ─────────────────────────────────── In _x Ga _(1-x) A _{/ X = 0.7 5.94 / In y} Al (1-y) As y = 0.5 5.86 ─────────────────────────── ──────── (Note 1) 0 <x <1, 0 <y <1. (Note 2) The composition of the quantum well layer 22 can be applied to the cap layer 13 and the buffer layer 17, and the composition of the barrier layer 21 can be applied to the cladding layers 14 and 16.

Note that the aperture 1 through which the excitation light is incident on the electrode 11
It is not necessary to form 1h. In this case, the excitation light is allowed to pass by forming the electrode 11 thin.

<Second Modification> In the above embodiment, the superlattice semiconductor element 10 and the current amplifier 31 are formed on separate substrates, but the present invention is not limited to this. The semiconductor element 10 and the current amplifier 31 (semiconductor element for performing the amplification) may be formed close to each other on the same semiconductor substrate or dielectric substrate. Thereby, transmission loss between the superlattice semiconductor element 10 and the current amplifier 31 can be reduced, and oscillation at a higher frequency can be efficiently amplified.

<Third Modification> In the above embodiment, continuous oscillation can be obtained by carrier excitation with laser light or the like. It is effective to use a superlattice layer having an InGaAs / InAlAs composition in which In is introduced into the quantum well layer 22 of FIG. In this case, a material of InP or InAs is used for the semiconductor substrate 20. Further, in particular, 1.3 μm or 1.5 μm used in optical communication devices and the like.
In order to obtain oscillation by light having a long wavelength of 5 μm, InG
A superlattice layer having the composition of aAsP / InP is used, and the semiconductor substrate 20 is made of an InP material.

<Fourth Modification> FIG. 6 shows a superlattice semiconductor element 10-11, 1 similar to the superlattice semiconductor element 10 of FIG.
FIG. 7 is a circuit diagram of an oscillating circuit when the oscillating circuit of FIG. 6 is formed by using four 0-12, 10-21, and 10-22 in a matrix shape or an array shape of rows and columns. FIG.

As shown in FIGS. 6 and 7, four superlattice semiconductor elements 10-11, 10-12, 10-21, and 10
-22 is a matrix or array of rows and columns,
For example, they are formed on the same dielectric substrate (not shown). Here, the superlattice semiconductor elements 10-11 and 10-1
2 are connected to the strip conductors P1 in the first row.
And superlattice semiconductor elements 10-21 and 1
The electrodes 11 of 0-22 are connected to each other by the strip conductors P2 in the second row. In addition, superlattice semiconductor element 1
The electrodes 12 of 0-11 and 10-21 are connected to each other by a strip conductor N1 in a first row, and the electrodes 12 of the superlattice semiconductor devices 10-12 and 10-22 are connected to each other in a strip conductor N2 of a second row. Connected by Note that, as shown in FIG. 7, the strip conductors P1 and P2 are formed on the insulating film 50 on the strip conductor N1 on the dielectric substrate.
Is formed through. Between the strip conductors P1, P2 and the strips N1, N2, respectively, as in FIG.
Current amplifier (not shown) and load resistance (not shown)
Are connected.

In the oscillation circuit configured as described above, for example, when the excitation light is input only to the superlattice semiconductor element 10-11, an oscillation signal is output between the strip conductor P1 and the strip conductor N1. And, for example,
When the excitation light is input only to the superlattice semiconductor element 10-21, an oscillation signal is output between the strip conductor P2 and the strip conductor N1. That is, by arranging the superlattice semiconductor elements 10 in a two-dimensional array shape, parallel optical data incident on a plane formed by the plurality of openings 11h of the superlattice semiconductor elements 10 is collectively processed in real space. To convert it into an AC electric signal. In this oscillation circuit, the number of elements is m × n (in the examples of FIGS. 6 and 7,
m = 2, n = 2) can be reduced to the number of electrodes (m + n), and the wiring can be simplified.

[0036]

As described above in detail, according to the superlattice semiconductor device of the present invention, the second device having a superlattice structure in which barrier layers and quantum well layers are alternately stacked between two electrodes.
A superlattice semiconductor device comprising a superlattice semiconductor element in which the semiconductor layers are sandwiched between first and third semiconductor layers, respectively, comprising at least one pair of barrier layers constituting the superlattice structure; The quantum well layer is made of a material having a different lattice constant from each other, and forms an opening in one electrode through which excitation light for exciting the superlattice semiconductor element is incident. Here, the superlattice semiconductor element is preferably p
-In type, niin type, or n ⁺ -n ^-- n ⁺ type, and the quantum well layer is preferably made of InGaAs or Ga.
As, and the barrier layer is preferably made of InAlAs.

Therefore, it is possible to provide a superlattice semiconductor device which can relatively freely set an applied voltage required for oscillation and has a small limitation on the wavelength of incident light at the time of photoexcitation and performs an oscillation operation. For example, by setting the bias voltage near 0 V, a superlattice semiconductor device with low voltage and low power consumption can be realized. In the present embodiment, the X-band edge was lowered by the effect of the distortion, and thus it was shown that the oscillation at about 0 volt with very low power consumption was obtained. However, for example, the In composition ratio of the barrier layer 21 or the quantum well Oscillation at an arbitrary voltage value can be realized by changing the width and the like of the layer 22 and the barrier layer 21.

Further, a plurality of the superlattice semiconductor elements are formed in an array, and one electrode of each of the plurality of superlattice semiconductor elements is connected to each other. May be connected to each other. A plurality of the superlattice semiconductor elements are formed in a matrix of rows and columns, one electrode of each of the plurality of superlattice semiconductor elements is connected to each other in each row, and the plurality of superlattice semiconductor elements are connected to each other. The other electrodes of the elements may be connected to each other in each column. Therefore, the parallel optical data can be collectively processed in the real space and converted into an AC electric signal,
In this device, the number of electrodes with respect to the number of elements can be reduced, and wiring can be simplified.

Further, the superlattice semiconductor element and an amplifier for amplifying and outputting an oscillation signal output from the superlattice semiconductor element are formed on the substrate. by this,
Transmission loss between the superlattice semiconductor element and the amplifier can be reduced, and oscillation at a higher frequency can be efficiently amplified. Further, the size of the device can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a superlattice semiconductor device including a superlattice semiconductor element 10 according to an embodiment of the present invention.

FIG. 2 shows an intrinsic semiconductor i of the superlattice semiconductor device 10 of FIG.
FIG. 9 is an energy band diagram showing a level energy with respect to a position in a thickness direction of a layer 15.

FIG. 3 is an energy band diagram showing a level energy at each point of an intrinsic semiconductor i-layer 15 when a reverse bias voltage Vb is applied to the superlattice semiconductor element 10 of FIG.

FIG. 4 is a graph showing current characteristics with respect to a reverse bias voltage Vb applied to the superlattice semiconductor device 10 of FIG.

FIG. 5 is a graph showing a current oscillation waveform of an oscillation circuit including the superlattice semiconductor device 10 of FIG.

6 is a circuit diagram of an oscillating circuit when four superlattice semiconductor elements 10 of FIG. 1 are configured in a matrix or array shape.

FIG. 7 is a perspective view illustrating an appearance of the oscillation circuit of FIG. 6;

[Explanation of symbols]

10,10-11,10-12,10-21,10-2
Reference numeral 2: superlattice semiconductor element, 11, 12: electrode, 13: p-type cap layer, 14: i-type cladding layer, 15: intrinsic semiconductor i-layer having a superlattice structure, 16: i-type cladding layer, 17: n-type Buffer layer, 20: n-type semiconductor substrate, 21-0 to 21-N: barrier layer, 22-0 to 22-N: quantum well layer, 30: variable DC power supply, 31: current amplifier, 32: load resistance.

────────────────────────────────────────────────── ─── Continued on the front page (72) Norifumi Egami, Inventor No. 5, Sanraya, Inaya, Seika-cho, Soraku-gun, Kyoto 5 -172241 (JP, A) JP-A-7-28104 (JP, A) JP-A-8-116074 (JP, A) JP-A-4-296059 (JP, A) JP-A-2-130933 (JP, A) JP-A-9-260691 (JP, A) JP-A-9-36390 (JP, A) JP-A-49-29590 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01S 5/00-5/50 H01L 29/06 H01L 31/10 JICST file (JOIS)

Claims (7)

(57) [Claims] 1. A second semiconductor layer which is an intrinsic semiconductor i-layer having a superlattice structure in which a barrier layer and a quantum well layer are alternately stacked between two electrodes, respectively, as a first and a third semiconductor. A superlattice semiconductor device comprising a superlattice semiconductor element sandwiched between layers, wherein at least one pair of barrier layers and quantum well layers constituting the superlattice structure have materials having different lattice constants from each other. A superlattice semiconductor device, characterized in that an opening is formed in one of the electrodes for receiving excitation light for exciting the superlattice semiconductor element. 2. The superlattice semiconductor device according to claim 1, wherein said superlattice semiconductor element is a pin type or a pin type. 3. A second semiconductor layer having a superlattice structure in which barrier layers and quantum well layers are alternately stacked between two electrodes, with the first and third semiconductor layers interposed therebetween. A superlattice semiconductor device comprising an n ⁺ -n ^-- n ⁺ -type superlattice semiconductor element, wherein at least one pair of barrier layers and quantum well layers constituting the superlattice structure have different lattice constants from each other. A superlattice semiconductor device, characterized in that an opening for receiving excitation light for exciting the superlattice semiconductor element is formed in one of the electrodes. 4. The quantum well layer is made of InGaAs or Ga.
The superlattice semiconductor device according to claim 1, 2 or 3, wherein the barrier layer is made of InAlAs. 5. A plurality of superlattice semiconductor elements according to claim 1, 2, 3, or 4 are formed in an array on a substrate, and one electrodes of the plurality of superlattice semiconductor elements are connected to each other. And the other electrodes of the plurality of superlattice semiconductor elements are connected to each other. 6. A plurality of superlattice semiconductor elements according to claim 1, 2, 3 or 4 are formed on a substrate in a matrix of rows and columns, and each one of said plurality of superlattice semiconductor elements is formed. A superlattice semiconductor device, wherein electrodes are connected to each other for each row, and the other electrodes of the plurality of superlattice semiconductor elements are connected to each other for each column. 7. The superlattice semiconductor element and an amplifier for amplifying and outputting an oscillation signal output from the superlattice semiconductor element are formed on a substrate.
5. The superlattice semiconductor device according to 2, 3, or 4.