JP3082248B2 - Semiconductor logic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to I ² L (Integra)
The present invention relates to a combined semiconductor logic circuit device of a bipolar transistor and a MOS transistor with improved TED (Injection Logic).

[0002]

2. Description of the Related Art The integration degree of a bipolar LSI is MOS-L.
I ² L (injection gate) as a technology that is as high as SI
Is known. This I ² L is a logic circuit composed of a multi-collector vertical bipolar transistor whose base is biased to a horizontal bipolar transistor. For example, Japanese Patent Publication No. Sho 59-7245 discloses that the I ² L is an RS flip-flop circuit. Are described.

FIG. 4 shows a conventional typical I ² L structure. An n ⁺ -type buried layer 2 is formed on a p-type silicon substrate 1.
And n ⁻ type epitaxial layer 3 surrounded by p type color region 4. On the surface of the n ⁻ -type epitaxial layer 3, there are provided a p ⁺ -type impurity diffusion region 5 serving as a base B of the vertical bipolar transistor and a plurality of n ⁺ -type impurity diffusion regions 5 formed in the p ⁺ -type impurity diffusion region 5. Impurity diffusion region 6
Is formed. The n ⁺ type impurity diffusion region 6 functions as multi-collectors C _1, C ₂ and C ₃ . On the surface of the epitaxial layer 3 separated from the p ⁺ -type impurity diffusion region 5, p ⁺
The impurity diffusion region 7 is formed and functions as an emitter of a lateral (lateral) bipolar transistor. The base of the lateral bipolar transistor is common to the emitter of the vertical bipolar transistor, and the base of the vertical bipolar transistor is common to the collector of the horizontal bipolar transistor. The buried layer 2 is extracted through an extraction layer 8.

FIG. 5 shows an equivalent circuit of the device of FIG. The emitter of the multi-collector vertical bipolar transistor Q1 is grounded, and its base is connected to the collector of the horizontal bipolar transistor Q2. In FIG. 4, the p ⁺ -type impurity diffusion region 5 is commonly used. The base of the lateral bipolar transistor Q2 is grounded, and its emitter I
NJ is supplied with current through an external resistor Rext. When the current from the horizontal bipolar transistor Q2 is injected into the base of the vertical bipolar transistor Q1, the vertical bipolar transistor Q1 is turned on.

[0005]

SUMMARY OF THE INVENTION The above-mentioned conventional structure of I
^{In 2} L, the n ⁻ -type epitaxial layer 3 serving as the base of the lateral bipolar transistor is fixed to the ground voltage. Therefore, for example, when the injection current from the lateral bipolar transistor as an injector is to be adjusted, the n ⁻ -type epitaxial layer 3 is connected to the emitter INJ. An external resistor Rext is required. However, when the amount of current to be injected is changed, it is necessary to change the external resistance Rext. Even when a resistive element is provided on the chip, the area on the chip is occupied by the resistance. Therefore, the present invention provides I ²
It is an object of the present invention to provide a semiconductor logic circuit device in which L is improved and the control of the injected current is facilitated.

[0006]

In order to achieve the above-mentioned object, a semiconductor logic circuit device according to the present invention comprises a vertical bipolar transistor and a MOS transistor formed on a semiconductor substrate in close proximity to each other. One of a base and one of a source and a drain of the MOS transistor is formed of a common impurity diffusion region, and a current injected into the vertical bipolar transistor is controlled by the MOS transistor.

[0007]

In the semiconductor logic circuit device of the present invention, a MOS transistor is used in place of the I ² L horizontal bipolar transistor, and current is injected into the base of the vertical bipolar transistor via the MOS transistor. Since the MOS transistor can control the drain-source current according to the gate voltage, the injection current can be controlled.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of the device of the present embodiment.
A buried layer 12 functioning as a part of an emitter of a vertical bipolar transistor is formed on a p ^- type silicon substrate 11.
Is formed. This buried layer 12 is formed of an n ⁺ -type impurity diffusion region. On this buried layer 12, an n ⁻ -type epitaxial layer 13 is laminated. A color region 14 composed of ap ⁺ -type impurity diffusion region is formed in the n ⁻ -type epitaxial layer 13 so as to surround the element, and an n ⁺ -type impurity diffusion region for taking out the emitter electrode Em from the buried layer 12. The take-out region 15 is also formed to penetrate the n ⁻ -type epitaxial layer 13.

On the surface of the n ⁻ -type epitaxial layer 13, p ^{+ serving} as a base B of a vertical bipolar transistor and functioning as a drain of a pMOS transistor is provided.
A type impurity diffusion region 16 is formed. On the surface of the p ⁺ -type impurity diffusion region 16, p ⁺ -type impurity diffusion region 16
, Three n ⁺ -type impurity diffusion regions 17 are formed. Each n ⁺ type impurity diffusion region 17 functions as a collector of a vertical bipolar transistor, and has a collector terminal C _1,
It has a multi-collector structure composed of C ₂ and C ₃ .

A gate electrode 18 is formed on the surface of the n ⁻ type epitaxial layer 13 and at a position facing the end of the p ⁺ type impurity diffusion region 16 via a gate insulating film. The gate electrode 18 is made of, for example, a polysilicon layer. The n ⁻ -type epitaxial layer 13 below the gate electrode 18 serves as a channel formation region, and the p ⁺ -type impurity diffusion region 16 is sandwiched between the channel formation region.
And the p ⁺ -type impurity diffusion region 19 are opposed to each other. This p ⁺ -type impurity diffusion region 19 functions as a source INJ of a MOS transistor for current injection. That is, MO
The S transistor has a p ⁺ -type impurity diffusion region 19 and p ⁺
The type impurity diffusion region 16 is used as a source and a drain, and the amount of current between the source and the drain is made variable according to the gate voltage applied to the gate electrode 18.

The entire surface of the epitaxial layer 13 is covered with an insulating film 20. The insulating film 10 is formed on the p ⁺ -type impurity diffusion regions 16 and 19 and on the n ⁺ -type impurity diffusion region 17.
An opening is formed in the upper region and in the extraction region 15, and the electrodes are connected to each other. FIG. 2 is a plan view of the device of this embodiment, and a cross section taken along line II of FIG. 2 corresponds to FIG. As shown in FIG. 2, the MOS transistor in which the p ⁺ -type impurity diffusion region 19 and the p ⁺ -type impurity diffusion region 16 face each other with the gate electrode 18 interposed therebetween is connected to the collector terminals C _1, C ₂ ,
It is a structure that is disposed on the side of C _3.

FIG. 3 is an equivalent circuit diagram of the device of this embodiment. The emitter terminal Em of the vertical bipolar transistor Q1 having a collector terminal C _1, C _2, C ₃ is grounded, pM with its base terminal B is an input terminal
It is connected to the drain of the OS transistor M1. p
The gate of the MOS transistor M1 is supplied with a voltage ΦG for variably controlling the amount of injected current. A required current is supplied to the source of the pMOS transistor M1, but since the amount of injected current can be controlled by the gate voltage ΦG, an external resistor or the like is not required.

In the device of this embodiment having such a structure, the amount of current injected into the base of the bipolar transistor Q1 is controlled by the gate voltage .PHI.G of the pMOS transistor M1. For this reason, the current supplied to the source INJ of the MOS transistor can be selected relatively freely, and no external resistance or the like is required. Since the resistance element for current control becomes unnecessary, the area on the chip can be effectively utilized, high integration can be achieved, and the problem of heat generation of the resistor can be suppressed. Generally, MOS transistors can be miniaturized more than bipolar transistors. Therefore, MO as an injector
The adoption of the S transistor is advantageous for high integration, and eliminates the base current loss in the lateral bipolar transistor. When not in use, the MOS transistor can be turned off by the gate voltage, and low power consumption can be achieved. Further, when the chip is formed into a bi-CMOS, it is easier to coexist with a bipolar transistor than a MOS logic because it has a bipolar transistor.

In the above-described embodiment, the MOS transistor is a pMOS transistor and the vertical bipolar transistor is an npn type.

Since the semiconductor logic circuit device of the present invention is a logic circuit for controlling the current injected into the base of the vertical bipolar transistor by the MOS transistor as described above, it is necessary to control the injected current. This is advantageous in that high integration, low power consumption, base current loss can be suppressed, and the like.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of an example of a semiconductor logic circuit device of the present invention.

FIG. 2 is a plan view of a main part of the example.

FIG. 3 is an equivalent circuit diagram of the above example.

FIG. 4 is a cross-sectional view showing a conventional I ² L structure.

FIG. 5 is an equivalent circuit diagram of a conventional I ² L.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Silicon substrate 12 ... Embedding layer 13 ... Epitaxial layer 16 ... P ⁺ type impurity diffusion region 17 ... n ⁺ type impurity diffusion region 18 ... Gate electrode 19 ... P ⁺ type impurity diffusion region Q1 ... Bipolar transistor M1 ... pMOS Transistor

Claims (1)

(57) [Claims] 1. A vertical bipolar transistor and a MOS transistor are formed close to each other on a semiconductor substrate, and a base of the vertical bipolar transistor and one of a source and a drain of the MOS transistor are formed of a common impurity diffusion region. A semiconductor logic circuit device, wherein a current injected into a vertical bipolar transistor is controlled by the MOS transistor.